Carles Fernandez
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4916c6c8e8
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Fix member initializations, potential data race conditions, and minor performance issues detected by Coverity Scan
Never throw from main
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2023-12-21 13:57:41 +01:00 |
Marc Majoral
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337c9c7d1f
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set the FPGA page size to 0x1000 for compatibility with the FPGA IP cores compiled for the ZynqMP
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2022-04-19 15:53:00 +02:00 |
Carles Fernandez
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6e96b41025
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Improve constructors: prefer member initializers to member initializations in the constructor body
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2021-10-11 15:13:12 +02:00 |
Carles Fernandez
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2287564752
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Make the address sanitizer happy
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2021-10-01 12:52:29 +02:00 |
Carles Fernandez
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d738d893c6
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Apply clang-format
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2021-01-26 00:14:50 +01:00 |
Carles Fernandez
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d6d1fff743
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Apply clang-tidy fixes when -DENABLE_FPGA=ON
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2021-01-25 22:07:59 +01:00 |
Carles Fernandez
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7308745f05
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Apply more concise file header format
Re-license CMake scripts with BSD-3-Clause
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2020-12-30 13:35:06 +01:00 |
Marc Majoral
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630f1932f2
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The tracking modules determine the uio device file that is assigned to them using the hardware accelerator device name in the FPGA
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2020-11-27 10:51:06 +01:00 |
Carles Fernandez
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499de7a9f1
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Update file headers
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2020-07-28 16:57:15 +02:00 |
Carles Fernandez
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1c4e4d3c67
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Remove all warnings raised by bugprone-* clang-tidy checks in tracking blocks
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2020-07-10 21:13:17 +02:00 |
Carles Fernandez
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09bcd1981c
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Replace std::endl by \n character. There is no need to always flush the stream.
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2020-07-07 18:53:50 +02:00 |
Carles Fernandez
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ce16b0e1a4
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Fix initialization
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2020-02-23 13:45:57 +01:00 |
Carles Fernandez
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649a1d7be6
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cpplint: Do not use variable-length arrays [runtime/arrays]
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2020-02-23 13:39:31 +01:00 |
Carles Fernandez
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4d0d263280
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Make the software package compliant with the REUSE Specification v3.0 (see https://reuse.software/spec/)
Update license headers to SPDX format (see https://spdx.org/)
Add license to all files
Add CI job in GitHub Actions to ensure compliance
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2020-02-08 01:20:02 +01:00 |
Carles Fernandez
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124531ba39
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Accelerate writing of secondary code
And other cosmetic changes
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2019-10-27 22:42:58 +01:00 |
Carles Fernandez
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b4e4c849b1
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More usage of volk_gnsssdr::vector
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2019-10-27 21:34:19 +01:00 |
Marc Majoral
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dbf0c38d37
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applied clang-format
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2019-10-03 16:37:18 +02:00 |
Marc Majoral
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f2b2eb2f1a
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replaced .device_base by .dev_file_num parameter. The .dev_file_num parameter points for each type of GNSS signal, the number of the first uio device file that is used for the tracking process.
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2019-10-03 16:37:18 +02:00 |
Carles Fernandez
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e80122f4ff
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Apply clang tidy checks and clang-format
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2019-09-13 08:56:37 +02:00 |
Marc Majoral
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c2acada665
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the device_base index is now a signed integer.
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2019-08-26 17:59:16 +02:00 |
Carles Fernandez
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4dd8aa12b4
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Replace C style casts by C++ casts
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2019-08-18 12:54:16 +02:00 |
Carles Fernandez
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5f176b084c
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Replace defines by constants and move them to the implementation
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2019-08-14 02:34:00 +02:00 |
Carles Fernandez
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3d146019dd
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Apply modernize-redundant-void-arg clang-tidy fix
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2019-08-14 02:14:29 +02:00 |
Carles Fernandez
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487010346f
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Apply readability-isolate-declaration clang-tidy check
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2019-08-13 00:19:31 +02:00 |
Marc Majoral
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f30d8a60ec
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updated doxygen comments
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2019-07-23 19:05:43 +02:00 |
Marc Majoral
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6ee9fedd76
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moved #defines to static consts + used clang-format + removed code that was commented out
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2019-07-23 15:20:59 +02:00 |
Marc Majoral
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00993d9719
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replaced #defines by static consts + removed unused tracking parameter + removed unnecessary comments
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2019-07-22 19:58:37 +02:00 |
Marc Majoral
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8b0e170a56
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applied clang-format
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2019-07-19 11:55:53 +02:00 |
Marc Majoral
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dd996bc2e2
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Merge branch 'next' of https://github.com/mmajoral/gnss-sdr into fpga_extended_coherent_integration
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2019-07-18 11:35:34 +02:00 |
Carles Fernandez
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19b35b6cef
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Remove cstdio header
See * MISRA C++:2008, 27-0-1 - The stream input/output library <cstdio> shall not be used.
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2019-07-14 00:42:56 +02:00 |
Marc Majoral
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33d1115246
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added support for extended coherent integration in the FPGA. The code still needs to be optimized and cleaned.
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2019-06-18 18:22:01 +02:00 |
Marc Majoral
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e1d01d3b97
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Re-enable uio interrupts manually + do not enable interrupt generation at reset.
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2019-05-13 16:30:01 +02:00 |
Marc Majoral
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585ecf2a84
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removed the activation of the flag that causes the tracking HW accelerators to trigger an interrupt upon reset.
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2019-05-13 16:30:01 +02:00 |
Marc Majoral
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9f80eaf0ff
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code cleanup
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2019-04-12 11:36:30 +02:00 |
Marc Majoral
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91f509abf9
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write the code phase rate and the nco phase rate parameters in the FPGA
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2019-04-10 11:31:34 +02:00 |
Marc Majoral
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19184da0f9
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The FPGA multicorrelator interrupt is enabled only once when a satellite is assigned to a particular channel. Until now the interrupt was automatically disabled by the interrupt handler of the uio driver and the multicorrelator code had to re-enable it every time. This change saves CUP cycles for real-time operation. It requires that the code that disables the interrupt in the uio driver interrupt handler is commented out.
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2019-04-09 16:03:31 +02:00 |
Marc Majoral
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ff024e7292
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cleaned unused code and added some comments.
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2019-04-04 19:55:02 +02:00 |
Marc Majoral
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553946fb65
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moved the setting of the flags for the writing of the local code to the initialization, to save cpu cycles during tracking.
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2019-04-02 20:36:48 +02:00 |
Marc Majoral
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a6110eb334
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moved the calculations related to the local code that is specific to the FPGA to the initialisation phase of the tracking modules to save clock cycles during real-time tracking.
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2019-04-02 18:46:37 +02:00 |
Marc Majoral
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905a85670c
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currently optimizing the FPGA-related code
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2019-03-25 19:45:54 +01:00 |
Carles Fernandez
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08ce4cdd75
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Sort includes, fix coverity scan defect
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2019-03-03 00:15:20 +01:00 |
Carles Fernandez
|
fcfe63ba08
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Fix defects detected by coverity scan
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2019-03-01 20:49:45 +01:00 |
Carles Fernandez
|
e43b8f5284
|
Fix defects detected by Coverity Scan
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2019-03-01 15:29:43 +01:00 |
Carles Fernandez
|
df0a77ee0d
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Fix warnings
more protection on read/write failures and some code cleaning
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2019-03-01 10:11:36 +01:00 |
Carles Fernandez
|
7c71ed9404
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Merge branch 'fpga' of https://github.com/gnss-sdr/gnss-sdr into merge-fpga
Applied checks and formatting
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2019-02-28 21:45:30 +01:00 |
Marc Majoral
|
c32e0b427a
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coding style + removed some unnecessary memory arrays in the FPGA E5A tracking adapter class.
|
2019-02-27 17:27:31 +01:00 |
Marc Majoral
|
a03ed571e6
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replaced int and unsigned int by int32_t and uint32_t
removed some unused variables
|
2019-02-27 14:37:07 +01:00 |
Marc Majoral
|
8d770d9be9
|
more code cleaning
removed some non used variables
|
2019-02-27 13:30:09 +01:00 |
Marc Majoral
|
f127729eb0
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Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga
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2019-01-25 18:02:07 +01:00 |
Marc Majoral
|
7da82dbaea
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updated the FPGA tracking gnuradioblock according to the latest changes in the SW tracking gnuradioblock.
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2018-12-14 18:15:21 +01:00 |