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https://github.com/gnss-sdr/gnss-sdr
synced 2024-12-14 12:10:34 +00:00
removed the activation of the flag that causes the tracking HW accelerators to trigger an interrupt upon reset.
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@ -58,8 +58,8 @@
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#define LOCAL_CODE_FPGA_CLEAR_ADDRESS_COUNTER 0x10000000
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#define LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY 0x0C000000
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#define TEST_REGISTER_TRACK_WRITEVAL 0x55AA
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#define ENABLE_TRK_INT_ON_RESET 1 /* flag that causes the tracking HW accelerator to trigger an interrupt when it is reset. It is used \
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to avoid a potential deadlock caused by the SW waiting for an interrupt from the FPGA when the HW is reset */
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//#define ENABLE_TRK_INT_ON_RESET 1 /* flag that causes the tracking HW accelerator to trigger an interrupt when it is reset. It is used \
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// to avoid a potential deadlock caused by the SW waiting for an interrupt from the FPGA when the HW is reset */
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#ifndef TEMP_FAILURE_RETRY
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#define TEMP_FAILURE_RETRY(exp) \
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({ \
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@ -284,7 +284,7 @@ void Fpga_Multicorrelator_8sc::set_channel(uint32_t channel)
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LOG(INFO) << "Test register sanity check success !";
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}
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d_map_base[INT_ON_RST_REG_ADDR] = ENABLE_TRK_INT_ON_RESET; // enable interrupts on reset to prevent deadlock
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//d_map_base[INT_ON_RST_REG_ADDR] = ENABLE_TRK_INT_ON_RESET; // enable interrupts on reset to prevent deadlock
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// enable interrupts
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int32_t reenable = 1;
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