mirror of
https://github.com/gnss-sdr/gnss-sdr
synced 2024-06-25 22:43:14 +00:00
added support for extended coherent integration in the FPGA. The code still needs to be optimized and cleaned.
This commit is contained in:
Marc Majoral
parent
46979c2197
commit
33d1115246
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@ -134,6 +134,58 @@ void pcps_acquisition_fpga::set_state(int32_t state)
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void pcps_acquisition_fpga::send_positive_acquisition()
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{
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// debug L5
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// d_gnss_synchro->Acq_delay_samples = 2694;
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// d_gnss_synchro->Acq_doppler_hz = 2650;
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// d_gnss_synchro->Acq_samplestamp_samples = 56500224;
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// d_gnss_synchro->Flag_valid_word = 0;
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// d_gnss_synchro->Flag_valid_pseudorange = 0;
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// d_gnss_synchro->Flag_valid_symbol_output = 0;
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// d_gnss_synchro->Flag_valid_acquisition = 0;
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// d_gnss_synchro->Acq_delay_samples = 10846;
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// d_gnss_synchro->Acq_doppler_hz = 2575;
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// d_gnss_synchro->Acq_samplestamp_samples = 399605760;
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// d_gnss_synchro->Flag_valid_word = 0;
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// d_gnss_synchro->Flag_valid_pseudorange = 0;
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// d_gnss_synchro->Flag_valid_symbol_output = 0;
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// d_gnss_synchro->Flag_valid_acquisition = 0;
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// if (d_channel == 0)
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// {
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// d_gnss_synchro->Acq_delay_samples = 401;
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// d_gnss_synchro->Acq_doppler_hz = 2650;
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// d_gnss_synchro->Acq_samplestamp_samples = 96591872;
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// d_gnss_synchro->Flag_valid_word = 0;
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// d_gnss_synchro->Flag_valid_pseudorange = 0;
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// d_gnss_synchro->Flag_valid_symbol_output = 0;
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// d_gnss_synchro->Flag_valid_acquisition = 0;
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// d_gnss_synchro->Acq_delay_samples = 1505;
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// d_gnss_synchro->Acq_doppler_hz = 2575;
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// d_gnss_synchro->Acq_samplestamp_samples = 194265553;
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// d_gnss_synchro->Flag_valid_word = 0;
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// d_gnss_synchro->Flag_valid_pseudorange = 0;
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// d_gnss_synchro->Flag_valid_symbol_output = 0;
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// d_gnss_synchro->Flag_valid_acquisition = 0;
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// }
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// debug E5a
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// d_gnss_synchro->Acq_delay_samples = 2012;
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// d_gnss_synchro->Acq_doppler_hz = -1125;
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// d_gnss_synchro->Acq_samplestamp_samples = 363462656;
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// d_gnss_synchro->Flag_valid_word = 0;
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// d_gnss_synchro->Flag_valid_pseudorange = 0;
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// d_gnss_synchro->Flag_valid_symbol_output = 0;
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// d_gnss_synchro->Flag_valid_acquisition = 0;
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// Declare positive acquisition using a message port
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// 0=STOP_CHANNEL 1=ACQ_SUCCEES 2=ACQ_FAIL
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DLOG(INFO) << "positive acquisition"
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@ -146,6 +198,23 @@ void pcps_acquisition_fpga::send_positive_acquisition()
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<< ", magnitude " << d_mag
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<< ", input signal power " << d_input_power;
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std::cout << "positive acquisition"
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<< ", satellite " << d_gnss_synchro->System << " " << d_gnss_synchro->PRN
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<< ", sample_stamp " << d_sample_counter
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<< ", test statistics value " << d_test_statistics
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<< ", test statistics threshold " << d_threshold
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<< ", code phase " << d_gnss_synchro->Acq_delay_samples
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<< ", doppler " << d_gnss_synchro->Acq_doppler_hz
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<< ", magnitude " << d_mag
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<< ", input signal power " << d_input_power
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<< ", d_gnss_synchro->Acq_samplestamp_samples " << d_gnss_synchro->Acq_samplestamp_samples
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<< ", d_gnss_synchro->Flag_valid_word " << d_gnss_synchro->Flag_valid_word
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<< ", Flag_valid_pseudorange " << d_gnss_synchro->Flag_valid_pseudorange
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<< ", d_gnss_synchro->Flag_valid_symbol_output " << d_gnss_synchro->Flag_valid_symbol_output
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<< ", d_gnss_synchro->Flag_valid_acquisition " << d_gnss_synchro->Flag_valid_acquisition
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<< std::endl;
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//the channel FSM is set, so, notify it directly the positive acquisition to minimize delays
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d_channel_fsm.lock()->Event_valid_acquisition();
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}
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@ -303,6 +303,7 @@ void Fpga_Acquisition::close_device()
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void Fpga_Acquisition::reset_acquisition(void)
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{
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//printf("============ resetting the hw now from the acquisition ===============");
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d_map_base[8] = RESET_ACQUISITION; // writing a 2 to d_map_base[8] resets the acquisition. This causes a reset of all
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// the FPGA HW modules including the multicorrelators
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}
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@ -280,6 +280,7 @@ GalileoE1DllPllVemlTrackingFpga::GalileoE1DllPllVemlTrackingFpga(
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trk_param_fpga.data_codes = d_data_codes;
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trk_param_fpga.code_length_chips = GALILEO_E1_B_CODE_LENGTH_CHIPS;
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trk_param_fpga.code_samples_per_chip = code_samples_per_chip; // 2 sample per chip
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trk_param_fpga.extended_correlation_in_fpga = false;
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//################# MAKE TRACKING GNURadio object ###################
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tracking_fpga_sc = dll_pll_veml_make_tracking_fpga(trk_param_fpga);
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channel_ = 0;
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@ -262,6 +262,14 @@ GalileoE5aDllPllTrackingFpga::GalileoE5aDllPllTrackingFpga(
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trk_param_fpga.data_codes = d_data_codes;
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trk_param_fpga.code_length_chips = code_length_chips;
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trk_param_fpga.code_samples_per_chip = code_samples_per_chip; // 2 sample per chip
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if (d_track_pilot)
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{
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trk_param_fpga.extended_correlation_in_fpga = true;
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}
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else
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{
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trk_param_fpga.extended_correlation_in_fpga = false;
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}
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//################# MAKE TRACKING GNURadio object ###################
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tracking_fpga_sc = dll_pll_veml_make_tracking_fpga(trk_param_fpga);
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channel_ = 0;
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@ -229,7 +229,7 @@ GpsL1CaDllPllTrackingFpga::GpsL1CaDllPllTrackingFpga(
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trk_param_fpga.ca_codes = d_ca_codes;
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trk_param_fpga.code_length_chips = GPS_L1_CA_CODE_LENGTH_CHIPS;
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trk_param_fpga.code_samples_per_chip = 1; // 1 sample per chip
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trk_param_fpga.extended_correlation_in_fpga = false;
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//################# MAKE TRACKING GNURadio object ###################
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tracking_fpga_sc = dll_pll_veml_make_tracking_fpga(trk_param_fpga);
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channel_ = 0;
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@ -286,6 +286,7 @@ GpsL5DllPllTrackingFpga::GpsL5DllPllTrackingFpga(
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trk_param_fpga.data_codes = d_data_codes;
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trk_param_fpga.code_length_chips = code_length_chips;
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trk_param_fpga.code_samples_per_chip = code_samples_per_chip; // 2 sample per chip
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trk_param_fpga.extended_correlation_in_fpga = true;
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tracking_fpga_sc = dll_pll_veml_make_tracking_fpga(trk_param_fpga);
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channel_ = 0;
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DLOG(INFO) << "tracking(" << tracking_fpga_sc->unique_id() << ")";
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File diff suppressed because it is too large
Load Diff
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@ -87,9 +87,12 @@ private:
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void do_correlation_step(void);
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void run_dll_pll();
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void update_tracking_vars();
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void update_tracking_vars_extend_integration_in_FPGA();
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void clear_tracking_vars();
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void save_correlation_results();
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void save_correlation_results_extended_integration_in_FPGA();
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void log_data(bool integrating);
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void log_data_extended_integration_in_FPGA(bool integrating, bool extended_correlation_in_fpga_enabled);
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int32_t save_matfile();
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//void run_state_2(Gnss_Synchro ¤t_synchro_data);
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@ -148,6 +151,9 @@ private:
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gr_complex d_L_accu;
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gr_complex d_VL_accu;
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// gr_complex d_P_data_accu; // when the extended integration is done in the FPGA we need to accumulate the pilot correlator results too
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uint32_t d_num_current_syncrho_repetitions;
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gr_complex *d_Prompt_Data;
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double d_code_phase_step_chips;
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@ -158,6 +164,9 @@ private:
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boost::circular_buffer<std::pair<double, double>> d_carr_ph_history;
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// remaining code phase and carrier phase between tracking loops
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double d_rem_code_phase_samples;
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double d_rem_code_phase_samples_first;
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double d_rem_code_phase_samples_next;
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double d_rem_code_phase_samples_prev;
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float d_rem_carr_phase_rad;
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// PLL and DLL filter library
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@ -184,8 +193,13 @@ private:
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double T_prn_seconds;
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double T_prn_samples;
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double K_blk_samples;
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double K_blk_samples_prev;
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// PRN period in samples
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int32_t d_current_prn_length_samples;
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// REPLACED BY d_correlation_length_samples, d_next_integration_length_samples
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//int32_t d_current_prn_length_samples;
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int32_t d_current_integration_length_samples;
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int32_t d_past_integration_length_samples;
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// processing samples counters
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uint64_t d_sample_counter;
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uint64_t d_acq_sample_stamp;
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@ -204,6 +218,9 @@ private:
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gr_complex *d_Prompt_buffer;
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Exponential_Smoother d_cn0_smoother;
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bool d_extended_correlation_in_fpga;
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// file dump
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std::ofstream d_dump_file;
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std::string d_dump_filename;
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@ -212,8 +229,60 @@ private:
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// extra
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int32_t d_correlation_length_samples;
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int32_t d_next_prn_length_samples;
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//int32_t d_next_prn_length_samples;
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int32_t d_next_integration_length_samples;
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int32_t d_extended_integration_first_prn_length_samples;
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int32_t d_extended_integration_next_prn_length_samples;
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double d_extended_integration_first_acc_carrier_phase_rad;
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double d_extended_integration_next_acc_carrier_phase_rad_step;
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//float d_extended_integration_first_rem_carr_phase_rad;
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//float d_extended_integration_next_rem_carr_phase_rad_step;
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uint64_t d_sample_counter_next;
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// DEBUG STUFF
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uint64_t d_current_synchro_data_Tracking_sample_counter[20];
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double d_current_synchro_data_Code_phase_samples[20];
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double d_current_synchro_data_Carrier_phase_rads[20];
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double d_current_synchro_data_Carrier_Doppler_hz[20];
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double d_current_synchro_data_CN0_dB_hz[20];
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bool d_current_synchro_data_Flag_valid_symbol_output[20];
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int32_t d_current_synchro_data_correlation_length_ms[20];
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double d_current_synchro_data_Prompt_I[20];
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double d_current_synchro_data_Prompt_Q[20];
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double T_prn_samples_prev;
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int32_t d_actual_blk_length;
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bool d_flag_printout;
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std::string *d_secondary_code_string_data;
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std::string *d_secondary_code_string_pilot;
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uint32_t d_secondary_code_length_data;
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uint32_t d_secondary_code_length_pilot;
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uint32_t d_first_length_secondary_code;
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uint32_t d_next_length_secondary_code;
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uint32_t d_debug_counter;
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uint32_t d_secondary_code_post_apply_counter; // init in set_gnss_synchro
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std::string *d_secondary_code_string_post_apply; // init in constructor
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uint32_t d_secondary_code_post_apply_length; // init in constructor
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bool enable_post_apply_secondary_code;
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uint32_t d_secondary_code_debug_counter_whole_bits;
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bool d_sc_remodulate_enabled;
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bool d_sc_demodulate_enabled;
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bool d_sc_prompt_changed;
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float debug_d_rem_carr_phase_rad;
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uint32_t debug_first_time;
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};
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#endif //GNSS_SDR_DLL_PLL_VEML_TRACKING_FPGA_H
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@ -77,4 +77,5 @@ Dll_Pll_Conf_Fpga::Dll_Pll_Conf_Fpga()
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code_samples_per_chip = 0U;
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ca_codes = nullptr;
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data_codes = nullptr;
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extended_correlation_in_fpga = false;
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}
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@ -83,6 +83,7 @@ public:
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uint32_t code_samples_per_chip;
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int32_t* ca_codes;
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int32_t* data_codes;
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bool extended_correlation_in_fpga;
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Dll_Pll_Conf_Fpga();
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};
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@ -119,6 +119,9 @@ Fpga_Multicorrelator_8sc::Fpga_Multicorrelator_8sc(int32_t n_correlators,
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d_code_samples_per_chip = code_samples_per_chip;
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d_code_length_samples = d_code_length_chips * d_code_samples_per_chip;
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d_secondary_code_enabled = false;
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DLOG(INFO) << "TRACKING FPGA CLASS CREATED";
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}
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@ -206,6 +209,23 @@ void Fpga_Multicorrelator_8sc::Carrier_wipeoff_multicorrelator_resampler(
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std::cout << "Tracking_module Read failed to retrieve 4 bytes!" << std::endl;
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std::cout << "Tracking_module Interrupt number " << irq_count << std::endl;
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}
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// release secondary code indices, keep channel locked
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if (d_secondary_code_enabled == true)
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{
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//printf("in the right place\n");
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// debug - force reset counter every time
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//d_map_base[DROP_SAMPLES_REG_ADDR] = ENABLE_SECONDARY_CODE | INIT_SECONDARY_CODE_ADDRESSES;
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d_map_base[DROP_SAMPLES_REG_ADDR] = ENABLE_SECONDARY_CODE; // keep secondary code enabled
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// //printf("do not enable secondary code on purpose\n");
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// d_map_base[DROP_SAMPLES_REG_ADDR] = 0; // block samples
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}
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else
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{
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//printf("in the wrong place\n");
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d_map_base[DROP_SAMPLES_REG_ADDR] = 0; // block samples
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}
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Fpga_Multicorrelator_8sc::read_tracking_gps_results();
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}
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@ -457,8 +477,10 @@ void Fpga_Multicorrelator_8sc::read_tracking_gps_results(void)
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void Fpga_Multicorrelator_8sc::unlock_channel(void)
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{
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// unlock the channel to let the next samples go through
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d_map_base[DROP_SAMPLES_REG_ADDR] = 1; // unlock the channel
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d_map_base[DROP_SAMPLES_REG_ADDR] = DROP_SAMPLES; // unlock the channel and disable secondary codes
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d_map_base[STOP_TRACKING_REG_ADDR] = 1; // set the tracking module back to idle
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d_secondary_code_enabled = false;
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}
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@ -478,3 +500,250 @@ void Fpga_Multicorrelator_8sc::lock_channel(void)
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// lock the channel for processing
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d_map_base[DROP_SAMPLES_REG_ADDR] = 0; // lock the channel
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}
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void Fpga_Multicorrelator_8sc::set_secondary_code_lengths(uint32_t secondary_code_0_length, uint32_t secondary_code_1_length)
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{
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d_secondary_code_0_length = secondary_code_0_length;
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d_secondary_code_1_length = secondary_code_1_length;
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// debug
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//printf("warning extending the code length 0 to 20\n");
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//d_secondary_code_0_length = 20;
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uint32_t secondary_code_length_0_minus_1 = d_secondary_code_0_length - 1;
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uint32_t secondary_code_length_1_minus_1 = d_secondary_code_1_length - 1;
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d_map_base[SECONDARY_CODE_LENGTHS_REG_ADDR] = secondary_code_length_1_minus_1*256 + secondary_code_length_0_minus_1;
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//std::cout << "setting secondary code lengths : \n";
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//std::cout << "initialized correlator 1 sec code length = " << d_secondary_code_1_length << " correlator 0 sec code length = " << d_secondary_code_0_length << std::endl;
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}
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void Fpga_Multicorrelator_8sc::update_secondary_code_length(uint32_t first_length_secondary_code, uint32_t next_length_secondary_code)
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{
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d_map_base[FIRST_PRN_LENGTH_MINUS_1_REG_ADDR] = first_length_secondary_code - 1;
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d_map_base[NEXT_PRN_LENGTH_MINUS_1_REG_ADDR] = next_length_secondary_code - 1;
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//std::cout << " first_length_secondary_code = " << first_length_secondary_code << " next_length_secondary_code = " << next_length_secondary_code << " sum = " << first_length_secondary_code + next_length_secondary_code << std::endl;
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}
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void Fpga_Multicorrelator_8sc::initialize_secondary_code(uint32_t secondary_code, std::string *secondary_code_string)
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{
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uint32_t secondary_code_length;
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uint32_t reg_addr;
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if (secondary_code == 0)
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{
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secondary_code_length = d_secondary_code_0_length;
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reg_addr = PROG_SECONDARY_CODE_0_DATA_REG_ADDR;
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}
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else
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{
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secondary_code_length = d_secondary_code_1_length;
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reg_addr = PROG_SECONDARY_CODE_1_DATA_REG_ADDR;
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}
|
||||
Fpga_Multicorrelator_8sc::write_secondary_code(secondary_code_length, secondary_code_string, reg_addr);
|
||||
|
||||
}
|
||||
|
||||
|
||||
//void Fpga_Multicorrelator_8sc::initialize_secondary_codes(bool track_pilot,
|
||||
// uint32_t secondary_code_length_data, std::string *secondary_code_string_data,
|
||||
// uint32_t secondary_code_length_pilot, std::string *secondary_code_string_pilot)
|
||||
//{
|
||||
// if (track_pilot)
|
||||
// {
|
||||
// // write secondary_code_length_pilot | secondary_code_length_data << 8
|
||||
// d_map_base[SECONDARY_CODE_LENGTHS_REG_ADDR] = secondary_code_length_pilot + secondary_code_length_data*256;
|
||||
//
|
||||
// // write pilot secondary code
|
||||
// Fpga_Multicorrelator_8sc::write_secondary_code(secondary_code_length_pilot, secondary_code_string_pilot, PROG_SECONDARY_CODE_0_DATA_REG_ADDR);
|
||||
//
|
||||
// // write data secondary code
|
||||
// Fpga_Multicorrelator_8sc::write_secondary_code(secondary_code_length_data, secondary_code_string_pilot, PROG_SECONDARY_CODE_1_DATA_REG_ADDR);
|
||||
//
|
||||
// }
|
||||
// else
|
||||
// {
|
||||
// d_map_base[SECONDARY_CODE_LENGTHS_REG_ADDR] = secondary_code_length_data;
|
||||
//
|
||||
// // write data secondary code
|
||||
// Fpga_Multicorrelator_8sc::write_secondary_code(secondary_code_length_data, secondary_code_string_pilot, PROG_SECONDARY_CODE_0_DATA_REG_ADDR);
|
||||
// }
|
||||
//
|
||||
// std::cout << "going to print string " << std::endl;
|
||||
// std::cout << secondary_code_string_data << std::endl;
|
||||
//
|
||||
//
|
||||
//}
|
||||
|
||||
void Fpga_Multicorrelator_8sc::write_secondary_code(uint32_t secondary_code_length, std::string *secondary_code_string, uint32_t reg_addr)
|
||||
{
|
||||
uint32_t num_words = ceil(((float) secondary_code_length)/SECONDARY_CODE_WORD_SIZE);
|
||||
uint32_t last_word_size = secondary_code_length % SECONDARY_CODE_WORD_SIZE;
|
||||
//uint32_t initial_pointer;
|
||||
|
||||
if (last_word_size == 0)
|
||||
{
|
||||
last_word_size = SECONDARY_CODE_WORD_SIZE;
|
||||
}
|
||||
// debug
|
||||
//std::cout << "secondary_code_length = " << secondary_code_length << std::endl;
|
||||
//std::cout << "secondary code string = " << *secondary_code_string << std::endl;
|
||||
//std::cout << "reg_addr = " << reg_addr << std::endl;
|
||||
|
||||
|
||||
// debug
|
||||
//std::cout << "num_words = " << num_words << std::endl;
|
||||
//std::cout << "last_word_size = " << last_word_size << std::endl;
|
||||
|
||||
|
||||
uint32_t write_val = 0U;
|
||||
uint32_t pow_k;
|
||||
uint32_t mem_addr;
|
||||
if (num_words > 1)
|
||||
{
|
||||
for (mem_addr = 0; mem_addr < num_words - 1 ;mem_addr++)
|
||||
{
|
||||
//std::cout << "------------------------------------------------------ going to write word " << mem_addr << std::endl;
|
||||
write_val = 0U;
|
||||
pow_k = 1;
|
||||
for (unsigned int k=0;k<SECONDARY_CODE_WORD_SIZE;k++)
|
||||
{
|
||||
// debug
|
||||
//std::cout << "reading bit position = " << mem_addr*SECONDARY_CODE_WORD_SIZE + k << std::endl;
|
||||
//std::cout << "bit shift = " << pow_k << std::endl;
|
||||
|
||||
std::string string_tmp(1, secondary_code_string->at(mem_addr*SECONDARY_CODE_WORD_SIZE + k));
|
||||
write_val = write_val | std::stoi(string_tmp)*pow_k;
|
||||
|
||||
// debug
|
||||
//std::cout << "computing bit k = " << k << " bit k value = "<< std::stoi(string_tmp) << std::endl;
|
||||
//std::cout << "computing bit k displaced = " << std::stoi(string_tmp)*pow_k << std::endl;
|
||||
//std::cout << "write val = " << write_val << std::endl;
|
||||
|
||||
pow_k = pow_k*2;
|
||||
}
|
||||
|
||||
//std::cout << "writing secondary code reg addr " << reg_addr << "secondary code value " << write_val << std::endl;
|
||||
|
||||
|
||||
// debug
|
||||
//write_val = 0;
|
||||
|
||||
write_val = write_val | mem_addr*SECONDARY_CODE_ADDR_BITS | SECONDARY_CODE_WR_STROBE;
|
||||
d_map_base[reg_addr] = write_val;
|
||||
|
||||
//std::cout << "writing fpga register value " << write_val << std::endl;
|
||||
|
||||
|
||||
// debug
|
||||
// std::cout << "wrote word " << mem_addr << "value is ";
|
||||
// while (write_val) {
|
||||
// if (write_val & 1)
|
||||
// printf("1");
|
||||
// else
|
||||
// printf("0");
|
||||
//
|
||||
// write_val >>= 1;
|
||||
// }
|
||||
// printf("\n");
|
||||
}
|
||||
}
|
||||
write_val = 0U;
|
||||
pow_k = 1;
|
||||
mem_addr = num_words - 1;
|
||||
|
||||
//std::cout << "------------------------------------------------------ going to write word " << mem_addr << std::endl;
|
||||
|
||||
for (unsigned int k=0;k<last_word_size;k++)
|
||||
{
|
||||
// debug
|
||||
//std::cout << "reading bit position = " << mem_addr*SECONDARY_CODE_WORD_SIZE + k << std::endl;
|
||||
//std::cout << "bit shift = " << pow_k << std::endl;
|
||||
|
||||
std::string string_tmp(1, secondary_code_string->at(mem_addr*SECONDARY_CODE_WORD_SIZE + k));
|
||||
write_val = write_val | std::stoi(string_tmp)*pow_k;
|
||||
|
||||
// debug
|
||||
//std::cout << "computing bit k = " << k << " bit k value = "<< std::stoi(string_tmp) << std::endl;
|
||||
//std::cout << "computing bit k displaced = " << std::stoi(string_tmp)*pow_k << std::endl;
|
||||
//std::cout << "write val = " << write_val << std::endl;
|
||||
|
||||
pow_k = pow_k*2;
|
||||
|
||||
}
|
||||
|
||||
// debug
|
||||
//write_val = 0;
|
||||
|
||||
//std::cout << "writing secondary code reg addr " << reg_addr << "secondary code value " << write_val << std::endl;
|
||||
|
||||
write_val = write_val | (mem_addr*SECONDARY_CODE_ADDR_BITS) | (SECONDARY_CODE_WR_STROBE);
|
||||
d_map_base[reg_addr] = write_val;
|
||||
|
||||
//std::cout << "writing fpga register value " << write_val << std::endl;
|
||||
|
||||
|
||||
// // debug
|
||||
// write_val = write_val | 705200;
|
||||
// d_map_base[reg_addr] = write_val;
|
||||
// printf("warning : extending the code length to 20\n");
|
||||
// std::cout << "writing fpga register value " << write_val << std::endl;
|
||||
|
||||
// // debug
|
||||
// //write_val = (SECONDARY_CODE_WR_STROBE) | 0x00055400;
|
||||
// write_val = (SECONDARY_CODE_WR_STROBE) | 0x00000155;
|
||||
// d_map_base[reg_addr] = write_val;
|
||||
// for (unsigned int k=1;k<5;k++)
|
||||
// {
|
||||
// write_val = (k*SECONDARY_CODE_ADDR_BITS) | (SECONDARY_CODE_WR_STROBE) | 0x00055555;
|
||||
// d_map_base[reg_addr] = write_val;
|
||||
// }
|
||||
|
||||
// // debug
|
||||
// std::cout << "wrote word " << mem_addr << " value is " << write_val << " = ";
|
||||
// while (write_val) {
|
||||
// if (write_val & 1)
|
||||
// printf("1");
|
||||
// else
|
||||
// printf("0");
|
||||
//
|
||||
// write_val >>= 1;
|
||||
// }
|
||||
// printf("\n");
|
||||
//printf("\n=============================================================================* END OF THIS\n");
|
||||
}
|
||||
|
||||
//void Fpga_Multicorrelator_8sc::init_secondary_code_indices(void)
|
||||
//{
|
||||
// d_map_base[DROP_SAMPLES_REG_ADDR] = 5; // leave channel unlocked, and init
|
||||
//}
|
||||
|
||||
void Fpga_Multicorrelator_8sc::enable_secondary_codes()
|
||||
{
|
||||
d_map_base[DROP_SAMPLES_REG_ADDR] = INIT_SECONDARY_CODE_ADDRESSES | ENABLE_SECONDARY_CODE; // enable secondary codes and clear secondary code indices
|
||||
d_secondary_code_enabled = true;
|
||||
//std::cout << "enabling secondary codes d_map_base[DROP_SAMPLES_REG_ADDR] = " << (INIT_SECONDARY_CODE_ADDRESSES | ENABLE_SECONDARY_CODE) << std::endl;
|
||||
|
||||
// // debug
|
||||
// printf("do not enable secondary code on purpose\n");
|
||||
// d_map_base[DROP_SAMPLES_REG_ADDR] = 0;
|
||||
}
|
||||
|
||||
void Fpga_Multicorrelator_8sc::disable_secondary_codes()
|
||||
{
|
||||
// this function is to be called before starting the tracking process in order to disable the secondary codes by default
|
||||
//printf("xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx disabling secondary codes in fpga\n");
|
||||
d_map_base[DROP_SAMPLES_REG_ADDR] = DROP_SAMPLES;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -58,6 +58,11 @@
|
|||
#define PHASE_STEP_RATE_REG_ADDR 22
|
||||
#define STOP_TRACKING_REG_ADDR 23
|
||||
#define INT_ON_RST_REG_ADDR 24 // cause interrupt on reset to prevent deadlock
|
||||
#define SECONDARY_CODE_LENGTHS_REG_ADDR 25
|
||||
#define PROG_SECONDARY_CODE_0_DATA_REG_ADDR 26
|
||||
#define PROG_SECONDARY_CODE_1_DATA_REG_ADDR 27
|
||||
#define FIRST_PRN_LENGTH_MINUS_1_REG_ADDR 28
|
||||
#define NEXT_PRN_LENGTH_MINUS_1_REG_ADDR 29
|
||||
#define START_FLAG_ADDR 30
|
||||
// read-write addresses
|
||||
#define TEST_REG_ADDR 31
|
||||
|
|
@ -67,6 +72,13 @@
|
|||
#define SAMPLE_COUNTER_REG_ADDR_LSW 13
|
||||
#define SAMPLE_COUNTER_REG_ADDR_MSW 14
|
||||
|
||||
// FPGA-related constants
|
||||
#define SECONDARY_CODE_WORD_SIZE 20 // the secondary codes are written in to the FPGA in words of SECONDARY_CODE_WORD_SIZE bits
|
||||
#define SECONDARY_CODE_WR_STROBE 0x800000 // write strobe position in the secondary code write register
|
||||
#define SECONDARY_CODE_ADDR_BITS 0x100000 // memory address position in the secondary code write register
|
||||
#define DROP_SAMPLES 1 // bit 0 of DROP_SAMPLES_REG_ADDR
|
||||
#define ENABLE_SECONDARY_CODE 2 // bit 1 of DROP_SAMPLES_REG_ADDR
|
||||
#define INIT_SECONDARY_CODE_ADDRESSES 4 // bit 2 of DROP_SAMPLES_REG_ADDR
|
||||
|
||||
/*!
|
||||
* \brief Class that implements carrier wipe-off and correlators.
|
||||
|
|
@ -93,6 +105,16 @@ public:
|
|||
uint64_t read_sample_counter();
|
||||
void lock_channel(void);
|
||||
void unlock_channel(void);
|
||||
// void initialize_secondary_codes(bool track_pilot,
|
||||
// uint32_t secondary_code_length_data, std::string *secondary_code_string_data,
|
||||
// uint32_t secondary_code_length_pilot, std::string *secondary_code_string_pilot);
|
||||
void set_secondary_code_lengths(uint32_t secondary_code_0_length, uint32_t secondary_code_1_length);
|
||||
void initialize_secondary_code(uint32_t secondary_code, std::string *secondary_code_string);
|
||||
void update_secondary_code_length(uint32_t first_length_secondary_code, uint32_t next_length_secondary_code);
|
||||
void enable_secondary_codes();
|
||||
void disable_secondary_codes();
|
||||
// void init_secondary_code_indices();
|
||||
|
||||
|
||||
private:
|
||||
gr_complex *d_corr_out;
|
||||
|
|
@ -139,6 +161,10 @@ private:
|
|||
|
||||
uint32_t d_multicorr_type;
|
||||
|
||||
uint32_t d_secondary_code_0_length;
|
||||
uint32_t d_secondary_code_1_length;
|
||||
|
||||
bool d_secondary_code_enabled;
|
||||
// private functions
|
||||
uint32_t fpga_acquisition_test_register(uint32_t writeval);
|
||||
void fpga_configure_tracking_gps_local_code(int32_t PRN);
|
||||
|
|
@ -149,6 +175,7 @@ private:
|
|||
void fpga_launch_multicorrelator_fpga(void);
|
||||
void read_tracking_gps_results(void);
|
||||
void close_device(void);
|
||||
void write_secondary_code(uint32_t secondary_code_length, std::string *secondary_code_string, uint32_t reg_addr);
|
||||
};
|
||||
|
||||
#endif /* GNSS_SDR_FPGA_MULTICORRELATOR_H_ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user