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moved #defines to static consts + used clang-format + removed code that was commented out

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This commit is contained in:
Marc Majoral 2019-07-23 15:20:59 +02:00
parent 00993d9719
commit 6ee9fedd76
17 changed files with 69 additions and 144 deletions
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2
src/algorithms/acquisition/adapters/gps_l1_ca_pcps_acquisition_fpga.cc
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@ -47,8 +47,6 @@
#include <cmath> // for abs, pow, floor
#include <complex> // for complex
#define NUM_PRNs 32
GpsL1CaPcpsAcquisitionFpga::GpsL1CaPcpsAcquisitionFpga(
ConfigurationInterface* configuration,
const std::string& role,

7
src/algorithms/acquisition/adapters/gps_l1_ca_pcps_acquisition_fpga.h
View File

@ -155,14 +155,15 @@ public:
void set_resampler_latency(uint32_t latency_samples __attribute__((unused))) override{};
private:
static const uint32_t NUM_PRNs = 32;
// the following flags are FPGA-specific and they are using arrange the values of the fft of the local code in the way the FPGA
// expects. This arrangement is done in the initialisation to avoid consuming unnecessary clock cycles during tracking.
static const uint32_t quant_bits_local_code = 16;
static const uint32_t select_lsbits = 0x0000FFFF; // Select the 10 LSbits out of a 20-bit word
static const uint32_t select_msbits = 0xFFFF0000; // Select the 10 MSbits out of a 20-bit word
static const uint32_t select_all_code_bits = 0xFFFFFFFF; // Select a 20 bit word
static const uint32_t shl_code_bits = 65536; // shift left by 10 bits
static const uint32_t select_msbits = 0xFFFF0000; // Select the 10 MSbits out of a 20-bit word
static const uint32_t select_all_code_bits = 0xFFFFFFFF; // Select a 20 bit word
static const uint32_t shl_code_bits = 65536; // shift left by 10 bits
ConfigurationInterface* configuration_;

7
src/algorithms/acquisition/adapters/gps_l2_m_pcps_acquisition_fpga.cc
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@ -46,13 +46,6 @@
#include <cmath> // for abs, pow, floor
#include <complex> // for complex
#define NUM_PRNs 32
#define QUANT_BITS_LOCAL_CODE 16
#define SELECT_LSBits 0x0000FFFF // Select the 10 LSbits out of a 20-bit word
#define SELECT_MSBbits 0xFFFF0000 // Select the 10 MSbits out of a 20-bit word
#define SELECT_ALL_CODE_BITS 0xFFFFFFFF // Select a 20 bit word
#define SHL_CODE_BITS 65536 // shift left by 10 bits
GpsL2MPcpsAcquisitionFpga::GpsL2MPcpsAcquisitionFpga(
ConfigurationInterface* configuration,
const std::string& role,

7
src/algorithms/acquisition/adapters/gps_l2_m_pcps_acquisition_fpga.h
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@ -156,6 +156,13 @@ public:
void set_resampler_latency(uint32_t latency_samples __attribute__((unused))) override{};
private:
static const uint32_t NUM_PRNs = 32;
static const uint32_t QUANT_BITS_LOCAL_CODE = 16;
static const uint32_t SELECT_LSBits = 0x0000FFFF; // Select the 10 LSbits out of a 20-bit word
static const uint32_t SELECT_MSBbits = 0xFFFF0000; // Select the 10 MSbits out of a 20-bit word
static const uint32_t SELECT_ALL_CODE_BITS = 0xFFFFFFFF; // Select a 20 bit word
static const uint32_t SHL_CODE_BITS = 65536; // shift left by 10 bits
ConfigurationInterface* configuration_;
pcps_acquisition_fpga_sptr acquisition_fpga_;
std::string item_type_;

2
src/algorithms/acquisition/adapters/gps_l5i_pcps_acquisition_fpga.cc
View File

@ -47,8 +47,6 @@
#include <cmath> // for abs, pow, floor
#include <complex> // for complex
#define NUM_PRNs 32
GpsL5iPcpsAcquisitionFpga::GpsL5iPcpsAcquisitionFpga(
ConfigurationInterface* configuration,
const std::string& role,

8
src/algorithms/acquisition/adapters/gps_l5i_pcps_acquisition_fpga.h
View File

@ -41,7 +41,6 @@
#include <string>
#include <vector>
class ConfigurationInterface;
/*!
@ -154,14 +153,15 @@ public:
void set_resampler_latency(uint32_t latency_samples __attribute__((unused))) override{};
private:
static const uint32_t NUM_PRNs = 32;
// the following flags are FPGA-specific and they are using arrange the values of the fft of the local code in the way the FPGA
// expects. This arrangement is done in the initialisation to avoid consuming unnecessary clock cycles during tracking.
static const uint32_t quant_bits_local_code = 16;
static const uint32_t select_lsbits = 0x0000FFFF; // Select the 10 LSbits out of a 20-bit word
static const uint32_t select_msbits = 0xFFFF0000; // Select the 10 MSbits out of a 20-bit word
static const uint32_t select_all_code_bits = 0xFFFFFFFF; // Select a 20 bit word
static const uint32_t shl_code_bits = 65536; // shift left by 10 bits
static const uint32_t select_msbits = 0xFFFF0000; // Select the 10 MSbits out of a 20-bit word
static const uint32_t select_all_code_bits = 0xFFFFFFFF; // Select a 20 bit word
static const uint32_t shl_code_bits = 65536; // shift left by 10 bits
ConfigurationInterface* configuration_;
pcps_acquisition_fpga_sptr acquisition_fpga_;

57
src/algorithms/acquisition/gnuradio_blocks/pcps_acquisition_fpga.cc
View File

@ -40,8 +40,6 @@
#include <utility> // for move
#define AQ_DOWNSAMPLING_DELAY 40 // delay due to the downsampling filter in the acquisition
pcps_acquisition_fpga_sptr pcps_make_acquisition_fpga(pcpsconf_fpga_t conf_)
{
return pcps_acquisition_fpga_sptr(new pcps_acquisition_fpga(std::move(conf_)));
@ -131,54 +129,6 @@ void pcps_acquisition_fpga::set_state(int32_t state)
void pcps_acquisition_fpga::send_positive_acquisition()
{
// debug L5
// d_gnss_synchro->Acq_delay_samples = 2694;
// d_gnss_synchro->Acq_doppler_hz = 2650;
// d_gnss_synchro->Acq_samplestamp_samples = 56500224;
// d_gnss_synchro->Flag_valid_word = 0;
// d_gnss_synchro->Flag_valid_pseudorange = 0;
// d_gnss_synchro->Flag_valid_symbol_output = 0;
// d_gnss_synchro->Flag_valid_acquisition = 0;
// d_gnss_synchro->Acq_delay_samples = 10846;
// d_gnss_synchro->Acq_doppler_hz = 2575;
// d_gnss_synchro->Acq_samplestamp_samples = 399605760;
// d_gnss_synchro->Flag_valid_word = 0;
// d_gnss_synchro->Flag_valid_pseudorange = 0;
// d_gnss_synchro->Flag_valid_symbol_output = 0;
// d_gnss_synchro->Flag_valid_acquisition = 0;
// if (d_channel == 0)
// {
// d_gnss_synchro->Acq_delay_samples = 401;
// d_gnss_synchro->Acq_doppler_hz = 2650;
// d_gnss_synchro->Acq_samplestamp_samples = 96591872;
// d_gnss_synchro->Flag_valid_word = 0;
// d_gnss_synchro->Flag_valid_pseudorange = 0;
// d_gnss_synchro->Flag_valid_symbol_output = 0;
// d_gnss_synchro->Flag_valid_acquisition = 0;
// d_gnss_synchro->Acq_delay_samples = 1505;
// d_gnss_synchro->Acq_doppler_hz = 2575;
// d_gnss_synchro->Acq_samplestamp_samples = 194265553;
// d_gnss_synchro->Flag_valid_word = 0;
// d_gnss_synchro->Flag_valid_pseudorange = 0;
// d_gnss_synchro->Flag_valid_symbol_output = 0;
// d_gnss_synchro->Flag_valid_acquisition = 0;
// }
// debug E5a
// d_gnss_synchro->Acq_delay_samples = 2012;
// d_gnss_synchro->Acq_doppler_hz = -1125;
// d_gnss_synchro->Acq_samplestamp_samples = 363462656;
// d_gnss_synchro->Flag_valid_word = 0;
// d_gnss_synchro->Flag_valid_pseudorange = 0;
// d_gnss_synchro->Flag_valid_symbol_output = 0;
// d_gnss_synchro->Flag_valid_acquisition = 0;
// Declare positive acquisition using a message port
// 0=STOP_CHANNEL 1=ACQ_SUCCEES 2=ACQ_FAIL
DLOG(INFO) << "positive acquisition"
@ -276,13 +226,6 @@ void pcps_acquisition_fpga::acquisition_core(uint32_t num_doppler_bins, uint32_t
}
}
// debug
// if (d_test_statistics > d_threshold)
// {
// printf("firstpeak = %f, secondpeak = %f, test_statistics = %f reported block exp = %d PRN = %d inext = %d, initial_sample = %ld doppler = %d\n", firstpeak, secondpeak, d_test_statistics, (int)total_block_exp, (int)d_gnss_synchro->PRN, (int)indext, (long int)initial_sample, (int)doppler);
// printf("doppler_min = %d doppler_step = %d num_doppler_bins = %d\n", (int)doppler_min, (int)doppler_step, (int)num_doppler_bins);
// }
d_gnss_synchro->Acq_doppler_hz = static_cast<double>(doppler);
d_sample_counter = initial_sample;

16
src/algorithms/acquisition/libs/fpga_acquisition.cc
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@ -44,22 +44,6 @@
#include <utility> // for move
// FPGA register parameters
#define PAGE_SIZE 0x10000 // default page size for the multicorrelator memory map
#define RESET_ACQUISITION 2 // command to reset the multicorrelator
#define LAUNCH_ACQUISITION 1 // command to launch the multicorrelator
#define TEST_REG_SANITY_CHECK 0x55AA // value to check the presence of the test register (to detect the hw)
#define LOCAL_CODE_CLEAR_MEM 0x10000000 // command to clear the internal memory of the multicorrelator
#define MEM_LOCAL_CODE_WR_ENABLE 0x0C000000 // command to enable the ENA and WR pins of the internal memory of the multicorrelator
#define POW_2_2 4 // 2^2 (used for the conversion of floating point numbers to integers)
#define POW_2_31 2147483648 // 2^31 (used for the conversion of floating point numbers to integers)
#define SELECT_LSBits 0x0000FFFF // Select the 10 LSbits out of a 20-bit word
#define SELECT_MSBbits 0xFFFF0000 // Select the 10 MSbits out of a 20-bit word
#define SELECT_ALL_CODE_BITS 0xFFFFFFFF // Select a 20 bit word
#define SHL_CODE_BITS 65536 // shift left by 10 bits
#ifndef TEMP_FAILURE_RETRY
#define TEMP_FAILURE_RETRY(exp) \
({ \

15
src/algorithms/acquisition/libs/fpga_acquisition.h
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@ -116,6 +116,21 @@ public:
void close_device();
private:
// FPGA register parameters
static const uint32_t PAGE_SIZE = 0x10000; // default page size for the multicorrelator memory map
static const uint32_t RESET_ACQUISITION = 2; // command to reset the multicorrelator
static const uint32_t LAUNCH_ACQUISITION = 1; // command to launch the multicorrelator
static const uint32_t TEST_REG_SANITY_CHECK = 0x55AA; // value to check the presence of the test register (to detect the hw)
static const uint32_t LOCAL_CODE_CLEAR_MEM = 0x10000000; // command to clear the internal memory of the multicorrelator
static const uint32_t MEM_LOCAL_CODE_WR_ENABLE = 0x0C000000; // command to enable the ENA and WR pins of the internal memory of the multicorrelator
static const uint32_t POW_2_2 = 4; // 2^2 (used for the conversion of floating point numbers to integers)
static const uint32_t POW_2_31 = 2147483648; // 2^31 (used for the conversion of floating point numbers to integers)
static const uint32_t SELECT_LSBits = 0x0000FFFF; // Select the 10 LSbits out of a 20-bit word
static const uint32_t SELECT_MSBbits = 0xFFFF0000; // Select the 10 MSbits out of a 20-bit word
static const uint32_t SELECT_ALL_CODE_BITS = 0xFFFFFFFF; // Select a 20 bit word
static const uint32_t SHL_CODE_BITS = 65536; // shift left by 10 bits
int64_t d_fs_in;
// data related to the hardware module and the driver
int32_t d_fd; // driver descriptor

5
src/algorithms/signal_source/libs/fpga_switch.cc
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@ -40,11 +40,6 @@
#include <iostream> // for cout, endl
#include <sys/mman.h> // for mmap
// constants
const size_t PAGE_SIZE = 0x10000;
const uint32_t TEST_REGISTER_TRACK_WRITEVAL = 0x55AA;
Fpga_Switch::Fpga_Switch(const std::string &device_name)
{
if ((d_device_descriptor = open(device_name.c_str(), O_RDWR | O_SYNC)) == -1)

6
src/algorithms/signal_source/libs/fpga_switch.h
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@ -39,8 +39,6 @@
#include <string>
#define MAX_LENGTH_DEVICEIO_NAME 50
class Fpga_Switch
{
public:
@ -49,6 +47,10 @@ public:
void set_switch_position(int32_t switch_position);
private:
static const size_t PAGE_SIZE = 0x10000;
static const uint32_t TEST_REGISTER_TRACK_WRITEVAL = 0x55AA;
static const uint32_t MAX_LENGTH_DEVICEIO_NAME = 50;
int d_device_descriptor; // driver descriptor
volatile unsigned* d_map_base; // driver memory map

2
src/algorithms/tracking/adapters/gps_l5_dll_pll_tracking_fpga.cc
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@ -47,8 +47,6 @@
#include <volk_gnsssdr/volk_gnsssdr.h>
#include <array>
#define NUM_PRNs 32 // number of PRNS
GpsL5DllPllTrackingFpga::GpsL5DllPllTrackingFpga(
ConfigurationInterface *configuration, const std::string &role,
unsigned int in_streams, unsigned int out_streams) : role_(role), in_streams_(in_streams), out_streams_(out_streams)

1
src/algorithms/tracking/adapters/gps_l5_dll_pll_tracking_fpga.h
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@ -96,6 +96,7 @@ public:
void stop_tracking() override;
private:
static const uint32_t NUM_PRNs = 32; // total number of PRNs
// the following flags are FPGA-specific and they are using arrange the values of the local code in the way the FPGA
// expects. This arrangement is done in the initialisation to avoid consuming unnecessary clock cycles during tracking.

45
src/algorithms/tracking/libs/fpga_multicorrelator.cc
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@ -43,20 +43,6 @@
#include <sys/mman.h> // for PROT_READ, PROT_WRITE, MAP_SHARED
#include <utility>
// FPGA register access constants
#define PAGE_SIZE 0x10000
#define MAX_LENGTH_DEVICEIO_NAME 50
#define CODE_RESAMPLER_NUM_BITS_PRECISION 20
#define CODE_PHASE_STEP_CHIPS_NUM_NBITS CODE_RESAMPLER_NUM_BITS_PRECISION
#define pwrtwo(x) (1 << (x))
#define MAX_CODE_RESAMPLER_COUNTER pwrtwo(CODE_PHASE_STEP_CHIPS_NUM_NBITS) // 2^CODE_PHASE_STEP_CHIPS_NUM_NBITS
#define PHASE_CARR_MAX 2147483648 // 2^(31) The phase is represented as a 32-bit vector in 1.31 format
#define PHASE_CARR_MAX_div_PI 683565275.5764316 // 2^(31)/pi
#define TWO_PI 6.283185307179586
#define LOCAL_CODE_FPGA_CORRELATOR_SELECT_COUNT 0x20000000
#define LOCAL_CODE_FPGA_CLEAR_ADDRESS_COUNTER 0x10000000
#define LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY 0x0C000000
#define TEST_REGISTER_TRACK_WRITEVAL 0x55AA
#ifndef TEMP_FAILURE_RETRY
#define TEMP_FAILURE_RETRY(exp) \
({ \
@ -246,7 +232,7 @@ bool Fpga_Multicorrelator_8sc::free()
void Fpga_Multicorrelator_8sc::set_channel(uint32_t channel)
{
char device_io_name[MAX_LENGTH_DEVICEIO_NAME]; // driver io name
char device_io_name[max_length_deviceio_name]; // driver io name
d_channel = channel;
// open the device corresponding to the assigned channel
@ -256,9 +242,9 @@ void Fpga_Multicorrelator_8sc::set_channel(uint32_t channel)
devicebasetemp << numdevice;
mergedname = d_device_name + devicebasetemp.str();
if (mergedname.size() > MAX_LENGTH_DEVICEIO_NAME)
if (mergedname.size() > max_length_deviceio_name)
{
mergedname = mergedname.substr(0, MAX_LENGTH_DEVICEIO_NAME);
mergedname = mergedname.substr(0, max_length_deviceio_name);
}
mergedname.copy(device_io_name, mergedname.size() + 1);
@ -270,7 +256,7 @@ void Fpga_Multicorrelator_8sc::set_channel(uint32_t channel)
LOG(WARNING) << "Cannot open deviceio" << device_io_name;
std::cout << "Cannot open deviceio" << device_io_name << std::endl;
}
d_map_base = reinterpret_cast<volatile uint32_t *>(mmap(nullptr, PAGE_SIZE,
d_map_base = reinterpret_cast<volatile uint32_t *>(mmap(nullptr, page_size,
PROT_READ | PROT_WRITE, MAP_SHARED, d_device_descriptor, 0));
if (d_map_base == reinterpret_cast<void *>(-1))
@ -281,7 +267,7 @@ void Fpga_Multicorrelator_8sc::set_channel(uint32_t channel)
}
// sanity check: check test register
uint32_t writeval = TEST_REGISTER_TRACK_WRITEVAL;
uint32_t writeval = test_register_track_writeval;
uint32_t readval;
readval = Fpga_Multicorrelator_8sc::fpga_acquisition_test_register(writeval);
if (writeval != readval)
@ -313,14 +299,14 @@ void Fpga_Multicorrelator_8sc::fpga_configure_tracking_gps_local_code(int32_t PR
{
uint32_t k;
d_map_base[prog_mems_addr] = LOCAL_CODE_FPGA_CLEAR_ADDRESS_COUNTER;
d_map_base[prog_mems_addr] = local_code_fpga_clear_address_counter;
for (k = 0; k < d_code_length_samples; k++)
{
d_map_base[prog_mems_addr] = d_ca_codes[(d_code_length_samples * (PRN - 1)) + k];
}
if (d_track_pilot)
{
d_map_base[prog_mems_addr] = LOCAL_CODE_FPGA_CLEAR_ADDRESS_COUNTER;
d_map_base[prog_mems_addr] = local_code_fpga_clear_address_counter;
for (k = 0; k < d_code_length_samples; k++)
{
d_map_base[prog_mems_addr] = d_data_codes[(d_code_length_samples * (PRN - 1)) + k];
@ -353,7 +339,7 @@ void Fpga_Multicorrelator_8sc::fpga_compute_code_shift_parameters(void)
frac_part = frac_part + 1.0; // fmod operator does not work as in Matlab with negative numbers
}
d_initial_interp_counter[i] = static_cast<uint32_t>(floor(MAX_CODE_RESAMPLER_COUNTER * frac_part));
d_initial_interp_counter[i] = static_cast<uint32_t>(floor(max_code_resampler_counter * frac_part));
}
if (d_track_pilot)
{
@ -370,7 +356,7 @@ void Fpga_Multicorrelator_8sc::fpga_compute_code_shift_parameters(void)
{
frac_part = frac_part + 1.0; // fmod operator does not work as in Matlab with negative numbers
}
d_initial_interp_counter[d_n_correlators] = static_cast<uint32_t>(floor(MAX_CODE_RESAMPLER_COUNTER * frac_part));
d_initial_interp_counter[d_n_correlators] = static_cast<uint32_t>(floor(max_code_resampler_counter * frac_part));
}
}
@ -394,8 +380,8 @@ void Fpga_Multicorrelator_8sc::fpga_compute_signal_parameters_in_fpga(void)
{
float d_rem_carrier_phase_in_rad_temp;
d_code_phase_step_chips_num = static_cast<uint32_t>(roundf(MAX_CODE_RESAMPLER_COUNTER * d_code_phase_step_chips));
d_code_phase_rate_step_chips_num = static_cast<uint32_t>(roundf(MAX_CODE_RESAMPLER_COUNTER * d_code_phase_rate_step_chips));
d_code_phase_step_chips_num = static_cast<uint32_t>(roundf(max_code_resampler_counter * d_code_phase_step_chips));
d_code_phase_rate_step_chips_num = static_cast<uint32_t>(roundf(max_code_resampler_counter * d_code_phase_rate_step_chips));
if (d_rem_carrier_phase_in_rad > M_PI)
{
@ -410,9 +396,9 @@ void Fpga_Multicorrelator_8sc::fpga_compute_signal_parameters_in_fpga(void)
d_rem_carrier_phase_in_rad_temp = d_rem_carrier_phase_in_rad;
}
d_rem_carr_phase_rad_int = static_cast<int32_t>(roundf((d_rem_carrier_phase_in_rad_temp)*PHASE_CARR_MAX_div_PI));
d_phase_step_rad_int = static_cast<int32_t>(roundf((d_phase_step_rad)*PHASE_CARR_MAX_div_PI)); // the FPGA accepts a range for the phase step between -pi and +pi
d_carrier_phase_rate_step_rad_int = static_cast<int32_t>(roundf((d_carrier_phase_rate_step_rad)*PHASE_CARR_MAX_div_PI));
d_rem_carr_phase_rad_int = static_cast<int32_t>(roundf((d_rem_carrier_phase_in_rad_temp)*PHASE_CARR_MAX_DIV_PI));
d_phase_step_rad_int = static_cast<int32_t>(roundf((d_phase_step_rad)*PHASE_CARR_MAX_DIV_PI)); // the FPGA accepts a range for the phase step between -pi and +pi
d_carrier_phase_rate_step_rad_int = static_cast<int32_t>(roundf((d_carrier_phase_rate_step_rad)*PHASE_CARR_MAX_DIV_PI));
}
@ -479,7 +465,7 @@ void Fpga_Multicorrelator_8sc::unlock_channel(void)
void Fpga_Multicorrelator_8sc::close_device()
{
auto *aux = const_cast<uint32_t *>(d_map_base);
if (munmap(static_cast<void *>(aux), PAGE_SIZE) == -1)
if (munmap(static_cast<void *>(aux), page_size) == -1)
{
std::cout << "Failed to unmap memory uio" << std::endl;
}
@ -571,7 +557,6 @@ void Fpga_Multicorrelator_8sc::write_secondary_code(uint32_t secondary_code_leng
write_val = write_val | (mem_addr * secondary_code_addr_bits) | (secondary_code_wr_strobe);
d_map_base[reg_addr] = write_val;
}
void Fpga_Multicorrelator_8sc::enable_secondary_codes()

22
src/algorithms/tracking/libs/fpga_multicorrelator.h
View File

@ -40,8 +40,9 @@
#include <gnuradio/block.h>
#include <cstdint>
// floating point math constants related to the parameters that are written in the FPGA
#define PHASE_CARR_MAX_DIV_PI 683565275.5764316 // 2^(31)/pi
#define TWO_PI 6.283185307179586
/*!
* \brief Class that implements carrier wipe-off and correlators.
@ -76,7 +77,6 @@ public:
private:
// FPGA register addresses
// write addresses
@ -107,14 +107,18 @@ private:
static const uint32_t result_reg_imag_base_addr = 7;
static const uint32_t sample_counter_reg_addr_lsw = 13;
static const uint32_t sample_counter_reg_addr_msw = 14;
// FPGA-related constants
static const uint32_t secondary_code_word_size = 20; // the secondary codes are written in to the FPGA in words of secondary_code_word_size bits
static const uint32_t secondary_code_wr_strobe = 0x800000; // write strobe position in the secondary code write register
static const uint32_t secondary_code_addr_bits = 0x100000; // memory address position in the secondary code write register
static const uint32_t drop_samples = 1; // bit 0 of drop_samples_reg_addr
static const uint32_t enable_secondary_code = 2; // bit 1 of drop_samples_reg_addr
static const uint32_t init_secondary_code_addresses = 4; // bit 2 of drop_samples_reg_addr
static const uint32_t secondary_code_wr_strobe = 0x800000; // write strobe position in the secondary code write register
static const uint32_t secondary_code_addr_bits = 0x100000; // memory address position in the secondary code write register
static const uint32_t drop_samples = 1; // bit 0 of drop_samples_reg_addr
static const uint32_t enable_secondary_code = 2; // bit 1 of drop_samples_reg_addr
static const uint32_t init_secondary_code_addresses = 4; // bit 2 of drop_samples_reg_addr
static const uint32_t page_size = 0x10000;
static const uint32_t max_length_deviceio_name = 50;
static const uint32_t max_code_resampler_counter = 1 << 20; // 2^(number of bits of precision of the code resampler)
static const uint32_t local_code_fpga_clear_address_counter = 0x10000000;
static const uint32_t test_register_track_writeval = 0x55AA;
gr_complex *d_corr_out;
gr_complex *d_Prompt_Data;

8
src/core/libs/gnss_sdr_fpga_sample_counter.cc
View File

@ -43,8 +43,6 @@
#include <unistd.h> // for write, close, read, ssize_t
#define PAGE_SIZE 0x10000 // default page size for the multicorrelator memory map
#define TEST_REG_SANITY_CHECK 0x55AA // value to check the presence of the test register (to detect the hw)
#ifndef TEMP_FAILURE_RETRY
#define TEMP_FAILURE_RETRY(exp) \
({ \
@ -151,7 +149,7 @@ void gnss_sdr_fpga_sample_counter::open_device()
LOG(WARNING) << "Cannot open deviceio" << device_name;
std::cout << "Counter-Intr: cannot open deviceio" << device_name << std::endl;
}
map_base = reinterpret_cast<volatile uint32_t *>(mmap(nullptr, PAGE_SIZE,
map_base = reinterpret_cast<volatile uint32_t *>(mmap(nullptr, page_size,
PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0));
if (map_base == reinterpret_cast<void *>(-1))
@ -161,7 +159,7 @@ void gnss_sdr_fpga_sample_counter::open_device()
}
// sanity check : check test register
uint32_t writeval = TEST_REG_SANITY_CHECK;
uint32_t writeval = test_reg_sanity_check;
uint32_t readval;
readval = gnss_sdr_fpga_sample_counter::test_register(writeval);
if (writeval != readval)
@ -181,7 +179,7 @@ void gnss_sdr_fpga_sample_counter::close_device()
map_base[2] = 0; // disable the generation of the interrupt in the device
auto *aux = const_cast<uint32_t *>(map_base);
if (munmap(static_cast<void *>(aux), PAGE_SIZE) == -1)
if (munmap(static_cast<void *>(aux), page_size) == -1)
{
std::cout << "Failed to unmap memory uio" << std::endl;
}

3
src/core/libs/gnss_sdr_fpga_sample_counter.h
View File

@ -55,6 +55,9 @@ public:
gr_vector_void_star &output_items);
private:
static const uint32_t page_size = 0x10000; // default page size for the multicorrelator memory map
static const uint32_t test_reg_sanity_check = 0x55AA; // value to check the presence of the test register (to detect the hw)
friend gnss_sdr_fpga_sample_counter_sptr gnss_sdr_make_fpga_sample_counter(double _fs, int32_t _interval_ms);
gnss_sdr_fpga_sample_counter(double _fs, int32_t _interval_ms);
uint32_t test_register(uint32_t writeval);