Improve constructors: prefer member initializers to member initializations in the constructor body

This commit is contained in:
Carles Fernandez 2021-10-11 15:13:12 +02:00
parent 3d6cfdbcbe
commit 6e96b41025
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GPG Key ID: 4C583C52B0C3877D
21 changed files with 297 additions and 468 deletions

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@ -72,12 +72,55 @@ dll_pll_veml_tracking_sptr dll_pll_veml_make_tracking(const Dll_Pll_Conf &conf_)
}
dll_pll_veml_tracking::dll_pll_veml_tracking(const Dll_Pll_Conf &conf_) : gr::block("dll_pll_veml_tracking", gr::io_signature::make(1, 1, sizeof(gr_complex)),
gr::io_signature::make(1, 1, sizeof(Gnss_Synchro)))
dll_pll_veml_tracking::dll_pll_veml_tracking(const Dll_Pll_Conf &conf_)
: gr::block("dll_pll_veml_tracking", gr::io_signature::make(1, 1, sizeof(gr_complex)),
gr::io_signature::make(1, 1, sizeof(Gnss_Synchro))),
d_trk_parameters(conf_),
d_acquisition_gnss_synchro(nullptr),
d_code_chip_rate(0.0),
d_acq_code_phase_samples(0.0),
d_acq_carrier_doppler_hz(0.0),
d_current_correlation_time_s(0.0),
d_carrier_doppler_hz(0.0),
d_acc_carrier_phase_rad(0.0),
d_rem_code_phase_chips(0.0),
d_T_chip_seconds(0.0),
d_T_prn_seconds(0.0),
d_T_prn_samples(0.0),
d_K_blk_samples(0.0),
d_carrier_lock_test(1.0),
d_CN0_SNV_dB_Hz(0.0),
d_carrier_lock_threshold(d_trk_parameters.carrier_lock_th),
d_carrier_phase_step_rad(0.0),
d_carrier_phase_rate_step_rad(0.0),
d_code_phase_step_chips(0.0),
d_code_phase_rate_step_chips(0.0),
d_rem_code_phase_samples(0.0), // Residual code phase (in chips)
d_sample_counter(0ULL),
d_acq_sample_stamp(0ULL),
d_rem_carr_phase_rad(0.0), // Residual carrier phase
d_state(0), // initial state: standby
d_current_prn_length_samples(static_cast<int32_t>(d_trk_parameters.vector_length)),
d_extend_correlation_symbols_count(0),
d_cn0_estimation_counter(0),
d_carrier_lock_fail_counter(0),
d_code_lock_fail_counter(0),
d_channel(0),
d_secondary_code_length(0U),
d_data_secondary_code_length(0U),
d_pull_in_transitory(true),
d_corrected_doppler(false),
d_interchange_iq(false),
d_veml(false),
d_cloop(true),
d_dump(d_trk_parameters.dump),
d_dump_mat(d_trk_parameters.dump_mat && d_dump),
d_acc_carrier_phase_initialized(false),
d_Flag_PLL_180_deg_phase_locked(false)
{
// prevent telemetry symbols accumulation in output buffers
this->set_max_noutput_items(1);
d_trk_parameters = conf_;
// Telemetry bit synchronization message port input
this->message_port_register_out(pmt::mp("events"));
this->set_relative_rate(1.0 / static_cast<double>(d_trk_parameters.vector_length));
@ -98,14 +141,6 @@ dll_pll_veml_tracking::dll_pll_veml_tracking(const Dll_Pll_Conf &conf_) : gr::bl
// initialize internal vars
d_dll_filt_history.set_capacity(1000);
d_veml = false;
d_cloop = true;
d_pull_in_transitory = true;
d_code_chip_rate = 0.0;
d_secondary_code_length = 0U;
d_data_secondary_code_length = 0U;
d_preamble_length_symbols = 0;
d_interchange_iq = false;
d_signal_type = std::string(d_trk_parameters.signal);
std::map<std::string, std::string> map_signal_pretty_name;
@ -410,10 +445,9 @@ dll_pll_veml_tracking::dll_pll_veml_tracking(const Dll_Pll_Conf &conf_) : gr::bl
d_code_samples_per_chip = 0U;
d_symbols_per_bit = 0;
}
d_T_chip_seconds = 0.0;
d_T_prn_seconds = 0.0;
d_T_prn_samples = 0.0;
d_K_blk_samples = 0.0;
// Initial code frequency basis of NCO
d_code_freq_chips = d_code_chip_rate;
// Initialize tracking ==========================================
d_code_loop_filter = Tracking_loop_filter(static_cast<float>(d_code_period), d_trk_parameters.dll_bw_hz, d_trk_parameters.dll_filter_order, false);
@ -488,28 +522,9 @@ dll_pll_veml_tracking::dll_pll_veml_tracking(const Dll_Pll_Conf &conf_) : gr::bl
// --- Initializations ---
d_Prompt_circular_buffer.set_capacity(d_secondary_code_length);
d_multicorrelator_cpu.set_high_dynamics_resampler(d_trk_parameters.high_dyn);
// Initial code frequency basis of NCO
d_code_freq_chips = d_code_chip_rate;
// Residual code phase (in chips)
d_rem_code_phase_samples = 0.0;
// Residual carrier phase
d_rem_carr_phase_rad = 0.0;
// sample synchronization
d_sample_counter = 0ULL;
d_acq_sample_stamp = 0ULL;
d_current_prn_length_samples = static_cast<int32_t>(d_trk_parameters.vector_length);
d_current_correlation_time_s = 0.0;
// CN0 estimation and lock detector buffers
d_cn0_estimation_counter = 0;
d_Prompt_buffer = volk_gnsssdr::vector<gr_complex>(d_trk_parameters.cn0_samples);
d_carrier_lock_test = 1.0;
d_CN0_SNV_dB_Hz = 0.0;
d_carrier_lock_fail_counter = 0;
d_code_lock_fail_counter = 0;
d_carrier_lock_threshold = d_trk_parameters.carrier_lock_th;
d_Prompt_Data = volk_gnsssdr::vector<gr_complex>(1);
d_cn0_smoother = Exponential_Smoother();
d_cn0_smoother.set_alpha(d_trk_parameters.cn0_smoother_alpha);
@ -525,21 +540,8 @@ dll_pll_veml_tracking::dll_pll_veml_tracking(const Dll_Pll_Conf &conf_) : gr::bl
d_carrier_lock_test_smoother.set_offset(0.0);
d_carrier_lock_test_smoother.set_samples_for_initialization(d_trk_parameters.carrier_lock_test_smoother_samples);
d_acquisition_gnss_synchro = nullptr;
d_channel = 0;
d_acq_code_phase_samples = 0.0;
d_acq_carrier_doppler_hz = 0.0;
d_carrier_doppler_hz = 0.0;
d_acc_carrier_phase_rad = 0.0;
d_extend_correlation_symbols_count = 0;
d_code_phase_step_chips = 0.0;
d_code_phase_rate_step_chips = 0.0;
d_carrier_phase_step_rad = 0.0;
d_carrier_phase_rate_step_rad = 0.0;
d_rem_code_phase_chips = 0.0;
d_state = 0; // initial state: standby
clear_tracking_vars();
if (d_trk_parameters.smoother_length > 0)
{
d_carr_ph_history.set_capacity(d_trk_parameters.smoother_length * 2);
@ -551,8 +553,6 @@ dll_pll_veml_tracking::dll_pll_veml_tracking(const Dll_Pll_Conf &conf_) : gr::bl
d_code_ph_history.set_capacity(1);
}
d_dump = d_trk_parameters.dump;
d_dump_mat = d_trk_parameters.dump_mat and d_dump;
if (d_dump)
{
d_dump_filename = d_trk_parameters.dump_filename;
@ -586,9 +586,6 @@ dll_pll_veml_tracking::dll_pll_veml_tracking(const Dll_Pll_Conf &conf_) : gr::bl
d_dump = false;
}
}
d_corrected_doppler = false;
d_acc_carrier_phase_initialized = false;
d_Flag_PLL_180_deg_phase_locked = false;
}

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@ -57,7 +57,7 @@ dll_pll_veml_tracking_sptr dll_pll_veml_make_tracking(const Dll_Pll_Conf &conf_)
class dll_pll_veml_tracking : public gr::block
{
public:
~dll_pll_veml_tracking();
~dll_pll_veml_tracking() override;
void set_channel(uint32_t channel);
void set_gnss_synchro(Gnss_Synchro *p_gnss_synchro);
@ -65,9 +65,9 @@ public:
void stop_tracking();
int general_work(int noutput_items, gr_vector_int &ninput_items,
gr_vector_const_void_star &input_items, gr_vector_void_star &output_items);
gr_vector_const_void_star &input_items, gr_vector_void_star &output_items) override;
void forecast(int noutput_items, gr_vector_int &ninput_items_required);
void forecast(int noutput_items, gr_vector_int &ninput_items_required) override;
private:
friend dll_pll_veml_tracking_sptr dll_pll_veml_make_tracking(const Dll_Pll_Conf &conf_);
@ -170,7 +170,6 @@ private:
float d_rem_carr_phase_rad;
int32_t d_symbols_per_bit;
int32_t d_preamble_length_symbols;
int32_t d_state;
int32_t d_correlation_length_ms;
int32_t d_n_correlator_taps;

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@ -61,13 +61,67 @@ dll_pll_veml_tracking_fpga_sptr dll_pll_veml_make_tracking_fpga(const Dll_Pll_Co
}
dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &conf_) : gr::block("dll_pll_veml_tracking_fpga", gr::io_signature::make(0, 0, sizeof(lv_16sc_t)),
gr::io_signature::make(1, 1, sizeof(Gnss_Synchro)))
dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &conf_)
: gr::block("dll_pll_veml_tracking_fpga", gr::io_signature::make(0, 0, sizeof(lv_16sc_t)),
gr::io_signature::make(1, 1, sizeof(Gnss_Synchro))),
d_trk_parameters(conf_),
d_acquisition_gnss_synchro(nullptr),
d_code_chip_rate(0.0),
d_code_phase_step_chips(0.0),
d_code_phase_rate_step_chips(0.0),
d_carrier_phase_step_rad(0.0),
d_carrier_phase_rate_step_rad(0.0),
d_acq_code_phase_samples(0.0),
d_acq_carrier_doppler_hz(0.0),
d_rem_code_phase_samples(0.0),
d_rem_code_phase_samples_prev(0.0),
d_current_correlation_time_s(0.0),
d_carrier_doppler_hz(0.0),
d_acc_carrier_phase_rad(0.0),
d_rem_code_phase_chips(0.0),
d_T_chip_seconds(0.0),
d_T_prn_seconds(0.0),
d_T_prn_samples(0.0),
d_K_blk_samples(0.0),
d_carrier_lock_test(1.0),
d_CN0_SNV_dB_Hz(0.0),
d_carrier_lock_threshold(d_trk_parameters.carrier_lock_th),
d_sample_counter(0ULL),
d_acq_sample_stamp(0ULL),
d_sample_counter_next(0ULL),
d_rem_carr_phase_rad(0.0),
d_state(1),
d_extend_correlation_symbols_count(0),
d_current_integration_length_samples(static_cast<int32_t>(d_trk_parameters.vector_length)),
d_cn0_estimation_counter(0),
d_carrier_lock_fail_counter(0),
d_code_lock_fail_counter(0),
d_extend_fpga_integration_periods(d_trk_parameters.extend_fpga_integration_periods),
d_channel(0),
d_secondary_code_length(0U),
d_data_secondary_code_length(0U),
d_code_length_chips(d_trk_parameters.code_length_chips),
d_code_samples_per_chip(d_trk_parameters.code_samples_per_chip),
d_fpga_integration_period(d_trk_parameters.fpga_integration_period),
d_current_fpga_integration_period(1),
d_veml(false),
d_cloop(true),
d_dump(d_trk_parameters.dump),
d_dump_mat(d_trk_parameters.dump_mat && d_dump),
d_pull_in_transitory(true),
d_corrected_doppler(false),
d_interchange_iq(false),
d_acc_carrier_phase_initialized(false),
d_worker_is_done(false),
d_extended_correlation_in_fpga(d_trk_parameters.extended_correlation_in_fpga),
d_current_extended_correlation_in_fpga(false),
d_stop_tracking(false),
d_sc_demodulate_enabled(false),
d_Flag_PLL_180_deg_phase_locked(false)
{
// prevent telemetry symbols accumulation in output buffers
this->set_max_noutput_items(1);
d_trk_parameters = conf_;
// Telemetry bit synchronization message port input
this->message_port_register_out(pmt::mp("events"));
this->set_relative_rate(1.0 / static_cast<double>(d_trk_parameters.vector_length));
@ -86,14 +140,8 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
#endif
// initialize internal vars
d_dll_filt_history.set_capacity(1000);
d_veml = false;
d_cloop = true;
d_pull_in_transitory = true;
d_code_chip_rate = 0.0;
d_secondary_code_length = 0U;
d_data_secondary_code_length = 0U;
d_signal_type = std::string(d_trk_parameters.signal);
d_interchange_iq = false;
std::map<std::string, std::string> map_signal_pretty_name;
map_signal_pretty_name["1C"] = "L1 C/A";
@ -106,15 +154,6 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
d_signal_pretty_name = map_signal_pretty_name[d_signal_type];
d_code_samples_per_chip = d_trk_parameters.code_samples_per_chip; // number of samples per chip
d_code_length_chips = d_trk_parameters.code_length_chips;
d_extended_correlation_in_fpga = d_trk_parameters.extended_correlation_in_fpga;
d_current_extended_correlation_in_fpga = false;
d_extend_fpga_integration_periods = d_trk_parameters.extend_fpga_integration_periods; // by default
d_fpga_integration_period = d_trk_parameters.fpga_integration_period; // by default
d_current_fpga_integration_period = 1;
d_sc_demodulate_enabled = false;
if (d_trk_parameters.system == 'G')
{
d_systemName = "GPS";
@ -290,10 +329,6 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
d_code_period = 0.0;
d_symbols_per_bit = 0;
}
d_T_chip_seconds = 0.0;
d_T_prn_seconds = 0.0;
d_T_prn_samples = 0.0;
d_K_blk_samples = 0.0;
// Initialize tracking ==========================================
d_code_loop_filter = Tracking_loop_filter(static_cast<float>(d_code_period), d_trk_parameters.dll_bw_hz, d_trk_parameters.dll_filter_order, false);
@ -353,30 +388,13 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
// --- Initializations ---
d_Prompt_circular_buffer.set_capacity(d_secondary_code_length);
// Initial code frequency basis of NCO
d_code_freq_chips = d_code_chip_rate;
// Residual code phase (in chips)
d_rem_code_phase_samples = 0.0;
d_rem_code_phase_samples_prev = 0.0; // previously calculated d_rem_code_phase_samples
// Residual carrier phase
d_rem_carr_phase_rad = 0.0;
// sample synchronization
d_sample_counter = 0ULL;
d_acq_sample_stamp = 0ULL;
d_current_integration_length_samples = static_cast<int32_t>(d_trk_parameters.vector_length);
d_next_integration_length_samples = d_current_integration_length_samples;
d_current_correlation_time_s = 0.0;
// CN0 estimation and lock detector buffers
d_cn0_estimation_counter = 0;
d_Prompt_buffer = volk_gnsssdr::vector<gr_complex>(d_trk_parameters.cn0_samples);
d_carrier_lock_test = 1.0;
d_CN0_SNV_dB_Hz = 0.0;
d_carrier_lock_fail_counter = 0;
d_code_lock_fail_counter = 0;
d_carrier_lock_threshold = d_trk_parameters.carrier_lock_th;
d_Prompt_Data = volk_gnsssdr::vector<gr_complex>(1);
d_cn0_smoother = Exponential_Smoother();
d_cn0_smoother.set_alpha(d_trk_parameters.cn0_smoother_alpha);
@ -391,20 +409,6 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
d_carrier_lock_test_smoother.set_offset(0.0);
d_carrier_lock_test_smoother.set_samples_for_initialization(d_trk_parameters.carrier_lock_test_smoother_samples);
d_acquisition_gnss_synchro = nullptr;
d_channel = 0;
d_acq_code_phase_samples = 0.0;
d_acq_carrier_doppler_hz = 0.0;
d_carrier_doppler_hz = 0.0;
d_acc_carrier_phase_rad = 0.0;
d_extend_correlation_symbols_count = 0;
d_code_phase_step_chips = 0.0;
d_code_phase_rate_step_chips = 0.0;
d_carrier_phase_step_rad = 0.0;
d_carrier_phase_rate_step_rad = 0.0;
d_rem_code_phase_chips = 0.0;
d_state = 1; // initial state: standby
clear_tracking_vars();
if (d_trk_parameters.smoother_length > 0)
{
@ -417,8 +421,12 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
d_code_ph_history.set_capacity(1);
}
d_dump = d_trk_parameters.dump;
d_dump_mat = d_trk_parameters.dump_mat and d_dump;
// create multicorrelator class
int32_t *ca_codes = d_trk_parameters.ca_codes;
int32_t *data_codes = d_trk_parameters.data_codes;
d_multicorrelator_fpga = std::make_shared<Fpga_Multicorrelator_8sc>(d_n_correlator_taps, ca_codes, data_codes, d_code_length_chips, d_trk_parameters.track_pilot, d_code_samples_per_chip);
d_multicorrelator_fpga->set_output_vectors(d_correlator_outs.data(), d_Prompt_Data.data());
if (d_dump)
{
d_dump_filename = d_trk_parameters.dump_filename;
@ -452,21 +460,6 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
d_dump = false;
}
}
// create multicorrelator class
int32_t *ca_codes = d_trk_parameters.ca_codes;
int32_t *data_codes = d_trk_parameters.data_codes;
d_multicorrelator_fpga = std::make_shared<Fpga_Multicorrelator_8sc>(d_n_correlator_taps, ca_codes, data_codes, d_code_length_chips, d_trk_parameters.track_pilot, d_code_samples_per_chip);
d_multicorrelator_fpga->set_output_vectors(d_correlator_outs.data(), d_Prompt_Data.data());
d_sample_counter_next = 0ULL;
d_corrected_doppler = false;
d_worker_is_done = false;
d_stop_tracking = false;
d_acc_carrier_phase_initialized = false;
d_Flag_PLL_180_deg_phase_locked = false;
}
@ -757,7 +750,7 @@ void dll_pll_veml_tracking_fpga::run_dll_pll()
if (d_dll_filt_history.full())
{
const float avg_code_error_chips_s = static_cast<float>(std::accumulate(d_dll_filt_history.begin(), d_dll_filt_history.end(), 0.0)) / static_cast<float>(d_dll_filt_history.capacity());
if (fabs(avg_code_error_chips_s) > 1.0)
if (std::fabs(avg_code_error_chips_s) > 1.0)
{
const float carrier_doppler_error_hz = static_cast<float>(d_signal_carrier_freq) * avg_code_error_chips_s / static_cast<float>(d_code_chip_rate);
LOG(INFO) << "Detected and corrected carrier doppler error: " << carrier_doppler_error_hz << " [Hz] on sat " << Gnss_Satellite(d_systemName, d_acquisition_gnss_synchro->PRN);

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@ -23,18 +23,6 @@
#include <cmath>
Cpu_Multicorrelator::Cpu_Multicorrelator()
{
d_sig_in = nullptr;
d_local_code_in = nullptr;
d_shifts_chips = nullptr;
d_corr_out = nullptr;
d_local_codes_resampled = nullptr;
d_code_length_chips = 0;
d_n_correlators = 0;
}
Cpu_Multicorrelator::~Cpu_Multicorrelator()
{
if (d_local_codes_resampled != nullptr)

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@ -37,7 +37,7 @@
class Cpu_Multicorrelator
{
public:
Cpu_Multicorrelator();
Cpu_Multicorrelator() = default;
~Cpu_Multicorrelator();
bool init(int max_signal_length_samples, int n_correlators);
bool set_local_code_and_taps(int code_length_chips, const std::complex<float> *local_code_in, float *shifts_chips);
@ -48,13 +48,13 @@ public:
private:
// Allocate the device input vectors
const std::complex<float> *d_sig_in;
const std::complex<float> *d_local_code_in;
std::complex<float> **d_local_codes_resampled;
std::complex<float> *d_corr_out;
float *d_shifts_chips;
int d_code_length_chips;
int d_n_correlators;
const std::complex<float> *d_sig_in{nullptr};
const std::complex<float> *d_local_code_in{nullptr};
std::complex<float> **d_local_codes_resampled{nullptr};
std::complex<float> *d_corr_out{nullptr};
float *d_shifts_chips{nullptr};
int d_code_length_chips{0};
int d_n_correlators{0};
};

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@ -91,18 +91,6 @@ bool Cpu_Multicorrelator_16sc::Carrier_wipeoff_multicorrelator_resampler(
}
Cpu_Multicorrelator_16sc::Cpu_Multicorrelator_16sc()
{
d_sig_in = nullptr;
d_local_code_in = nullptr;
d_shifts_chips = nullptr;
d_corr_out = nullptr;
d_local_codes_resampled = nullptr;
d_code_length_chips = 0;
d_n_correlators = 0;
}
Cpu_Multicorrelator_16sc::~Cpu_Multicorrelator_16sc()
{
if (d_local_codes_resampled != nullptr)

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@ -35,7 +35,7 @@
class Cpu_Multicorrelator_16sc
{
public:
Cpu_Multicorrelator_16sc();
Cpu_Multicorrelator_16sc() = default;
~Cpu_Multicorrelator_16sc();
bool init(int max_signal_length_samples, int n_correlators);
bool set_local_code_and_taps(int code_length_chips, const lv_16sc_t *local_code_in, float *shifts_chips);
@ -46,13 +46,13 @@ public:
private:
// Allocate the device input vectors
const lv_16sc_t *d_sig_in;
const lv_16sc_t *d_local_code_in;
lv_16sc_t **d_local_codes_resampled;
lv_16sc_t *d_corr_out;
float *d_shifts_chips;
int d_code_length_chips;
int d_n_correlators;
const lv_16sc_t *d_sig_in{nullptr};
const lv_16sc_t *d_local_code_in{nullptr};
lv_16sc_t **d_local_codes_resampled{nullptr};
lv_16sc_t *d_corr_out{nullptr};
float *d_shifts_chips{nullptr};
int d_code_length_chips{0};
int d_n_correlators{0};
};

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@ -23,18 +23,6 @@
#include <volk_gnsssdr/volk_gnsssdr.h>
#include <cmath>
Cpu_Multicorrelator_Real_Codes::Cpu_Multicorrelator_Real_Codes()
{
d_sig_in = nullptr;
d_local_code_in = nullptr;
d_shifts_chips = nullptr;
d_corr_out = nullptr;
d_local_codes_resampled = nullptr;
d_code_length_chips = 0;
d_n_correlators = 0;
d_use_high_dynamics_resampler = true;
}
Cpu_Multicorrelator_Real_Codes::~Cpu_Multicorrelator_Real_Codes()
{

View File

@ -37,7 +37,7 @@
class Cpu_Multicorrelator_Real_Codes
{
public:
Cpu_Multicorrelator_Real_Codes();
Cpu_Multicorrelator_Real_Codes() = default;
void set_high_dynamics_resampler(bool use_high_dynamics_resampler);
~Cpu_Multicorrelator_Real_Codes();
bool init(int max_signal_length_samples, int n_correlators);
@ -50,14 +50,14 @@ public:
private:
// Allocate the device input vectors
const std::complex<float> *d_sig_in;
const float *d_local_code_in;
std::complex<float> *d_corr_out;
float **d_local_codes_resampled;
float *d_shifts_chips;
int d_code_length_chips;
int d_n_correlators;
bool d_use_high_dynamics_resampler;
const std::complex<float> *d_sig_in{nullptr};
const float *d_local_code_in{nullptr};
std::complex<float> *d_corr_out{nullptr};
float **d_local_codes_resampled{nullptr};
float *d_shifts_chips{nullptr};
int d_code_length_chips{0};
int d_n_correlators{0};
bool d_use_high_dynamics_resampler{true};
};

View File

@ -21,55 +21,15 @@
#include <glog/logging.h>
Dll_Pll_Conf::Dll_Pll_Conf()
Dll_Pll_Conf::Dll_Pll_Conf() : carrier_lock_th(FLAGS_carrier_lock_th),
cn0_samples(FLAGS_cn0_samples),
cn0_min(FLAGS_cn0_min),
max_code_lock_fail(FLAGS_max_lock_fail),
max_carrier_lock_fail(FLAGS_max_carrier_lock_fail)
{
/* DLL/PLL tracking configuration */
high_dyn = false;
smoother_length = 10;
fs_in = 2000000.0;
vector_length = 0U;
dump = false;
dump_mat = true;
dump_filename = std::string("./dll_pll_dump.dat");
enable_fll_pull_in = false;
enable_fll_steady_state = false;
pull_in_time_s = 10;
bit_synchronization_time_limit_s = pull_in_time_s + 10;
fll_filter_order = 1;
pll_filter_order = 3;
dll_filter_order = 2;
fll_bw_hz = 35.0;
pll_pull_in_bw_hz = 50.0;
dll_pull_in_bw_hz = 3.0;
pll_bw_hz = 35.0;
dll_bw_hz = 2.0;
pll_bw_narrow_hz = 5.0;
dll_bw_narrow_hz = 0.75;
early_late_space_chips = 0.25;
very_early_late_space_chips = 0.5;
early_late_space_narrow_chips = 0.15;
very_early_late_space_narrow_chips = 0.5;
slope = 1.0;
spc = 0.5;
y_intercept = 1.0;
carrier_aiding = true;
extend_correlation_symbols = 1;
cn0_samples = FLAGS_cn0_samples;
cn0_smoother_samples = 200;
cn0_smoother_alpha = 0.002;
carrier_lock_test_smoother_alpha = 0.002;
carrier_lock_test_smoother_samples = 25;
cn0_min = FLAGS_cn0_min;
max_carrier_lock_fail = FLAGS_max_carrier_lock_fail;
max_code_lock_fail = FLAGS_max_lock_fail;
carrier_lock_th = FLAGS_carrier_lock_th;
track_pilot = true;
enable_doppler_correction = false;
system = 'G';
signal[0] = '1';
signal[1] = 'C';
signal[2] = '\0';
item_type = std::string("gr_complex");
}

View File

@ -36,50 +36,50 @@ public:
void SetFromConfiguration(const ConfigurationInterface *configuration, const std::string &role);
/* DLL/PLL tracking configuration */
std::string item_type;
std::string dump_filename;
double fs_in;
double carrier_lock_th;
float pll_pull_in_bw_hz;
float dll_pull_in_bw_hz;
float fll_bw_hz;
float pll_bw_hz;
float dll_bw_hz;
float pll_bw_narrow_hz;
float dll_bw_narrow_hz;
float early_late_space_chips;
float very_early_late_space_chips;
float early_late_space_narrow_chips;
float very_early_late_space_narrow_chips;
float slope;
float spc;
float y_intercept;
float cn0_smoother_alpha;
float carrier_lock_test_smoother_alpha;
uint32_t pull_in_time_s;
uint32_t bit_synchronization_time_limit_s;
uint32_t vector_length;
uint32_t smoother_length;
int32_t fll_filter_order;
int32_t pll_filter_order;
int32_t dll_filter_order;
int32_t extend_correlation_symbols;
int32_t cn0_samples;
int32_t cn0_smoother_samples;
int32_t carrier_lock_test_smoother_samples;
int32_t cn0_min;
int32_t max_code_lock_fail;
int32_t max_carrier_lock_fail;
std::string item_type{"gr_complex"};
std::string dump_filename{"./dll_pll_dump.dat"};
double fs_in{2000000.0};
double carrier_lock_th{0.0};
float pll_pull_in_bw_hz{50.0};
float dll_pull_in_bw_hz{3.0};
float fll_bw_hz{35.0};
float pll_bw_hz{35.0};
float dll_bw_hz{2.0};
float pll_bw_narrow_hz{5.0};
float dll_bw_narrow_hz{0.75};
float early_late_space_chips{0.25};
float very_early_late_space_chips{0.5};
float early_late_space_narrow_chips{0.15};
float very_early_late_space_narrow_chips{0.5};
float slope{1.0};
float spc{0.5};
float y_intercept{1.0};
float cn0_smoother_alpha{0.002};
float carrier_lock_test_smoother_alpha{0.002};
uint32_t pull_in_time_s{10U};
uint32_t bit_synchronization_time_limit_s{20U};
uint32_t vector_length{0U};
uint32_t smoother_length{10U};
int32_t fll_filter_order{1};
int32_t pll_filter_order{3};
int32_t dll_filter_order{2};
int32_t extend_correlation_symbols{1};
int32_t cn0_samples{0};
int32_t cn0_smoother_samples{200};
int32_t carrier_lock_test_smoother_samples{25};
int32_t cn0_min{0};
int32_t max_code_lock_fail{0};
int32_t max_carrier_lock_fail{0};
char signal[3]{};
char system;
bool enable_fll_pull_in;
bool enable_fll_steady_state;
bool track_pilot;
bool enable_doppler_correction;
bool carrier_aiding;
bool high_dyn;
bool dump;
bool dump_mat;
char system{'G'};
bool enable_fll_pull_in{false};
bool enable_fll_steady_state{false};
bool track_pilot{true};
bool enable_doppler_correction{false};
bool carrier_aiding{true};
bool high_dyn{false};
bool dump{false};
bool dump_mat{true};
};

View File

@ -22,63 +22,15 @@
#include <glog/logging.h>
Dll_Pll_Conf_Fpga::Dll_Pll_Conf_Fpga()
Dll_Pll_Conf_Fpga::Dll_Pll_Conf_Fpga() : carrier_lock_th(FLAGS_carrier_lock_th),
cn0_samples(FLAGS_cn0_samples),
cn0_min(FLAGS_cn0_min),
max_code_lock_fail(FLAGS_max_lock_fail),
max_carrier_lock_fail(FLAGS_max_carrier_lock_fail)
{
/* DLL/PLL tracking configuration */
high_dyn = false;
smoother_length = 10;
fs_in = 12500000.0;
vector_length = 0U;
dump = false;
dump_mat = true;
dump_filename = std::string("./dll_pll_dump.dat");
enable_fll_pull_in = false;
enable_fll_steady_state = false;
pull_in_time_s = 10;
bit_synchronization_time_limit_s = pull_in_time_s + 60;
fll_filter_order = 1;
pll_filter_order = 3;
dll_filter_order = 2;
fll_bw_hz = 35.0;
pll_pull_in_bw_hz = 50.0;
dll_pull_in_bw_hz = 3.0;
pll_bw_hz = 5.0;
dll_bw_hz = 0.5;
pll_bw_narrow_hz = 2.0;
dll_bw_narrow_hz = 0.25;
early_late_space_chips = 0.25;
very_early_late_space_chips = 0.5;
early_late_space_narrow_chips = 0.15;
very_early_late_space_narrow_chips = 0.5;
slope = 1.0;
spc = 0.5;
y_intercept = 1.0;
carrier_aiding = true;
extend_correlation_symbols = 1;
cn0_samples = FLAGS_cn0_samples;
cn0_smoother_samples = 200;
cn0_smoother_alpha = 0.002;
carrier_lock_test_smoother_alpha = 0.002;
carrier_lock_test_smoother_samples = 25;
cn0_min = FLAGS_cn0_min;
max_carrier_lock_fail = FLAGS_max_carrier_lock_fail;
max_code_lock_fail = FLAGS_max_lock_fail;
carrier_lock_th = FLAGS_carrier_lock_th;
// max_lock_fail = 50;
enable_doppler_correction = false;
track_pilot = true;
system = 'G';
signal[0] = '1';
signal[1] = 'C';
signal[2] = '\0';
device_name = std::string("/dev/uio");
code_length_chips = 0U;
code_samples_per_chip = 0U;
ca_codes = nullptr;
data_codes = nullptr;
extended_correlation_in_fpga = false;
extend_fpga_integration_periods = 1;
fpga_integration_period = 0;
}

View File

@ -38,65 +38,65 @@ public:
void SetFromConfiguration(const ConfigurationInterface* configuration, const std::string& role);
/* DLL/PLL tracking configuration */
std::string device_name;
std::string dump_filename;
std::string device_name{"/dev/uio"};
std::string dump_filename{"./dll_pll_dump.dat"};
double fs_in;
double carrier_lock_th;
double fs_in{12500000.0};
double carrier_lock_th{0.0};
float pll_pull_in_bw_hz;
float dll_pull_in_bw_hz;
float fll_bw_hz;
float pll_bw_hz;
float dll_bw_hz;
float pll_bw_narrow_hz;
float dll_bw_narrow_hz;
float early_late_space_chips;
float very_early_late_space_chips;
float early_late_space_narrow_chips;
float very_early_late_space_narrow_chips;
float slope;
float spc;
float y_intercept;
float cn0_smoother_alpha;
float carrier_lock_test_smoother_alpha;
float pll_pull_in_bw_hz{50.0};
float dll_pull_in_bw_hz{3.0};
float fll_bw_hz{35.0};
float pll_bw_hz{5.0};
float dll_bw_hz{0.5};
float pll_bw_narrow_hz{2.0};
float dll_bw_narrow_hz{0.25};
float early_late_space_chips{0.25};
float very_early_late_space_chips{0.5};
float early_late_space_narrow_chips{0.15};
float very_early_late_space_narrow_chips{0.5};
float slope{1.0};
float spc{0.5};
float y_intercept{1.0};
float cn0_smoother_alpha{0.002};
float carrier_lock_test_smoother_alpha{0.002};
uint32_t pull_in_time_s; // signed integer, when pull in time is not yet reached it has to be compared against a negative number
uint32_t bit_synchronization_time_limit_s;
uint32_t vector_length;
uint32_t smoother_length;
uint32_t code_length_chips;
uint32_t code_samples_per_chip;
uint32_t extend_fpga_integration_periods;
uint32_t fpga_integration_period;
uint32_t pull_in_time_s{10U}; // signed integer, when pull in time is not yet reached it has to be compared against a negative number
uint32_t bit_synchronization_time_limit_s{70U};
uint32_t vector_length{0U};
uint32_t smoother_length{10U};
uint32_t code_length_chips{0U};
uint32_t code_samples_per_chip{0U};
uint32_t extend_fpga_integration_periods{1};
uint32_t fpga_integration_period{0};
int32_t fll_filter_order;
int32_t pll_filter_order;
int32_t dll_filter_order;
int32_t extend_correlation_symbols;
int32_t cn0_samples;
int32_t cn0_min;
int32_t max_code_lock_fail;
int32_t max_carrier_lock_fail;
int32_t cn0_smoother_samples;
int32_t carrier_lock_test_smoother_samples;
int32_t fll_filter_order{1};
int32_t pll_filter_order{3};
int32_t dll_filter_order{2};
int32_t extend_correlation_symbols{1};
int32_t cn0_samples{0};
int32_t cn0_min{0};
int32_t max_code_lock_fail{0};
int32_t max_carrier_lock_fail{0};
int32_t cn0_smoother_samples{200};
int32_t carrier_lock_test_smoother_samples{25};
// int32_t max_lock_fail;
int32_t* ca_codes;
int32_t* data_codes;
int32_t* ca_codes{nullptr};
int32_t* data_codes{nullptr};
char signal[3];
char system;
char signal[3]{};
char system{'G'};
bool extended_correlation_in_fpga;
bool track_pilot;
bool enable_doppler_correction;
bool enable_fll_pull_in;
bool enable_fll_steady_state;
bool carrier_aiding;
bool high_dyn;
bool dump;
bool dump_mat;
bool extended_correlation_in_fpga{false};
bool track_pilot{true};
bool enable_doppler_correction{false};
bool enable_fll_pull_in{false};
bool enable_fll_steady_state{false};
bool carrier_aiding{true};
bool high_dyn{false};
bool dump{false};
bool dump_mat{true};
};

View File

@ -22,14 +22,6 @@
Exponential_Smoother::Exponential_Smoother()
{
alpha_ = 0.001;
old_value_ = 0.0;
one_minus_alpha_ = 1.0F - alpha_;
samples_for_initialization_ = 200;
initializing_ = true;
init_counter_ = 0;
min_value_ = 25.0;
offset_ = 12.0;
init_buffer_.reserve(samples_for_initialization_);
}

View File

@ -55,14 +55,14 @@ public:
private:
std::vector<float> init_buffer_;
float alpha_; // takes value 0.0001 if not set
float one_minus_alpha_;
float old_value_;
float min_value_;
float offset_;
int samples_for_initialization_;
int init_counter_;
bool initializing_;
float alpha_{0.001};
float one_minus_alpha_{0.999};
float old_value_{0.0};
float min_value_{25.0};
float offset_{12.0};
int samples_for_initialization_{200};
int init_counter_{0};
bool initializing_{true};
};

View File

@ -52,12 +52,28 @@ Fpga_Multicorrelator_8sc::Fpga_Multicorrelator_8sc(int32_t n_correlators,
uint32_t code_length_chips,
bool track_pilot,
uint32_t code_samples_per_chip)
: d_initial_sample_counter(0),
d_corr_out(nullptr),
d_Prompt_Data(nullptr),
d_shifts_chips(nullptr),
d_prompt_data_shift(nullptr),
d_rem_code_phase_chips(0),
d_code_phase_step_chips(0),
d_rem_carrier_phase_in_rad(0),
d_phase_step_rad(0),
d_code_length_samples(code_length_chips * code_samples_per_chip),
d_n_correlators(n_correlators),
d_device_descriptor(0),
d_map_base(nullptr),
d_correlator_length_samples(0),
d_code_phase_step_chips_num(0),
d_rem_carr_phase_rad_int(0),
d_phase_step_rad_int(0),
d_ca_codes(ca_codes),
d_data_codes(data_codes),
d_track_pilot(track_pilot),
d_secondary_code_enabled(false)
{
d_n_correlators = n_correlators;
d_track_pilot = track_pilot;
d_device_descriptor = 0;
d_map_base = nullptr;
// instantiate variable length vectors
if (d_track_pilot)
{
@ -69,26 +85,6 @@ Fpga_Multicorrelator_8sc::Fpga_Multicorrelator_8sc(int32_t n_correlators,
d_initial_index = volk_gnsssdr::vector<uint32_t>(n_correlators);
d_initial_interp_counter = volk_gnsssdr::vector<uint32_t>(n_correlators);
}
d_shifts_chips = nullptr;
d_prompt_data_shift = nullptr;
d_Prompt_Data = nullptr;
d_corr_out = nullptr;
d_code_length_chips = 0;
d_rem_code_phase_chips = 0;
d_code_phase_step_chips = 0;
d_rem_carrier_phase_in_rad = 0;
d_phase_step_rad = 0;
d_rem_carr_phase_rad_int = 0;
d_phase_step_rad_int = 0;
d_initial_sample_counter = 0;
d_correlator_length_samples = 0;
d_code_phase_step_chips_num = 0;
d_code_length_chips = code_length_chips;
d_ca_codes = ca_codes;
d_data_codes = data_codes;
d_code_samples_per_chip = code_samples_per_chip;
d_code_length_samples = d_code_length_chips * d_code_samples_per_chip;
d_secondary_code_enabled = false;
DLOG(INFO) << "TRACKING FPGA CLASS CREATED";
}

View File

@ -221,7 +221,6 @@ private:
float d_phase_step_rad;
float d_carrier_phase_rate_step_rad;
uint32_t d_code_length_chips;
uint32_t d_code_length_samples;
uint32_t d_n_correlators; // number of correlators
@ -231,7 +230,6 @@ private:
// configuration data received from the interface
uint32_t d_correlator_length_samples;
uint32_t d_code_samples_per_chip;
uint32_t d_code_phase_step_chips_num;
uint32_t d_code_phase_rate_step_chips_num;

View File

@ -59,17 +59,15 @@ float Tracking_2nd_DLL_filter::get_code_nco(float DLL_discriminator)
}
Tracking_2nd_DLL_filter::Tracking_2nd_DLL_filter(float pdi_code)
Tracking_2nd_DLL_filter::Tracking_2nd_DLL_filter(float pdi_code) : d_pdi_code(pdi_code),
d_dlldampingratio(0.7)
{
d_pdi_code = pdi_code; // Summation interval for code
d_dlldampingratio = 0.7;
}
Tracking_2nd_DLL_filter::Tracking_2nd_DLL_filter()
Tracking_2nd_DLL_filter::Tracking_2nd_DLL_filter() : d_pdi_code(0.001),
d_dlldampingratio(0.7)
{
d_pdi_code = 0.001; // Summation interval for code
d_dlldampingratio = 0.7;
}

View File

@ -63,19 +63,15 @@ float Tracking_2nd_PLL_filter::get_carrier_nco(float PLL_discriminator)
}
Tracking_2nd_PLL_filter::Tracking_2nd_PLL_filter(float pdi_carr)
Tracking_2nd_PLL_filter::Tracking_2nd_PLL_filter(float pdi_carr) : d_pdi_carr(pdi_carr),
d_plldampingratio(0.7)
{
// PLL variables
d_pdi_carr = pdi_carr; // Summation interval for carrier
d_plldampingratio = 0.7;
}
Tracking_2nd_PLL_filter::Tracking_2nd_PLL_filter()
Tracking_2nd_PLL_filter::Tracking_2nd_PLL_filter() : d_pdi_carr(0.001),
d_plldampingratio(0.7)
{
// PLL variables
d_pdi_carr = 0.001; // Summation interval for carrier
d_plldampingratio = 0.7;
}

View File

@ -20,22 +20,6 @@
#include "tracking_FLL_PLL_filter.h"
Tracking_FLL_PLL_filter::Tracking_FLL_PLL_filter()
{
d_order = 0;
d_pll_w = 0.0;
d_pll_w0p3 = 0.0;
d_pll_w0f2 = 0.0;
d_pll_x = 0.0;
d_pll_a2 = 0.0;
d_pll_w0f = 0.0;
d_pll_a3 = 0.0;
d_pll_w0p2 = 0.0;
d_pll_b3 = 0.0;
d_pll_w0p = 0.0;
}
void Tracking_FLL_PLL_filter::set_params(float fll_bw_hz, float pll_bw_hz, int order)
{
/*

View File

@ -29,7 +29,7 @@
class Tracking_FLL_PLL_filter
{
public:
Tracking_FLL_PLL_filter();
Tracking_FLL_PLL_filter() = default;
~Tracking_FLL_PLL_filter() = default;
void set_params(float fll_bw_hz, float pll_bw_hz, int order);
void initialize(float d_acq_carrier_doppler_hz);
@ -37,17 +37,17 @@ public:
private:
// FLL + PLL filter parameters
float d_pll_w;
float d_pll_w0p3;
float d_pll_w0f2;
float d_pll_x;
float d_pll_a2;
float d_pll_w0f;
float d_pll_a3;
float d_pll_w0p2;
float d_pll_b3;
float d_pll_w0p;
int d_order;
float d_pll_w{0.0};
float d_pll_w0p3{0.0};
float d_pll_w0f2{0.0};
float d_pll_x{0.0};
float d_pll_a2{0.0};
float d_pll_w0f{0.0};
float d_pll_a3{0.0};
float d_pll_w0p2{0.0};
float d_pll_b3{0.0};
float d_pll_w0p{0.0};
int d_order{0};
};