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564 Commits

Author SHA1 Message Date
Carles Fernandez
de79147def
Fix OpenCL test if the OpenCL Platform is not ready 2019-06-24 14:33:08 +02:00
Carles Fernandez
9318fe540d
Fixes for modern OpenCL versions 2019-06-24 13:39:34 +02:00
Carles Fernandez
a2dcf223f0
Create OpenCL imported target 2019-06-24 11:25:18 +02:00
Marc Majoral
0bb38ce38b removed some not used variables + code optimization 2019-06-20 14:28:47 +02:00
Marc Majoral
05d006d1f9 Merge branch 'next' of https://github.com/mmajoral/gnss-sdr into fpga_extended_coherent_integration 2019-06-18 18:25:24 +02:00
Marc Majoral
33d1115246 added support for extended coherent integration in the FPGA. The code still needs to be optimized and cleaned. 2019-06-18 18:22:01 +02:00
Carles Fernandez
8d424a13b6
Replace boost::filesystem by std::experimental::filesystem when the later is available 2019-06-12 20:39:29 +02:00
Carles Fernandez
ca6b4b545b
Replace Boost::filesystem by std::filesystem if C++17 support is available 2019-06-10 21:41:13 +02:00
Marc Majoral
e1d01d3b97 Re-enable uio interrupts manually + do not enable interrupt generation at reset. 2019-05-13 16:30:01 +02:00
Carles Fernandez
307373e362
Avoid unnecessary copy of channel_fsm 2019-04-22 13:03:01 +02:00
Marc Majoral
bf3f66278f closed the acquisition device driver in the proper way + updated fpga block expponent. 2019-04-15 16:39:05 +02:00
Marc Majoral
059fbfedc2 changed default fft/ifft block exp 2019-04-12 15:26:47 +02:00
Marc Majoral
7a06434928 removed unnecessary function in fpga_acquisition class 2019-04-12 15:16:31 +02:00
Marc Majoral
9f80eaf0ff code cleanup 2019-04-12 11:36:30 +02:00
Marc Majoral
a628ad5906 removed FPGA dummy read 2019-04-12 10:03:57 +02:00
Marc Majoral
19e46a2ebf Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga 2019-04-10 19:53:45 +02:00
Marc Majoral
91f509abf9 write the code phase rate and the nco phase rate parameters in the FPGA 2019-04-10 11:31:34 +02:00
Javier Arribas
a79280d029 FPGA compilation error fix 2019-04-09 20:01:30 +02:00
Javier Arribas
141e101363 Bug fix that restores the acquisition and tracking destructor calls due to circular smart pointer references 2019-04-09 17:39:48 +02:00
Carles Fernandez
cc162dac9e
Code cleaning 2019-04-08 11:14:41 +02:00
Marc Majoral
4d530b0ce4 updated fft-ifft ref exponents 2019-04-05 15:59:40 +02:00
Marc Majoral
6696e378c5 updated the reference value for the gain of the fft-ifft 2019-04-05 15:15:02 +02:00
Marc Majoral
ff024e7292 cleaned unused code and added some comments. 2019-04-04 19:55:02 +02:00
Marc Majoral
eda3f21fb9 added the reading of the high_dyn parameter in the tracking adapter modules + added max_num_acqs parameter for the FPGA acquisition. 2019-04-04 16:10:29 +02:00
Marc Majoral
5bc7a778e9 commented out the old DLL and PLL filters in the tracking modules + removed some old not used code in the acquisition that was already commented out. 2019-04-02 13:10:09 +02:00
Marc Majoral
3249f55029 Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga 2019-03-27 12:38:43 +01:00
Marc Majoral
4164d28abf solved a bug: the acquisition device driver was not properly closed if double acquisition was enabled and the second acquisition was not successful. 2019-03-27 12:35:36 +01:00
Marc Majoral
47b405f92d commented out debug messages that increase the time between accquisition and tracking 2019-03-27 11:57:31 +01:00
Carles Fernandez
77851e5589
BeiDou B3I bug fixes (credits to dmiralles2019) 2019-03-26 22:34:08 +01:00
Marc Majoral
58a0de006e corrected comment 2019-03-26 16:41:20 +01:00
Marc Majoral
63cee0e63b In order to reduce the CPU workload, the FPGA acquisition does not close and open the device driver in between the first and the second acquisition anymore. 2019-03-26 16:35:19 +01:00
Marc Majoral
cbc8131677 optimized the computation of FPGA acquisition doppler shift and dopper step registers 
removed unnecessary function call
 2019-03-26 16:22:49 +01:00
Marc Majoral
2b46c79ba7 optimized the process of computing and writing the fft of the local code to the acquisition HW accelerator. 
The writing of the local code is still performed by processor instructions in a loop.
THe FPGA L2 classes were updated accordingly.
 2019-03-26 12:26:08 +01:00
Marc Majoral
905a85670c currently optimizing the FPGA-related code 2019-03-25 19:45:54 +01:00
Marc Majoral
2bae20d2fd Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga 
added second acquisition to reduce the time between acquisition and tracking when using the FPGA
moved the process of writing of the tracking local code to the HW accelerator from the start_tracking() function to the set_gnss_synchro() function (this is only applicable for the FPGA case)
there was a bug in the computation of the tracking starting position for the L1/E1 band when using the FPGA, only high sample counter values (>31 bits) were affected, due to a uint64_t*float mult.
 2019-03-22 19:03:46 +01:00
Carles Fernandez
88b60aa6b1 Remove unused includes 2019-03-20 18:08:39 +01:00
Carles Fernandez
f3d91bbd38 Remove unused includes 2019-03-20 18:00:37 +01:00
Marc Majoral
e6b661494c moved to 16 bits per local code. 2019-03-20 16:59:32 +01:00
Javier Arribas
55b1f316ed Removing gnuradio block inheritance in FPGA acquisition 2019-03-20 16:57:50 +01:00
Marc Majoral
6da82535ba Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga 2019-03-20 16:35:55 +01:00
Carles Fernandez
8a52c20e28 Add missing override keyword 2019-03-20 15:44:59 +01:00
Javier Arribas
0be8c657de Reducing the latency in the acquisition to tracking transition 2019-03-20 15:13:17 +01:00
Marc Majoral
a24d26f427 set the default sampling frequency of the HW source to 12.5 Msps and the default bandpass bandwidth to 12.5 MHz + other minor changes 2019-03-19 10:14:09 +01:00
Marc Majoral
bef7e42fb9 Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga 2019-03-18 19:37:19 +01:00
Carles Fernandez
52c69073ac
Apply clang-tidy fixes 2019-03-18 09:10:00 +01:00
Carles Fernandez
ed9aaf86ce
Fix building, apply formatting 2019-03-18 08:43:38 +01:00
Damian Miralles
dc65760122
bds_b3i: Updating branch with new changes from upstream repo 2019-03-12 10:54:17 -05:00
Damian Miralles
2b4a395dc8 bds_b3i: merging new changes, fixing D2 decoding bug 2019-03-07 09:38:49 -06:00
Carles Fernandez
dd7a52c93b
Fix headers 2019-03-06 21:54:39 +01:00
Carles Fernandez
9ce827437c Improve includes (IWYU) 2019-03-06 16:10:18 +01:00
Carles Fernandez
5b8ab9f591 Improve includes (IWYU) 2019-03-06 13:49:14 +01:00
Carles Fernandez
e7ea5c1fdd
Remove superfluous 'using google::LogMessage' 2019-03-03 13:39:35 +01:00
Carles Fernandez
fcfe63ba08
Fix defects detected by coverity scan 2019-03-01 20:49:45 +01:00
Marc Majoral
5a2dc274cf but solved: double acquisition was using uint32_t for the initial doppler estimation. Therefore when the first estimated doppler was negative it was reset to zero. 2019-03-01 20:37:14 +01:00
Damian Miralles
9ccb86dac6 Merge branch 'next' into bds_b3i 2019-03-01 13:29:10 -06:00
Damian Miralles
8782fcba69 bds_b3i: merging new changes, fixing small bugs 2019-03-01 13:28:21 -06:00
Carles Fernandez
e43b8f5284
Fix defects detected by Coverity Scan 2019-03-01 15:29:43 +01:00
Carles Fernandez
df0a77ee0d
Fix warnings 
more protection on read/write failures and some code cleaning
 2019-03-01 10:11:36 +01:00
Carles Fernandez
7c71ed9404
Merge branch 'fpga' of https://github.com/gnss-sdr/gnss-sdr into merge-fpga 
Applied checks and formatting
 2019-02-28 21:45:30 +01:00
Marc Majoral
ea86546d99 implemented double acquisition for the FPGA 2019-02-28 20:49:35 +01:00
Marc Majoral
c32e0b427a coding style + removed some unnecessary memory arrays in the FPGA E5A tracking adapter class. 2019-02-27 17:27:31 +01:00
Marc Majoral
a03ed571e6 replaced int and unsigned int by int32_t and uint32_t 
removed some unused variables
 2019-02-27 14:37:07 +01:00
Marc Majoral
8d770d9be9 more code cleaning 
removed some non used variables
 2019-02-27 13:30:09 +01:00
Marc Majoral
5e22e4c50a cleaned the FPGA acquisition code 2019-02-26 18:28:14 +01:00
Marc Majoral
cf0a37300a Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga 2019-02-25 19:21:00 +01:00
Carles Fernandez
d7d4cd09ae
Fix naming in fgpa and extra unit test implementations 2019-02-22 15:57:15 +01:00
Carles Fernandez
62a7e54359
Introduce readability-identifier-naming check 
This commit enforces naming style for Classes and global constants:
Camel_Snake_Case for Classes
UPPER_CASE for global constants
CamelCase for abstract classes
 2019-02-22 10:47:24 +01:00
Carles Fernandez
9bc771bed6
Deploy a new option -DENABLE_CLANG_TIDY to integrate clang-tidy checks and fixes into the compilation process, if found. It defaults to OFF 2019-02-21 09:59:06 +01:00
Marc Majoral
fd3eb2a80e The termination process is now done correctly when using the FPGA. 2019-02-13 17:48:14 +01:00
Carles Fernandez
31383258b0 clang-tidy: apply checks 2019-02-12 15:56:18 +01:00
Carles Fernandez
111c6291ec Revert "clang-tidy: apply performance-unnecessary-value-param check" 
This reverts commit eae967ed1a.
 2019-02-12 12:07:40 +01:00
Carles Fernandez
0c4b68c92d
clang-tidy: apply performance-move-const-arg check 
See https://clang.llvm.org/extra/clang-tidy/checks/performance-move-const-arg.html
 2019-02-12 02:07:06 +01:00
Carles Fernandez
eae967ed1a
clang-tidy: apply performance-unnecessary-value-param check 
See https://clang.llvm.org/extra/clang-tidy/checks/performance-unnecessary-value-param.html
 2019-02-12 01:00:36 +01:00
Carles Fernandez
73b7341904
clang-tidy: apply readability-braces-around-statements plus code formatting 
See http://releases.llvm.org/7.0.0/tools/clang/tools/extra/docs/clang-tidy/checks/readability-braces-around-statements.html
Code formatting applied with:
  find ../src/ -iname *.h -o -iname *.cc | xargs clang-format -i
 2019-02-11 21:13:02 +01:00
Carles Fernandez
6abebac5eb Make use of cstdint type names 2019-02-11 17:51:20 +01:00
Carles Fernandez
0707963ab5 Use cstdint type names 2019-02-11 17:17:35 +01:00
Carles Fernandez
dfc963ad86 clang-tidy: apply readability-else-after-return check 
See https://clang.llvm.org/extra/clang-tidy/checks/readability-else-after-return.html
 2019-02-11 15:53:50 +01:00
Carles Fernandez
b9c115bdf8 clang-tidy: apply modernize-use-using check 2019-02-11 13:13:06 +01:00
Carles Fernandez
4b2b205e21
Avoid throwing exceptions from destructors 
Detected by clang-tidy check bugprone-exception-escape
 2019-02-10 21:55:51 +01:00
Carles Fernandez
75bd492d96
Change CMake target names to more meaningful ones, reflecting the code tree 2019-02-10 18:34:28 +01:00
Carles Fernandez
ce051e040f
Improve target design 2019-02-10 01:13:02 +01:00
Carles Fernandez
a63d7834f4
Remove unused include 2019-02-10 00:12:19 +01:00
Carles Fernandez
dfc89868af
Fix building 2019-02-08 00:05:14 +01:00
Carles Fernandez
e5b7eaa366
Reorder static dependencies 2019-02-07 23:07:24 +01:00
Carles Fernandez
60637c6125
Reorder dependencies 2019-02-07 21:31:40 +01:00
Damian Miralles
1b7d4edf51 bds_b31: Getting new changes from upstream 2019-02-05 17:25:16 -06:00
Carles Fernandez
708b288e61
Clean CMake scripts 2019-02-04 22:44:45 +01:00
Carles Fernandez
8ae72fe458
Update to modern CMake usage 2019-02-03 19:24:44 +01:00
Marc Majoral
ec80df40dc minor corrections 2019-01-31 15:36:11 +01:00
Marc Majoral
bb0fae98c7 Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga 2019-01-30 10:28:52 +01:00
Carles Fernandez
c561d7e799
Applying code formatting rules 2019-01-28 02:29:43 +01:00
Carles Fernandez
fa19b2e6a4
Fix compilation in Mac OS and crosscompilation. 
Formatting rules applied
 2019-01-28 01:08:57 +01:00
Damian Miralles
e78ba653e6 bds b3i: Adding code to process BeiDou B3I signals 
Adds code to perform acq and trk in BeiDou B3I signals. Stages of
telemetry decoding, observables computation and pvt use existing
code on the platform. Some further testing is required
 2019-01-25 15:43:00 -06:00
Marc Majoral
f127729eb0 Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga 2019-01-25 18:02:07 +01:00
Damian Miralles
42b506d0bb bds b1i: Merging latest changes from upstream/next 2018-12-18 15:55:36 -06:00
Marc Majoral
ae61646270 Solved two bugs: 
- a minor bug in the E5A fpga acquisition adapter module: a config parameter was not correctly read.
- a bug in the tracking fpga multicorrelator module: if pilot tracking was enabled then the results of the pilot correlator were not correctly read when using the multicorrelator 3-1 HW Accelerator in the FPGA (used for GPS L5 and Galileo E5A).
 2018-12-11 14:44:42 +01:00
Carles Fernandez
f351615ef9
Apply clang-tidy fix modernize-use-bool-literals 2018-12-11 12:08:54 +01:00
Carles Fernandez
e2582586b9
Apply fixes by clang-tidy 2018-12-11 02:22:33 +01:00
Carles Fernandez
d920aa4d92
Apply fixes by clang-tidy 2018-12-11 01:56:25 +01:00
Carles Fernandez
54237770a6
Apply fixes by clang-tidy 2018-12-10 22:59:10 +01:00