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https://github.com/gnss-sdr/gnss-sdr
synced 2024-12-15 04:30:33 +00:00
optimized the computation of FPGA acquisition doppler shift and dopper step registers
removed unnecessary function call
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9d7f8be4ef
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cbc8131677
@ -111,7 +111,7 @@ void pcps_acquisition_fpga::init()
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d_num_doppler_bins = static_cast<uint32_t>(std::ceil(static_cast<double>(static_cast<int32_t>(d_doppler_max) - static_cast<int32_t>(-d_doppler_max)) / static_cast<double>(d_doppler_step))) + 1;
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acquisition_fpga->init();
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// acquisition_fpga->init();
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}
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@ -52,12 +52,7 @@
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#define LOCAL_CODE_CLEAR_MEM 0x10000000 // command to clear the internal memory of the multicorrelator
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#define MEM_LOCAL_CODE_WR_ENABLE 0x0C000000 // command to enable the ENA and WR pins of the internal memory of the multicorrelator
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#define POW_2_2 4 // 2^2 (used for the conversion of floating point numbers to integers)
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#define POW_2_29 536870912 // 2^29 (used for the conversion of floating point numbers to integers)
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#define POW_2_31 2147483648 // 2^31 (used for the conversion of floating point numbers to integers)
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//#define SELECT_LSBits 0x000003FF // Select the 10 LSbits out of a 20-bit word
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//#define SELECT_MSBbits 0x000FFC00 // Select the 10 MSbits out of a 20-bit word
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//#define SELECT_ALL_CODE_BITS 0x000FFFFF // Select a 20 bit word
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//#define SHL_CODE_BITS 1024 // shift left by 10 bits
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#define SELECT_LSBits 0x0000FFFF // Select the 10 LSbits out of a 20-bit word
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#define SELECT_MSBbits 0xFFFF0000 // Select the 10 MSbits out of a 20-bit word
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@ -116,10 +111,10 @@ Fpga_Acquisition::Fpga_Acquisition(std::string device_name,
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Fpga_Acquisition::~Fpga_Acquisition() = default;
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bool Fpga_Acquisition::init()
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{
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return true;
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}
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//bool Fpga_Acquisition::init()
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//{
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// return true;
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//}
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bool Fpga_Acquisition::set_local_code(uint32_t PRN)
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@ -132,13 +127,9 @@ bool Fpga_Acquisition::set_local_code(uint32_t PRN)
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void Fpga_Acquisition::write_local_code()
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{
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uint32_t local_code;
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int32_t k, tmp, tmp2;
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int32_t fft_data;
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d_map_base[9] = LOCAL_CODE_CLEAR_MEM;
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// write local code
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for (k = 0; k < d_vector_length; k++)
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for (uint32_t k = 0; k < d_vector_length; k++)
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{
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// tmp = d_all_fft_codes[d_nsamples_total * (d_PRN - 1) + k].real();
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// tmp2 = d_all_fft_codes[d_nsamples_total * (d_PRN - 1) + k].imag();
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@ -242,21 +233,18 @@ void Fpga_Acquisition::set_block_exp(uint32_t total_block_exp)
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void Fpga_Acquisition::set_doppler_sweep(uint32_t num_sweeps, uint32_t doppler_step, int32_t doppler_min)
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{
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float phase_step_rad_real;
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float phase_step_rad_int_temp;
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int32_t phase_step_rad_int;
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// The doppler step can never be outside the range -pi to +pi, otherwise there would be aliasing
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// The FPGA expects phase_step_rad between -1 (-pi) to +1 (+pi)
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// The FPGA also expects the phase to be negative since it produces cos(x) -j*sin(x)
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phase_step_rad_real = 2.0 * (doppler_min) / static_cast<float>(d_fs_in);
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phase_step_rad_int_temp = phase_step_rad_real * POW_2_2; // * 2^2
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phase_step_rad_int = static_cast<int32_t>(phase_step_rad_int_temp * (POW_2_29)); // * 2^29 (in total it makes x2^31 in two steps to avoid the warnings
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phase_step_rad_int = static_cast<int32_t>(phase_step_rad_real * (POW_2_31));
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d_map_base[3] = phase_step_rad_int;
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// repeat the calculation with the doppler step
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phase_step_rad_real = 2.0 * (doppler_step) / static_cast<float>(d_fs_in);
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phase_step_rad_int_temp = phase_step_rad_real * POW_2_2; // * 2^2
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phase_step_rad_int = static_cast<int32_t>(phase_step_rad_int_temp * (POW_2_29)); // * 2^29 (in total it makes x2^31 in two steps to avoid the warnings
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phase_step_rad_int = static_cast<int32_t>(phase_step_rad_real * (POW_2_31)); // * 2^29 (in total it makes x2^31 in two steps to avoid the warnings
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d_map_base[4] = phase_step_rad_int;
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// write number of doppler sweeps
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@ -58,7 +58,7 @@ public:
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uint32_t excludelimit);
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~Fpga_Acquisition();
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bool init();
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//bool init();
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bool set_local_code(uint32_t PRN);
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bool free();
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void set_doppler_sweep(uint32_t num_sweeps, uint32_t doppler_step, int32_t doppler_min);
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