Gerald LaMountain
d4d849c83d
Add refs to tracking lib for bayesian estimation
2019-05-20 12:42:43 -04:00
Javier Arribas
be5ffe6b67
Implementation of Differential Arctangent Discriminator for FLL
2019-05-15 17:38:45 +02:00
Marc Majoral
e1d01d3b97
Re-enable uio interrupts manually + do not enable interrupt generation at reset.
2019-05-13 16:30:01 +02:00
Marc Majoral
585ecf2a84
removed the activation of the flag that causes the tracking HW accelerators to trigger an interrupt upon reset.
2019-05-13 16:30:01 +02:00
Carles Fernandez
6a6ec19b63
Fix building with Boost 1.65.1 (Ubuntu 18.04)
2019-05-08 21:35:15 +02:00
Carles Fernandez
a8bcc77bfc
Add blank line
2019-05-08 19:31:13 +02:00
Carles Fernandez
5563e609ec
Fix identification of Boost version
2019-05-08 19:28:53 +02:00
Carles Fernandez
214c9d5de0
Fix building for Boost < 1.66
2019-05-08 16:15:59 +02:00
Carles Fernandez
40f0a93695
Replace boost::asio::io_service (deprecated since Boost 1.66) by boost::asio::io_context
2019-05-08 15:23:55 +02:00
Carles Fernandez
cd0e7adaf4
Correct comments. Fixes : #269
2019-05-01 14:44:12 +02:00
Carles Fernandez
692cbf3130
Do not use std::cbegin, not available in old versions of gcc
2019-04-27 18:39:20 +02:00
Carles Fernandez
3602f9772c
Use constant iterators
2019-04-27 13:34:21 +02:00
Carles Fernandez
9d36199901
Trim CN0 smoother parameters. Add it to the FPGA block
2019-04-25 15:30:11 +02:00
Carles Fernandez
42c0544c4c
Accelerate CN0 estimation
2019-04-25 14:58:30 +02:00
Carles Fernandez
50d4db9c05
Add a simple CN0 smoother
2019-04-25 08:50:21 +02:00
Carles Fernandez
7fc8d53508
Remove double assignment. Fixes #266
2019-04-14 13:01:59 +02:00
Marc Majoral
9f80eaf0ff
code cleanup
2019-04-12 11:36:30 +02:00
Marc Majoral
692978f66b
updated the PLL/DLL initialisation according to the latest changes in dll_pll_veml_tracking.cc
2019-04-11 11:44:00 +02:00
Marc Majoral
19e46a2ebf
Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga
2019-04-10 19:53:45 +02:00
Marc Majoral
1a3305fc5b
static cast
2019-04-10 19:40:34 +02:00
Marc Majoral
2555f26238
use of d_preamble_length_symbols
2019-04-10 17:18:27 +02:00
Marc Majoral
824dcebec2
immediate call to state 2 (Wide tracking and symbol synchronization) removed from pull-in state.
2019-04-10 16:53:03 +02:00
Marc Majoral
91f509abf9
write the code phase rate and the nco phase rate parameters in the FPGA
2019-04-10 11:31:34 +02:00
Javier Arribas
226edca17c
Improving tracking loop filter initialization
2019-04-09 17:36:05 +02:00
Marc Majoral
19184da0f9
The FPGA multicorrelator interrupt is enabled only once when a satellite is assigned to a particular channel. Until now the interrupt was automatically disabled by the interrupt handler of the uio driver and the multicorrelator code had to re-enable it every time. This change saves CUP cycles for real-time operation. It requires that the code that disables the interrupt in the uio driver interrupt handler is commented out.
2019-04-09 16:03:31 +02:00
Marc Majoral
2da2fa12e3
removed some non-used variables and some non-used instructions. Changed the initialisation of d_current_prn_length_samples to vector_length, instead of T_prn_mod_samples
2019-04-09 11:23:30 +02:00
Marc Majoral
6979e561b8
Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga
2019-04-04 19:55:56 +02:00
Marc Majoral
ff024e7292
cleaned unused code and added some comments.
2019-04-04 19:55:02 +02:00
Marc Majoral
eda3f21fb9
added the reading of the high_dyn parameter in the tracking adapter modules + added max_num_acqs parameter for the FPGA acquisition.
2019-04-04 16:10:29 +02:00
Javier Arribas
02db271011
Set default Galileo E1 VE and VL correlator spacing to 0.5
2019-04-03 15:28:56 +02:00
Javier Arribas
bd22ef5153
Improving DLL discriminators implementation
2019-04-03 15:25:40 +02:00
Marc Majoral
d8e8b8a5a0
solved a bug in the E1 data code generation optimization
2019-04-03 10:21:16 +02:00
Marc Majoral
553946fb65
moved the setting of the flags for the writing of the local code to the initialization, to save cpu cycles during tracking.
2019-04-02 20:36:48 +02:00
Marc Majoral
a6110eb334
moved the calculations related to the local code that is specific to the FPGA to the initialisation phase of the tracking modules to save clock cycles during real-time tracking.
2019-04-02 18:46:37 +02:00
Marc Majoral
db05be36d1
removed non essential instructions in start_tracking() function and moved them to set_gnss_synchro (which is called with a valid PRN before starting an acquisition of a new channel)
2019-04-02 15:53:16 +02:00
Marc Majoral
5bc7a778e9
commented out the old DLL and PLL filters in the tracking modules + removed some old not used code in the acquisition that was already commented out.
2019-04-02 13:10:09 +02:00
Marc Majoral
edac9923ae
updated the tracking code loop filter, the carrier filter and the d_Prompt circular buffer.
2019-04-01 12:38:45 +02:00
Marc Majoral
fb38247273
updated the tracking adapters and added new FPGA tracking correlator parameters according to what is implemented in the SW tracking correlator.
2019-03-28 12:30:57 +01:00
Marc Majoral
3098ca1a48
added the reception of messages from the telemetry module to the FPGA tracking modules.
2019-03-27 16:59:04 +01:00
Marc Majoral
905a85670c
currently optimizing the FPGA-related code
2019-03-25 19:45:54 +01:00
Marc Majoral
2bae20d2fd
Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga
...
added second acquisition to reduce the time between acquisition and tracking when using the FPGA
moved the process of writing of the tracking local code to the HW accelerator from the start_tracking() function to the set_gnss_synchro() function (this is only applicable for the FPGA case)
there was a bug in the computation of the tracking starting position for the L1/E1 band when using the FPGA, only high sample counter values (>31 bits) were affected, due to a uint64_t*float mult.
2019-03-22 19:03:46 +01:00
Carles Fernandez
6a17a33d6f
Expose more tracking parameters to the configuration: filters order, FLL usage, pull-in time
2019-03-21 19:21:39 +01:00
Marc Majoral
6da82535ba
Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga
2019-03-20 16:35:55 +01:00
Carles Fernandez
10d73da839
Fix typo
2019-03-19 20:39:23 +01:00
Carles Fernandez
c8d27eb97c
Move contructor to the beginning of the file
2019-03-19 20:37:42 +01:00
Carles Fernandez
296d6d66c9
Move constants to implementation, fix typos in comments
2019-03-19 20:16:59 +01:00
Carles Fernandez
4bc4fb9988
Remove misleading comment
2019-03-19 19:53:51 +01:00
Carles Fernandez
3cd1e70706
Fix defects detected by Coverity Scan
2019-03-19 07:53:21 +01:00
Javier Arribas
df46cdeb65
Add missing message ports to trackings
2019-03-18 21:49:59 +01:00
Carles Fernandez
2afcbb7803
Fix warning
2019-03-18 21:47:36 +01:00
