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Code Issues Releases Wiki Activity

updated the tracking adapters and added new FPGA tracking correlator parameters according to what is implemented in the SW tracking correlator.

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This commit is contained in:
Marc Majoral 2019-03-28 12:30:57 +01:00
parent 3098ca1a48
commit fb38247273
6 changed files with 331 additions and 30 deletions
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86
src/algorithms/tracking/adapters/galileo_e1_dll_pll_veml_tracking_fpga.cc
View File

@ -56,8 +56,6 @@ GalileoE1DllPllVemlTrackingFpga::GalileoE1DllPllVemlTrackingFpga(
Dll_Pll_Conf_Fpga trk_param_fpga = Dll_Pll_Conf_Fpga();
DLOG(INFO) << "role " << role;
//################# CONFIGURATION PARAMETERS ########################
std::string default_item_type = "gr_complex";
std::string item_type = configuration->property(role + ".item_type", default_item_type);
int32_t fs_in_deprecated = configuration->property("GNSS-SDR.internal_fs_hz", 2048000);
int32_t fs_in = configuration->property("GNSS-SDR.internal_fs_sps", fs_in_deprecated);
trk_param_fpga.fs_in = fs_in;
@ -68,16 +66,75 @@ GalileoE1DllPllVemlTrackingFpga::GalileoE1DllPllVemlTrackingFpga(
trk_param_fpga.dump_filename = dump_filename;
bool dump_mat = configuration->property(role + ".dump_mat", true);
trk_param_fpga.dump_mat = dump_mat;
if (configuration->property(role + ".smoother_length", 10) < 1)
{
trk_param_fpga.smoother_length = 1;
std::cout << TEXT_RED << "WARNING: Gal. E1. smoother_length must be bigger than 0. It has been set to 1" << TEXT_RESET << std::endl;
}
else
{
trk_param_fpga.smoother_length = configuration->property(role + ".smoother_length", 10);
}
float pll_bw_hz = configuration->property(role + ".pll_bw_hz", 5.0);
if (FLAGS_pll_bw_hz != 0.0) pll_bw_hz = static_cast<float>(FLAGS_pll_bw_hz);
if (FLAGS_pll_bw_hz != 0.0)
{
pll_bw_hz = static_cast<float>(FLAGS_pll_bw_hz);
}
trk_param_fpga.pll_bw_hz = pll_bw_hz;
float dll_bw_hz = configuration->property(role + ".dll_bw_hz", 0.5);
if (FLAGS_dll_bw_hz != 0.0) dll_bw_hz = static_cast<float>(FLAGS_dll_bw_hz);
if (FLAGS_dll_bw_hz != 0.0)
{
dll_bw_hz = static_cast<float>(FLAGS_dll_bw_hz);
}
trk_param_fpga.dll_bw_hz = dll_bw_hz;
float pll_bw_narrow_hz = configuration->property(role + ".pll_bw_narrow_hz", 2.0);
trk_param_fpga.pll_bw_narrow_hz = pll_bw_narrow_hz;
float dll_bw_narrow_hz = configuration->property(role + ".dll_bw_narrow_hz", 0.25);
trk_param_fpga.dll_bw_narrow_hz = dll_bw_narrow_hz;
int dll_filter_order = configuration->property(role + ".dll_filter_order", 2);
if (dll_filter_order < 1)
{
LOG(WARNING) << "dll_filter_order parameter must be 1, 2 or 3. Set to 1.";
dll_filter_order = 1;
}
if (dll_filter_order > 3)
{
LOG(WARNING) << "dll_filter_order parameter must be 1, 2 or 3. Set to 3.";
dll_filter_order = 3;
}
trk_param_fpga.dll_filter_order = dll_filter_order;
int pll_filter_order = configuration->property(role + ".pll_filter_order", 3);
if (pll_filter_order < 2)
{
LOG(WARNING) << "pll_filter_order parameter must be 2 or 3. Set to 2.";
pll_filter_order = 2;
}
if (pll_filter_order > 3)
{
LOG(WARNING) << "pll_filter_order parameter must be 2 or 3. Set to 3.";
pll_filter_order = 3;
}
trk_param_fpga.pll_filter_order = pll_filter_order;
if (pll_filter_order == 2)
{
trk_param_fpga.fll_filter_order = 1;
}
if (pll_filter_order == 3)
{
trk_param_fpga.fll_filter_order = 2;
}
bool enable_fll_pull_in = configuration->property(role + ".enable_fll_pull_in", false);
trk_param_fpga.enable_fll_pull_in = enable_fll_pull_in;
float fll_bw_hz = configuration->property(role + ".fll_bw_hz", 35.0);
trk_param_fpga.fll_bw_hz = fll_bw_hz;
float pull_in_time_s = configuration->property(role + ".pull_in_time_s", 2.0);
trk_param_fpga.pull_in_time_s = pull_in_time_s;
int32_t extend_correlation_symbols = configuration->property(role + ".extend_correlation_symbols", 1);
float early_late_space_chips = configuration->property(role + ".early_late_space_chips", 0.15);
trk_param_fpga.early_late_space_chips = early_late_space_chips;
@ -111,16 +168,29 @@ GalileoE1DllPllVemlTrackingFpga::GalileoE1DllPllVemlTrackingFpga(
char sig_[3] = "1B";
std::memcpy(trk_param_fpga.signal, sig_, 3);
int32_t cn0_samples = configuration->property(role + ".cn0_samples", 20);
if (FLAGS_cn0_samples != 20) cn0_samples = FLAGS_cn0_samples;
if (FLAGS_cn0_samples != 20)
{
cn0_samples = FLAGS_cn0_samples;
}
trk_param_fpga.cn0_samples = cn0_samples;
int32_t cn0_min = configuration->property(role + ".cn0_min", 25);
if (FLAGS_cn0_min != 25) cn0_min = FLAGS_cn0_min;
if (FLAGS_cn0_min != 25)
{
cn0_min = FLAGS_cn0_min;
}
trk_param_fpga.cn0_min = cn0_min;
int32_t max_lock_fail = configuration->property(role + ".max_lock_fail", 50);
if (FLAGS_max_lock_fail != 50) max_lock_fail = FLAGS_max_lock_fail;
if (FLAGS_max_lock_fail != 50)
{
max_lock_fail = FLAGS_max_lock_fail;
}
trk_param_fpga.max_lock_fail = max_lock_fail;
double carrier_lock_th = configuration->property(role + ".carrier_lock_th", 0.85);
if (FLAGS_carrier_lock_th != 0.85) carrier_lock_th = FLAGS_carrier_lock_th;
if (FLAGS_carrier_lock_th != 0.85)
{
carrier_lock_th = FLAGS_carrier_lock_th;
}
trk_param_fpga.carrier_lock_th = carrier_lock_th;
// FPGA configuration parameters

85
src/algorithms/tracking/adapters/galileo_e5a_dll_pll_tracking_fpga.cc
View File

@ -53,8 +53,6 @@ GalileoE5aDllPllTrackingFpga::GalileoE5aDllPllTrackingFpga(
Dll_Pll_Conf_Fpga trk_param_fpga = Dll_Pll_Conf_Fpga();
DLOG(INFO) << "role " << role;
//################# CONFIGURATION PARAMETERS ########################
std::string default_item_type = "gr_complex";
std::string item_type = configuration->property(role + ".item_type", default_item_type);
int32_t fs_in_deprecated = configuration->property("GNSS-SDR.internal_fs_hz", 12000000);
int32_t fs_in = configuration->property("GNSS-SDR.internal_fs_sps", fs_in_deprecated);
trk_param_fpga.fs_in = fs_in;
@ -65,12 +63,70 @@ GalileoE5aDllPllTrackingFpga::GalileoE5aDllPllTrackingFpga(
trk_param_fpga.dump_filename = dump_filename;
bool dump_mat = configuration->property(role + ".dump_mat", true);
trk_param_fpga.dump_mat = dump_mat;
if (configuration->property(role + ".smoother_length", 10) < 1)
{
trk_param_fpga.smoother_length = 1;
std::cout << TEXT_RED << "WARNING: Gal. E5a. smoother_length must be bigger than 0. It has been set to 1" << TEXT_RESET << std::endl;
}
else
{
trk_param_fpga.smoother_length = configuration->property(role + ".smoother_length", 10);
}
float pll_bw_hz = configuration->property(role + ".pll_bw_hz", 20.0);
if (FLAGS_pll_bw_hz != 0.0) pll_bw_hz = static_cast<float>(FLAGS_pll_bw_hz);
if (FLAGS_pll_bw_hz != 0.0)
{
pll_bw_hz = static_cast<float>(FLAGS_pll_bw_hz);
}
trk_param_fpga.pll_bw_hz = pll_bw_hz;
float dll_bw_hz = configuration->property(role + ".dll_bw_hz", 20.0);
if (FLAGS_dll_bw_hz != 0.0) dll_bw_hz = static_cast<float>(FLAGS_dll_bw_hz);
if (FLAGS_dll_bw_hz != 0.0)
{
dll_bw_hz = static_cast<float>(FLAGS_dll_bw_hz);
}
trk_param_fpga.dll_bw_hz = dll_bw_hz;
int dll_filter_order = configuration->property(role + ".dll_filter_order", 2);
if (dll_filter_order < 1)
{
LOG(WARNING) << "dll_filter_order parameter must be 1, 2 or 3. Set to 1.";
dll_filter_order = 1;
}
if (dll_filter_order > 3)
{
LOG(WARNING) << "dll_filter_order parameter must be 1, 2 or 3. Set to 3.";
dll_filter_order = 3;
}
trk_param_fpga.dll_filter_order = dll_filter_order;
int pll_filter_order = configuration->property(role + ".pll_filter_order", 3);
if (pll_filter_order < 2)
{
LOG(WARNING) << "pll_filter_order parameter must be 2 or 3. Set to 2.";
pll_filter_order = 2;
}
if (pll_filter_order > 3)
{
LOG(WARNING) << "pll_filter_order parameter must be 2 or 3. Set to 3.";
pll_filter_order = 3;
}
trk_param_fpga.pll_filter_order = pll_filter_order;
if (pll_filter_order == 2)
{
trk_param_fpga.fll_filter_order = 1;
}
if (pll_filter_order == 3)
{
trk_param_fpga.fll_filter_order = 2;
}
bool enable_fll_pull_in = configuration->property(role + ".enable_fll_pull_in", false);
trk_param_fpga.enable_fll_pull_in = enable_fll_pull_in;
float fll_bw_hz = configuration->property(role + ".fll_bw_hz", 35.0);
trk_param_fpga.fll_bw_hz = fll_bw_hz;
float pull_in_time_s = configuration->property(role + ".pull_in_time_s", 2.0);
trk_param_fpga.pull_in_time_s = pull_in_time_s;
float pll_bw_narrow_hz = configuration->property(role + ".pll_bw_narrow_hz", 5.0);
trk_param_fpga.pll_bw_narrow_hz = pll_bw_narrow_hz;
float dll_bw_narrow_hz = configuration->property(role + ".dll_bw_narrow_hz", 2.0);
@ -106,17 +162,30 @@ GalileoE5aDllPllTrackingFpga::GalileoE5aDllPllTrackingFpga(
char sig_[3] = "5X";
std::memcpy(trk_param_fpga.signal, sig_, 3);
int32_t cn0_samples = configuration->property(role + ".cn0_samples", 20);
if (FLAGS_cn0_samples != 20) cn0_samples = FLAGS_cn0_samples;
if (FLAGS_cn0_samples != 20)
{
cn0_samples = FLAGS_cn0_samples;
}
trk_param_fpga.cn0_samples = cn0_samples;
int32_t cn0_min = configuration->property(role + ".cn0_min", 25);
if (FLAGS_cn0_min != 25) cn0_min = FLAGS_cn0_min;
if (FLAGS_cn0_min != 25)
{
cn0_min = FLAGS_cn0_min;
}
trk_param_fpga.cn0_min = cn0_min;
int32_t max_lock_fail = configuration->property(role + ".max_lock_fail", 50);
if (FLAGS_max_lock_fail != 50) max_lock_fail = FLAGS_max_lock_fail;
if (FLAGS_max_lock_fail != 50)
{
max_lock_fail = FLAGS_max_lock_fail;
}
trk_param_fpga.max_lock_fail = max_lock_fail;
double carrier_lock_th = configuration->property(role + ".carrier_lock_th", 0.85);
if (FLAGS_carrier_lock_th != 0.85) carrier_lock_th = FLAGS_carrier_lock_th;
if (FLAGS_carrier_lock_th != 0.85)
{
carrier_lock_th = FLAGS_carrier_lock_th;
}
trk_param_fpga.carrier_lock_th = carrier_lock_th;
d_data_codes = nullptr;
// FPGA configuration parameters

88
src/algorithms/tracking/adapters/gps_l1_ca_dll_pll_tracking_fpga.cc
View File

@ -62,6 +62,17 @@ GpsL1CaDllPllTrackingFpga::GpsL1CaDllPllTrackingFpga(
int32_t fs_in_deprecated = configuration->property("GNSS-SDR.internal_fs_hz", 2048000);
int32_t fs_in = configuration->property("GNSS-SDR.internal_fs_sps", fs_in_deprecated);
trk_param_fpga.fs_in = fs_in;
if (configuration->property(role + ".smoother_length", 10) < 1)
{
trk_param_fpga.smoother_length = 1;
std::cout << TEXT_RED << "WARNING: GPS L1 C/A. smoother_length must be bigger than 0. It has been set to 1" << TEXT_RESET << std::endl;
}
else
{
trk_param_fpga.smoother_length = configuration->property(role + ".smoother_length", 10);
}
bool dump = configuration->property(role + ".dump", false);
trk_param_fpga.dump = dump;
std::string default_dump_filename = "./track_ch";
@ -70,15 +81,64 @@ GpsL1CaDllPllTrackingFpga::GpsL1CaDllPllTrackingFpga(
bool dump_mat = configuration->property(role + ".dump_mat", true);
trk_param_fpga.dump_mat = dump_mat;
float pll_bw_hz = configuration->property(role + ".pll_bw_hz", 50.0);
if (FLAGS_pll_bw_hz != 0.0) pll_bw_hz = static_cast<float>(FLAGS_pll_bw_hz);
if (FLAGS_pll_bw_hz != 0.0)
{
pll_bw_hz = static_cast<float>(FLAGS_pll_bw_hz);
}
trk_param_fpga.pll_bw_hz = pll_bw_hz;
float pll_bw_narrow_hz = configuration->property(role + ".pll_bw_narrow_hz", 20.0);
trk_param_fpga.pll_bw_narrow_hz = pll_bw_narrow_hz;
float dll_bw_narrow_hz = configuration->property(role + ".dll_bw_narrow_hz", 2.0);
trk_param_fpga.dll_bw_narrow_hz = dll_bw_narrow_hz;
float dll_bw_hz = configuration->property(role + ".dll_bw_hz", 2.0);
if (FLAGS_dll_bw_hz != 0.0) dll_bw_hz = static_cast<float>(FLAGS_dll_bw_hz);
if (FLAGS_dll_bw_hz != 0.0)
{
dll_bw_hz = static_cast<float>(FLAGS_dll_bw_hz);
}
trk_param_fpga.dll_bw_hz = dll_bw_hz;
int dll_filter_order = configuration->property(role + ".dll_filter_order", 2);
if (dll_filter_order < 1)
{
LOG(WARNING) << "dll_filter_order parameter must be 1, 2 or 3. Set to 1.";
dll_filter_order = 1;
}
if (dll_filter_order > 3)
{
LOG(WARNING) << "dll_filter_order parameter must be 1, 2 or 3. Set to 3.";
dll_filter_order = 3;
}
trk_param_fpga.dll_filter_order = dll_filter_order;
int pll_filter_order = configuration->property(role + ".pll_filter_order", 3);
if (pll_filter_order < 2)
{
LOG(WARNING) << "pll_filter_order parameter must be 2 or 3. Set to 2.";
pll_filter_order = 2;
}
if (pll_filter_order > 3)
{
LOG(WARNING) << "pll_filter_order parameter must be 2 or 3. Set to 3.";
pll_filter_order = 3;
}
trk_param_fpga.pll_filter_order = pll_filter_order;
if (pll_filter_order == 2)
{
trk_param_fpga.fll_filter_order = 1;
}
if (pll_filter_order == 3)
{
trk_param_fpga.fll_filter_order = 2;
}
bool enable_fll_pull_in = configuration->property(role + ".enable_fll_pull_in", false);
trk_param_fpga.enable_fll_pull_in = enable_fll_pull_in;
float fll_bw_hz = configuration->property(role + ".fll_bw_hz", 35.0);
trk_param_fpga.fll_bw_hz = fll_bw_hz;
float pull_in_time_s = configuration->property(role + ".pull_in_time_s", 2.0);
trk_param_fpga.pull_in_time_s = pull_in_time_s;
float early_late_space_chips = configuration->property(role + ".early_late_space_chips", 0.5);
trk_param_fpga.early_late_space_chips = early_late_space_chips;
float early_late_space_narrow_chips = configuration->property(role + ".early_late_space_narrow_chips", 0.5);
@ -113,16 +173,28 @@ GpsL1CaDllPllTrackingFpga::GpsL1CaDllPllTrackingFpga(
char sig_[3] = "1C";
std::memcpy(trk_param_fpga.signal, sig_, 3);
int32_t cn0_samples = configuration->property(role + ".cn0_samples", 20);
if (FLAGS_cn0_samples != 20) cn0_samples = FLAGS_cn0_samples;
if (FLAGS_cn0_samples != 20)
{
cn0_samples = FLAGS_cn0_samples;
}
trk_param_fpga.cn0_samples = cn0_samples;
int32_t cn0_min = configuration->property(role + ".cn0_min", 25);
if (FLAGS_cn0_min != 25) cn0_min = FLAGS_cn0_min;
int32_t cn0_min = configuration->property(role + ".cn0_min", 30);
if (FLAGS_cn0_min != 25)
{
cn0_min = FLAGS_cn0_min;
}
trk_param_fpga.cn0_min = cn0_min;
int32_t max_lock_fail = configuration->property(role + ".max_lock_fail", 50);
if (FLAGS_max_lock_fail != 50) max_lock_fail = FLAGS_max_lock_fail;
if (FLAGS_max_lock_fail != 50)
{
max_lock_fail = FLAGS_max_lock_fail;
}
trk_param_fpga.max_lock_fail = max_lock_fail;
double carrier_lock_th = configuration->property(role + ".carrier_lock_th", 0.85);
if (FLAGS_carrier_lock_th != 0.85) carrier_lock_th = FLAGS_carrier_lock_th;
double carrier_lock_th = configuration->property(role + ".carrier_lock_th", 0.80);
if (FLAGS_carrier_lock_th != 0.85)
{
carrier_lock_th = FLAGS_carrier_lock_th;
}
trk_param_fpga.carrier_lock_th = carrier_lock_th;
// FPGA configuration parameters

82
src/algorithms/tracking/adapters/gps_l5_dll_pll_tracking_fpga.cc
View File

@ -70,11 +70,26 @@ GpsL5DllPllTrackingFpga::GpsL5DllPllTrackingFpga(
trk_param_fpga.dump_filename = dump_filename;
bool dump_mat = configuration->property(role + ".dump_mat", true);
trk_param_fpga.dump_mat = dump_mat;
if (configuration->property(role + ".smoother_length", 10) < 1)
{
trk_param_fpga.smoother_length = 1;
std::cout << TEXT_RED << "WARNING: GPS L5. smoother_length must be bigger than 0. It has been set to 1" << TEXT_RESET << std::endl;
}
else
{
trk_param_fpga.smoother_length = configuration->property(role + ".smoother_length", 10);
}
float pll_bw_hz = configuration->property(role + ".pll_bw_hz", 50.0);
if (FLAGS_pll_bw_hz != 0.0) pll_bw_hz = static_cast<float>(FLAGS_pll_bw_hz);
if (FLAGS_pll_bw_hz != 0.0)
{
pll_bw_hz = static_cast<float>(FLAGS_pll_bw_hz);
}
trk_param_fpga.pll_bw_hz = pll_bw_hz;
float dll_bw_hz = configuration->property(role + ".dll_bw_hz", 2.0);
if (FLAGS_dll_bw_hz != 0.0) dll_bw_hz = static_cast<float>(FLAGS_dll_bw_hz);
if (FLAGS_dll_bw_hz != 0.0)
{
dll_bw_hz = static_cast<float>(FLAGS_dll_bw_hz);
}
trk_param_fpga.dll_bw_hz = dll_bw_hz;
float pll_bw_narrow_hz = configuration->property(role + ".pll_bw_narrow_hz", 2.0);
trk_param_fpga.pll_bw_narrow_hz = pll_bw_narrow_hz;
@ -82,6 +97,49 @@ GpsL5DllPllTrackingFpga::GpsL5DllPllTrackingFpga(
trk_param_fpga.dll_bw_narrow_hz = dll_bw_narrow_hz;
float early_late_space_chips = configuration->property(role + ".early_late_space_chips", 0.5);
trk_param_fpga.early_late_space_chips = early_late_space_chips;
int dll_filter_order = configuration->property(role + ".dll_filter_order", 2);
if (dll_filter_order < 1)
{
LOG(WARNING) << "dll_filter_order parameter must be 1, 2 or 3. Set to 1.";
dll_filter_order = 1;
}
if (dll_filter_order > 3)
{
LOG(WARNING) << "dll_filter_order parameter must be 1, 2 or 3. Set to 3.";
dll_filter_order = 3;
}
trk_param_fpga.dll_filter_order = dll_filter_order;
int pll_filter_order = configuration->property(role + ".pll_filter_order", 3);
if (pll_filter_order < 2)
{
LOG(WARNING) << "pll_filter_order parameter must be 2 or 3. Set to 2.";
pll_filter_order = 2;
}
if (pll_filter_order > 3)
{
LOG(WARNING) << "pll_filter_order parameter must be 2 or 3. Set to 3.";
pll_filter_order = 3;
}
trk_param_fpga.pll_filter_order = pll_filter_order;
if (pll_filter_order == 2)
{
trk_param_fpga.fll_filter_order = 1;
}
if (pll_filter_order == 3)
{
trk_param_fpga.fll_filter_order = 2;
}
bool enable_fll_pull_in = configuration->property(role + ".enable_fll_pull_in", false);
trk_param_fpga.enable_fll_pull_in = enable_fll_pull_in;
float fll_bw_hz = configuration->property(role + ".fll_bw_hz", 35.0);
trk_param_fpga.fll_bw_hz = fll_bw_hz;
float pull_in_time_s = configuration->property(role + ".pull_in_time_s", 2.0);
trk_param_fpga.pull_in_time_s = pull_in_time_s;
int32_t vector_length = std::round(static_cast<double>(fs_in) / (static_cast<double>(GPS_L5I_CODE_RATE_HZ) / static_cast<double>(GPS_L5I_CODE_LENGTH_CHIPS)));
trk_param_fpga.vector_length = vector_length;
int32_t extend_correlation_symbols = configuration->property(role + ".extend_correlation_symbols", 1);
@ -111,16 +169,28 @@ GpsL5DllPllTrackingFpga::GpsL5DllPllTrackingFpga(
char sig_[3] = "L5";
std::memcpy(trk_param_fpga.signal, sig_, 3);
int32_t cn0_samples = configuration->property(role + ".cn0_samples", 20);
if (FLAGS_cn0_samples != 20) cn0_samples = FLAGS_cn0_samples;
if (FLAGS_cn0_samples != 20)
{
cn0_samples = FLAGS_cn0_samples;
}
trk_param_fpga.cn0_samples = cn0_samples;
int32_t cn0_min = configuration->property(role + ".cn0_min", 25);
if (FLAGS_cn0_min != 25) cn0_min = FLAGS_cn0_min;
if (FLAGS_cn0_min != 25)
{
cn0_min = FLAGS_cn0_min;
}
trk_param_fpga.cn0_min = cn0_min;
int32_t max_lock_fail = configuration->property(role + ".max_lock_fail", 50);
if (FLAGS_max_lock_fail != 50) max_lock_fail = FLAGS_max_lock_fail;
if (FLAGS_max_lock_fail != 50)
{
max_lock_fail = FLAGS_max_lock_fail;
}
trk_param_fpga.max_lock_fail = max_lock_fail;
double carrier_lock_th = configuration->property(role + ".carrier_lock_th", 0.75);
if (FLAGS_carrier_lock_th != 0.85) carrier_lock_th = FLAGS_carrier_lock_th;
if (FLAGS_carrier_lock_th != 0.85)
{
carrier_lock_th = FLAGS_carrier_lock_th;
}
trk_param_fpga.carrier_lock_th = carrier_lock_th;
// FPGA configuration parameters

9
src/algorithms/tracking/libs/dll_pll_conf_fpga.cc
View File

@ -44,6 +44,15 @@ Dll_Pll_Conf_Fpga::Dll_Pll_Conf_Fpga()
dump = false;
dump_mat = true;
dump_filename = std::string("./dll_pll_dump.dat");
enable_fll_pull_in = false;
enable_fll_steady_state = false;
pull_in_time_s = 2;
fll_filter_order = 1;
pll_filter_order = 3;
dll_filter_order = 2;
fll_bw_hz = 35.0;
pll_pull_in_bw_hz = 50.0;
dll_pull_in_bw_hz = 3.0;
pll_bw_hz = 35.0;
dll_bw_hz = 2.0;
pll_bw_narrow_hz = 5.0;

11
src/algorithms/tracking/libs/dll_pll_conf_fpga.h
View File

@ -42,11 +42,22 @@ class Dll_Pll_Conf_Fpga
{
public:
/* DLL/PLL tracking configuration */
int fll_filter_order;
bool enable_fll_pull_in;
bool enable_fll_steady_state;
unsigned int pull_in_time_s;
int pll_filter_order;
int dll_filter_order;
double fs_in;
uint32_t vector_length;
bool dump;
bool dump_mat;
std::string dump_filename;
float pll_pull_in_bw_hz;
float dll_pull_in_bw_hz;
float fll_bw_hz;
float pll_bw_hz;
float dll_bw_hz;
float pll_bw_narrow_hz;