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753 Commits

Author SHA1 Message Date
Marc Majoral
9f80eaf0ff code cleanup 2019-04-12 11:36:30 +02:00
Marc Majoral
692978f66b updated the PLL/DLL initialisation according to the latest changes in dll_pll_veml_tracking.cc 2019-04-11 11:44:00 +02:00
Marc Majoral
19e46a2ebf Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga 2019-04-10 19:53:45 +02:00
Marc Majoral
1a3305fc5b static cast 2019-04-10 19:40:34 +02:00
Marc Majoral
2555f26238 use of d_preamble_length_symbols 2019-04-10 17:18:27 +02:00
Marc Majoral
824dcebec2 immediate call to state 2 (Wide tracking and symbol synchronization) removed from pull-in state. 2019-04-10 16:53:03 +02:00
Marc Majoral
91f509abf9 write the code phase rate and the nco phase rate parameters in the FPGA 2019-04-10 11:31:34 +02:00
Javier Arribas
226edca17c Improving tracking loop filter initialization 2019-04-09 17:36:05 +02:00
Marc Majoral
19184da0f9 The FPGA multicorrelator interrupt is enabled only once when a satellite is assigned to a particular channel. Until now the interrupt was automatically disabled by the interrupt handler of the uio driver and the multicorrelator code had to re-enable it every time. This change saves CUP cycles for real-time operation. It requires that the code that disables the interrupt in the uio driver interrupt handler is commented out. 2019-04-09 16:03:31 +02:00
Marc Majoral
2da2fa12e3 removed some non-used variables and some non-used instructions. Changed the initialisation of d_current_prn_length_samples to vector_length, instead of T_prn_mod_samples 2019-04-09 11:23:30 +02:00
Marc Majoral
6979e561b8 Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga 2019-04-04 19:55:56 +02:00
Marc Majoral
ff024e7292 cleaned unused code and added some comments. 2019-04-04 19:55:02 +02:00
Marc Majoral
eda3f21fb9 added the reading of the high_dyn parameter in the tracking adapter modules + added max_num_acqs parameter for the FPGA acquisition. 2019-04-04 16:10:29 +02:00
Javier Arribas
02db271011 Set default Galileo E1 VE and VL correlator spacing to 0.5 2019-04-03 15:28:56 +02:00
Javier Arribas
bd22ef5153 Improving DLL discriminators implementation 2019-04-03 15:25:40 +02:00
Marc Majoral
d8e8b8a5a0 solved a bug in the E1 data code generation optimization 2019-04-03 10:21:16 +02:00
Marc Majoral
553946fb65 moved the setting of the flags for the writing of the local code to the initialization, to save cpu cycles during tracking. 2019-04-02 20:36:48 +02:00
Marc Majoral
a6110eb334 moved the calculations related to the local code that is specific to the FPGA to the initialisation phase of the tracking modules to save clock cycles during real-time tracking. 2019-04-02 18:46:37 +02:00
Marc Majoral
db05be36d1 removed non essential instructions in start_tracking() function and moved them to set_gnss_synchro (which is called with a valid PRN before starting an acquisition of a new channel) 2019-04-02 15:53:16 +02:00
Marc Majoral
5bc7a778e9 commented out the old DLL and PLL filters in the tracking modules + removed some old not used code in the acquisition that was already commented out. 2019-04-02 13:10:09 +02:00
Marc Majoral
edac9923ae updated the tracking code loop filter, the carrier filter and the d_Prompt circular buffer. 2019-04-01 12:38:45 +02:00
Marc Majoral
fb38247273 updated the tracking adapters and added new FPGA tracking correlator parameters according to what is implemented in the SW tracking correlator. 2019-03-28 12:30:57 +01:00
Marc Majoral
3098ca1a48 added the reception of messages from the telemetry module to the FPGA tracking modules. 2019-03-27 16:59:04 +01:00
Marc Majoral
905a85670c currently optimizing the FPGA-related code 2019-03-25 19:45:54 +01:00
Marc Majoral
2bae20d2fd Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga 
added second acquisition to reduce the time between acquisition and tracking when using the FPGA
moved the process of writing of the tracking local code to the HW accelerator from the start_tracking() function to the set_gnss_synchro() function (this is only applicable for the FPGA case)
there was a bug in the computation of the tracking starting position for the L1/E1 band when using the FPGA, only high sample counter values (>31 bits) were affected, due to a uint64_t*float mult.
 2019-03-22 19:03:46 +01:00
Carles Fernandez
6a17a33d6f
Expose more tracking parameters to the configuration: filters order, FLL usage, pull-in time 2019-03-21 19:21:39 +01:00
Marc Majoral
6da82535ba Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga 2019-03-20 16:35:55 +01:00
Carles Fernandez
10d73da839
Fix typo 2019-03-19 20:39:23 +01:00
Carles Fernandez
c8d27eb97c
Move contructor to the beginning of the file 2019-03-19 20:37:42 +01:00
Carles Fernandez
296d6d66c9
Move constants to implementation, fix typos in comments 2019-03-19 20:16:59 +01:00
Carles Fernandez
4bc4fb9988
Remove misleading comment 2019-03-19 19:53:51 +01:00
Carles Fernandez
3cd1e70706
Fix defects detected by Coverity Scan 2019-03-19 07:53:21 +01:00
Javier Arribas
df46cdeb65
Add missing message ports to trackings 2019-03-18 21:49:59 +01:00
Carles Fernandez
2afcbb7803
Fix warning 2019-03-18 21:47:36 +01:00
Marc Majoral
bef7e42fb9 Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga 2019-03-18 19:37:19 +01:00
Javier Arribas
48180c967a
Replacing PLL/DLL fixed order loop filters with DLL/PLL/FLL order-configurable filters. Adding PLL false lock protection by using telemetry validation flag 2019-03-18 19:35:40 +01:00
Carles Fernandez
597ef26092
Minor fixes 2019-03-18 19:28:35 +01:00
Carles Fernandez
52c69073ac
Apply clang-tidy fixes 2019-03-18 09:10:00 +01:00
Carles Fernandez
ed9aaf86ce
Fix building, apply formatting 2019-03-18 08:43:38 +01:00
Damian Miralles
3136817737
bds_b3i: Adding BeiDou B3I PVT computation 2019-03-17 18:49:06 -05:00
Damian Miralles
dc65760122
bds_b3i: Updating branch with new changes from upstream repo 2019-03-12 10:54:17 -05:00
Damian Miralles
2b4a395dc8 bds_b3i: merging new changes, fixing D2 decoding bug 2019-03-07 09:38:49 -06:00
Carles Fernandez
dd7a52c93b
Fix headers 2019-03-06 21:54:39 +01:00
Carles Fernandez
9ce827437c Improve includes (IWYU) 2019-03-06 16:10:18 +01:00
Carles Fernandez
502bf32d83 Improve includes (IWYU) 2019-03-06 14:36:51 +01:00
Damian Miralles
de964d4a77 bds_b3i: fixing bug in b1i for d2 decoding 2019-03-05 16:00:26 -06:00
Carles Fernandez
3f4a1dba09
Remove unused include 2019-03-05 12:53:27 +01:00
Carles Fernandez
c82c7225dd Improve includes with the aid of include-what-you-use (IWYU) 
See rationale at https://github.com/include-what-you-use/include-what-you-use/blob/master/docs/WhyIWYU.md
 2019-03-05 08:59:04 +01:00
Carles Fernandez
2f6c123307
Fix header 2019-03-03 14:35:39 +01:00
Carles Fernandez
e7ea5c1fdd
Remove superfluous 'using google::LogMessage' 2019-03-03 13:39:35 +01:00
Carles Fernandez
08ce4cdd75
Sort includes, fix coverity scan defect 2019-03-03 00:15:20 +01:00
Damian Miralles
16e66834fa bds_b3I: trying to fix bug with b1i pvt 2019-03-01 15:16:37 -06:00
Carles Fernandez
fcfe63ba08
Fix defects detected by coverity scan 2019-03-01 20:49:45 +01:00
Damian Miralles
9ccb86dac6 Merge branch 'next' into bds_b3i 2019-03-01 13:29:10 -06:00
Damian Miralles
8782fcba69 bds_b3i: merging new changes, fixing small bugs 2019-03-01 13:28:21 -06:00
Carles Fernandez
2543b2aae2
Fix error 2019-03-01 16:59:29 +01:00
Carles Fernandez
e43b8f5284
Fix defects detected by Coverity Scan 2019-03-01 15:29:43 +01:00
Carles Fernandez
df0a77ee0d
Fix warnings 
more protection on read/write failures and some code cleaning
 2019-03-01 10:11:36 +01:00
Carles Fernandez
7c71ed9404
Merge branch 'fpga' of https://github.com/gnss-sdr/gnss-sdr into merge-fpga 
Applied checks and formatting
 2019-02-28 21:45:30 +01:00
Marc Majoral
ea86546d99 implemented double acquisition for the FPGA 2019-02-28 20:49:35 +01:00
Carles Fernandez
e6d2776f1b Replace std::deque by faster boost::circular_buffer 2019-02-28 14:10:44 +01:00
Marc Majoral
c32e0b427a coding style + removed some unnecessary memory arrays in the FPGA E5A tracking adapter class. 2019-02-27 17:27:31 +01:00
Marc Majoral
a03ed571e6 replaced int and unsigned int by int32_t and uint32_t 
removed some unused variables
 2019-02-27 14:37:07 +01:00
Marc Majoral
8d770d9be9 more code cleaning 
removed some non used variables
 2019-02-27 13:30:09 +01:00
Marc Majoral
2b6e7749a8 cleaned the source code of the FPGA switch and the FPGA tracking adapters 2019-02-26 19:30:08 +01:00
Marc Majoral
cf0a37300a Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga 2019-02-25 19:21:00 +01:00
Carles Fernandez
d7d4cd09ae
Fix naming in fgpa and extra unit test implementations 2019-02-22 15:57:15 +01:00
Carles Fernandez
62a7e54359
Introduce readability-identifier-naming check 
This commit enforces naming style for Classes and global constants:
Camel_Snake_Case for Classes
UPPER_CASE for global constants
CamelCase for abstract classes
 2019-02-22 10:47:24 +01:00
Carles Fernandez
a734411b86
clang-tidy: apply performance-type-promotion-in-math-fn check 2019-02-21 12:46:01 +01:00
Carles Fernandez
b3ae2c969a
clang-tidy: apply fixes 2019-02-21 10:33:20 +01:00
Carles Fernandez
9bc771bed6
Deploy a new option -DENABLE_CLANG_TIDY to integrate clang-tidy checks and fixes into the compilation process, if found. It defaults to OFF 2019-02-21 09:59:06 +01:00
Carles Fernandez
88147d4956
Fix build with Clang (not AppleClang) on macOS 2019-02-20 22:21:53 +01:00
Carles Fernandez
eedc3d5de6
clang-tidy: apply checks 2019-02-19 09:08:09 +01:00
Carles Fernandez
b5c59ee6f7
Fix defects detected by Coverity Scan 2019-02-14 22:49:36 +01:00
Carles Fernandez
31383258b0 clang-tidy: apply checks 2019-02-12 15:56:18 +01:00
Carles Fernandez
111c6291ec Revert "clang-tidy: apply performance-unnecessary-value-param check" 
This reverts commit eae967ed1a.
 2019-02-12 12:07:40 +01:00
Carles Fernandez
0c4b68c92d
clang-tidy: apply performance-move-const-arg check 
See https://clang.llvm.org/extra/clang-tidy/checks/performance-move-const-arg.html
 2019-02-12 02:07:06 +01:00
Carles Fernandez
eae967ed1a
clang-tidy: apply performance-unnecessary-value-param check 
See https://clang.llvm.org/extra/clang-tidy/checks/performance-unnecessary-value-param.html
 2019-02-12 01:00:36 +01:00
Carles Fernandez
73b7341904
clang-tidy: apply readability-braces-around-statements plus code formatting 
See http://releases.llvm.org/7.0.0/tools/clang/tools/extra/docs/clang-tidy/checks/readability-braces-around-statements.html
Code formatting applied with:
  find ../src/ -iname *.h -o -iname *.cc | xargs clang-format -i
 2019-02-11 21:13:02 +01:00
Carles Fernandez
b9c115bdf8 clang-tidy: apply modernize-use-using check 2019-02-11 13:13:06 +01:00
Carles Fernandez
4b2b205e21
Avoid throwing exceptions from destructors 
Detected by clang-tidy check bugprone-exception-escape
 2019-02-10 21:55:51 +01:00
Carles Fernandez
75bd492d96
Change CMake target names to more meaningful ones, reflecting the code tree 2019-02-10 18:34:28 +01:00
Carles Fernandez
bf65447cdf
Remove unused includes 2019-02-10 13:23:36 +01:00
Carles Fernandez
ce051e040f
Improve target design 2019-02-10 01:13:02 +01:00
Carles Fernandez
a63d7834f4
Remove unused include 2019-02-10 00:12:19 +01:00
Carles Fernandez
5d9dea9537
Clean CMake scripts 2019-02-07 20:51:50 +01:00
Damian Miralles
1b7d4edf51 bds_b31: Getting new changes from upstream 2019-02-05 17:25:16 -06:00
Carles Fernandez
dfab84b2de
Add fixes applied by clang-tidy 2019-02-05 01:31:09 +01:00
Carles Fernandez
708b288e61
Clean CMake scripts 2019-02-04 22:44:45 +01:00
Carles Fernandez
b58b07fe01
Update and clean CMake scripts 2019-02-04 20:29:42 +01:00
Carles Fernandez
8ae72fe458
Update to modern CMake usage 2019-02-03 19:24:44 +01:00
Marc Majoral
bb0fae98c7 Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga 2019-01-30 10:28:52 +01:00
Carles Fernandez
1633556504
Fix comparison warnings 2019-01-28 02:54:02 +01:00
Carles Fernandez
2389eed440
Fix comparison warning 2019-01-28 02:49:27 +01:00
Carles Fernandez
c561d7e799
Applying code formatting rules 2019-01-28 02:29:43 +01:00
Damian Miralles
7f1619483f bds_b3i: bug fix in code generation 
Moved code generation logic to use bool type to keep same notation
as the previous implementations. More testing in code is required
 2019-01-27 19:05:41 -06:00
Damian Miralles
e78ba653e6 bds b3i: Adding code to process BeiDou B3I signals 
Adds code to perform acq and trk in BeiDou B3I signals. Stages of
telemetry decoding, observables computation and pvt use existing
code on the platform. Some further testing is required
 2019-01-25 15:43:00 -06:00
Marc Majoral
f127729eb0 Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga 2019-01-25 18:02:07 +01:00
Damian Miralles
7cef679744 bds_b1i: Adding support for d2 nav decoding 2018-12-26 12:54:23 -06:00
Damian Miralles
7cdd2ee477 bds b1i: Adding geo satellites tracking and setting up structure for d2 nav decoding 2018-12-24 15:14:10 -06:00