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9,219 Commits 7 Branches 21 Tags 98 MiB
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92 Commits

Author SHA1 Message Date
Marc Majoral 8b512d997b Remove the EZDMA driver, fix time reporting when using the FPGA, and include minor fixes for the dynamic bit selection, the AD9361 FPGA signal source, and the FPGA acquisition sampling factor parameter 2023-12-20 18:56:04 +01:00
Marc Majoral 5c0826b11e
Optimize the use of the FPGA dynamic bit selection blocks. Reorder AD9361 FPGA signal source private members by size. use ssize_t write() return value. 2023-09-13 17:19:10 +02:00
Marc Majoral 4ce4682ea8 use separate files for the Xilinx DMA-proxy and the ezdma drivers 2022-12-05 19:18:31 +01:00
Marc Majoral 6e368622e2 Prefer initialization to assignment in constructors 2022-05-30 09:02:22 +02:00
Marc Majoral ab310a367a fix gain_rx2 2022-05-18 18:04:43 +02:00
Marc Majoral a1d8d8c19d make the ad9361_manager functions flexible to allow the use of two AD9361 devices when using the FPGA. 2022-05-13 18:12:25 +02:00
Marc Majoral d346e763f8 use std::array 2022-04-29 10:41:44 +02:00
Marc Majoral ea172f0d36 move all DMA control to Fpga_DMA class 2022-04-28 22:33:29 +02:00
Marc Majoral 4244944814 fix filename0 and filename1 assignment 2022-04-28 19:09:26 +02:00
Marc Majoral 3f8e22b255 added support for the Xilinx dma-proxy driver when using 64-bit processor architectures. 2022-04-28 18:41:31 +02:00
Carles Fernandez 05a7d2413d
Prefer initialization to assignment in constructors in some signal sources 2021-12-28 19:14:18 +01:00
Carles Fernandez bfb9bc88b9
CI: make clang-tidy happy 2021-12-17 19:24:05 +01:00
Marc Majoral eccf2ee746 temporarily prevent a problem with the DMA, which occurs when using petalinux 2018.3, the ezdma and when switching from tx to rx transfer mode. 2021-10-08 10:14:38 +02:00
Marc Majoral 4141164fac fixed FPGA dual-band post-processing mode. 2021-03-12 18:01:25 +01:00
Marc Majoral 27470787a0 proper initialization of samples_to_skip_. Change samples_ from uint64_t to int64_t for the proper checking of the number of samples to process. 2021-03-05 19:02:40 +01:00
Carles Fernandez 5d78b87dbb
Apply clang tidy checks: readability-isolate-declaration, readability-inconsistent-declaration-parameter-name 2021-02-24 12:08:10 +01:00
Carles Fernandez 07b401e3bc
Improve error messages in case of wrong configuration for the FPGA offloading flowgraph 2021-02-23 21:40:53 +01:00
Marc Majoral 79c968f279 modified some comments 2021-02-19 16:34:49 +01:00
Marc Majoral f85a653285 stop the receiver in a controlled way on EOF or error condition. 
+ add support for the following signal source configuration options: samples, repeat, seconds_to_skip, header_size
+ remove unused header files
 2021-02-19 13:03:22 +01:00
Marc Majoral e4de9c54de do not stop the receiver when buffer overflow is detected. 2021-02-18 12:32:44 +01:00
Carles Fernandez 73a728b3f6
Merge branch 'feature/signal_source_interface' of https://github.com/jwmelto/gnss-sdr into jwmelto-feature/signal_source_interface 2021-02-18 09:03:03 +01:00
Carles Fernandez f703990a09
Fix building when using C++11 
Update changelog
 2021-02-17 09:43:05 +01:00
Jim Melton 6e04a42c8a
clang-format 
This was much worse than I thought. I had run clang-format at some point, but
apparently I subsequently made some non-compliant changes in pretty much every
file I touched.
 2021-02-15 15:34:48 -07:00
Marc Majoral b279c3bcbd replace exception by receiver stop command 2021-02-15 21:44:05 +01:00
Jim Melton 78362e7cba add signal_source_interface 
also adds a base implementation that most signal sources should inherit from.
The gen_signal_source is inexplicably different (probably as a test fixture,
commonality was not valued).

Only the file_signal_source has been tested; all the sources are modified in the same
way, but we all know the only proof of correctness is testing.

The block factory was simplified a bit. Handling for legacy config files was pulled out
of the flowgraph; now when the "0" instance of a component (Foo0) is created, if there is
no config for it, then the legacy version (Foo) will be tried. This is different from
passing -1 for the item number (which is still supported). Theoretically, all existing
config files should still work.
 2021-02-15 11:47:13 -07:00
Marc Majoral c0e4b2aee5 dump the buffer monitor results to a file 2021-02-15 11:53:16 +01:00
Marc Majoral 03e8f97d2e real-time FPGA receiver buffer monitoring 2021-02-13 17:10:43 +01:00
Carles Fernandez 7308745f05
Apply more concise file header format 
Re-license CMake scripts with BSD-3-Clause
 2020-12-30 13:35:06 +01:00
Marc Majoral 312e8c6c9c cleaned comments 2020-11-27 12:21:10 +01:00
Marc Majoral 3047051835 The dynamic bit selector modules determine the uio device file that is assigned to them using the hardware accelerator device name in the FPGA. The Switch device name is not configurable. 2020-11-27 11:24:44 +01:00
Marc Majoral a53109c718 The sample counter, the Acquisition and the Switch determine the uio device file that is assigned to them using the hardware accelerator device name in the FPGA 2020-11-26 17:07:15 +01:00
Marc Majoral beddfb6f73 close the DMA descriptor properly. 2020-10-16 09:05:10 +02:00
Marc Majoral 933873c265 When using the FPGA in post-processing mode, start the DMA after instantiating the complete flowgraph, not before. 2020-09-10 10:08:25 +02:00
Carles Fernandez a9472dea30
Remove redundant void (clang-tidy modernize-redundant-void-arg) 2020-08-27 12:48:20 +02:00
Carles Fernandez 499de7a9f1
Update file headers 2020-07-28 16:57:15 +02:00
Carles Fernandez 8633c03cf9
Remove unused lines 
Some more const correctness
 2020-07-28 01:33:26 +02:00
Carles Fernandez 7bececeef6
Improve const correctness 
Remove all buprone conversions from signal_generator module
 2020-07-17 09:11:42 +02:00
Marc Majoral 98f1287f0e dynamic bit selection based on the estimated power of the received signal. 2020-07-16 15:42:55 +02:00
Carles Fernandez c04948fd02
Reduce number of warnings raised by bugprone-* clang-tidy checks 2020-07-10 00:37:55 +02:00
Carles Fernandez 09bcd1981c Replace std::endl by \n character. There is no need to always flush the stream. 2020-07-07 18:53:50 +02:00
Carles Fernandez fcf1b97c30
Fix call to overloded property in GCC 2020-07-03 21:52:40 +02:00
Carles Fernandez fb8e5e5c47
Fix a bug in signal sources that made the number of samples parameter ignored when too large (Fixes: #396) 2020-07-03 20:18:42 +02:00
Carles Fernandez c412d0a3f5
Fix clang warning: equality comparison with extraneous parentheses 2020-07-02 10:53:51 +02:00
Marc Majoral 6ae4ddb3b8 init nread_elements to prevent compiler warning. 2020-07-02 10:33:36 +02:00
Carles Fernandez 7634934995
Fix ccplint job 2020-07-01 20:04:40 +02:00
Marc Majoral 975f22f53d fixed program termination when using the FPGA in post-processing mode: the DMA process was not properly checking enable_DMA. 2020-07-01 17:42:40 +02:00
Carles Fernandez 2b3d4b321d
Make the adapters take the configuration pointer as const 2020-06-29 09:07:41 +02:00
Carles Fernandez df7c466de0
Sort data members in headers 2020-06-24 22:27:51 +02:00
Carles Fernandez 81af1a531b
Redesign of pointer management 
Avoid indirection caused by passing shared_ptr by reference

The block factory does not have responsability on the lifetime of their inputs

Define std::make_unique when using C++11 and make use of it

Printers are turned into unique_ptr to express ownership

Printers do not participate on the lifelime of the data, so they take const raw pointers

Modernize tests code
 2020-06-18 11:49:28 +02:00
Carles Fernandez 2df45a2d06
Remove tabs 2020-03-31 00:34:26 +02:00