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Improve error messages in case of wrong configuration for the FPGA offloading flowgraph

This commit is contained in:
Carles Fernandez 2021-02-23 21:40:53 +01:00
parent df8cdc678d
commit 07b401e3bc
No known key found for this signature in database
GPG Key ID: 4C583C52B0C3877D
7 changed files with 114 additions and 107 deletions
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82
conf/gnss-sdr_GPS_L1_FPGA.conf
View File

@ -10,77 +10,67 @@
[GNSS-SDR]
;######### GLOBAL OPTIONS ##################
;internal_fs_sps: Internal signal sampling frequency after the signal conditioning stage [samples per second].
GNSS-SDR.internal_fs_sps=4000000
GNSS-SDR.internal_fs_sps=12500000
GNSS-SDR.enable_FPGA=true
;######### SIGNAL_SOURCE CONFIG ############
SignalSource.implementation=Pass_Through
SignalSource.filename=/datalogger/signals/Agilent/New York/4msps.dat ; <- PUT YOUR FILE HERE
SignalSource.item_type=ishort
SignalSource.sampling_frequency=4000000
SignalSource.implementation=Ad9361_Fpga_Signal_Source
SignalSource.sampling_frequency=12500000
SignalSource.freq=1575420000
SignalSource.repeat=false
SignalSource.dump=false
SignalSource.dump_filename=../data/signal_source.dat
SignalSource.enable_throttle_control=false
SignalSource.enable_FPGA=true
SignalSource.switch_position=2
SignalSource.gain_mode_rx1=slow_attack
;######### SIGNAL_CONDITIONER CONFIG ############
SignalConditioner.implementation=Pass_Through
SignalConditioner.item_type=cshort
SignalConditioner.enable_FPGA=true
;######### CHANNELS GLOBAL CONFIG ############
Channels_1C.count=8
Channels.in_acquisition=1
Channel.signal=1C
Channel.enable_FPGA=true
Channels_1C.count=12
;######### ACQUISITION GLOBAL CONFIG ############
;######### GPS ACQUISITION CONFIG ############
Acquisition_1C.implementation=GPS_L1_CA_PCPS_Acquisition_Fpga
Acquisition_1C.dump=false
Acquisition_1C.dump_filename=./acq_dump.dat
Acquisition_1C.item_type=cshort
Acquisition_1C.coherent_integration_time_ms=1
Acquisition_1C.select_queue_Fpga=0;
Acquisition_1C.threshold=0.005
;Acquisition_1C.pfa=0.01
Acquisition_1C.doppler_max=10000
Acquisition_1C.doppler_step=500
Acquisition_1C.threshold=2.0
Acquisition_1C.doppler_max=50000
Acquisition_1C.doppler_step=250
Acquisition_1C.make_two_steps=true
Acquisition_1C.second_nbins=3
Acquisition_1C.doppler_step2=250
Acquisition_1C.max_num_acqs=100
;######### TRACKING GLOBAL CONFIG ############
;######### TRACKING GPS CONFIG ############
Tracking_1C.implementation=GPS_L1_CA_DLL_PLL_Tracking_Fpga
Tracking_1C.item_type=cshort
Tracking_1C.dump=false
Tracking_1C.dump_filename=../data/epl_tracking_ch_
Tracking_1C.pll_bw_hz=45.0;
Tracking_1C.extend_correlation_symbols=20
Tracking_1C.pll_bw_hz=35;
Tracking_1C.dll_bw_hz=2.0;
Tracking_1C.order=3;
Tracking_1C.pll_bw_narrow_hz=5.0;
Tracking_1C.dll_bw_narrow_hz=0.50;
Tracking_1C.fll_bw_hz=10
Tracking_1C.enable_fll_pull_in=true;
Tracking_1C.enable_fll_steady_state=false
Tracking_1C.high_dyn=true
Tracking_1C.dump=false
Tracking_1C.dump_filename=tracking_ch_
;######### TELEMETRY DECODER GPS CONFIG ############
TelemetryDecoder_1C.implementation=GPS_L1_CA_Telemetry_Decoder
TelemetryDecoder_1C.dump=false
;######### OBSERVABLES CONFIG ############
Observables.implementation=GPS_L1_CA_Observables
Observables.implementation=Hybrid_Observables
Observables.dump=false
Observables.dump_filename=./observables.dat
;######### PVT CONFIG ############
PVT.implementation=GPS_L1_CA_PVT
PVT.averaging_depth=100
PVT.flag_averaging=false
PVT.output_rate_ms=10
PVT.display_rate_ms=500
PVT.dump_filename=./PVT
PVT.nmea_dump_filename=./gnss_sdr_pvt.nmea;
PVT.flag_nmea_tty_port=false;
PVT.nmea_dump_devname=/dev/pts/4
PVT.implementation=RTKLIB_PVT
PVT.positioning_mode=Single
PVT.iono_model=OFF
PVT.trop_model=OFF
PVT.raim_fde=1
PVT.output_rate_ms=20;
PVT.display_rate_ms=500;
PVT.elevation_mask=0;
PVT.flag_rtcm_server=false
PVT.flag_rtcm_tty_port=false
PVT.rtcm_dump_devname=/dev/pts/1
PVT.dump=false
PVT.dump_filename=./PVT

2
src/algorithms/signal_source/adapters/CMakeLists.txt
View File

@ -149,6 +149,8 @@ target_include_directories(signal_source_adapters
if(ENABLE_FPGA OR ENABLE_AD9361)
target_link_libraries(signal_source_adapters
PUBLIC
signal_source_libs
PRIVATE
core_libs
)

64
src/algorithms/signal_source/adapters/ad9361_fpga_signal_source.cc
View File

@ -96,7 +96,6 @@ Ad9361FpgaSignalSource::Ad9361FpgaSignalSource(const ConfigurationInterface *con
rf_shutdown_ = configuration->property(role + ".rf_shutdown", FLAGS_rf_shutdown);
// initialize the variables that are used in post-processing mode
enable_DMA_ = false;
@ -165,10 +164,8 @@ Ad9361FpgaSignalSource::Ad9361FpgaSignalSource(const ConfigurationInterface *con
// find the uio device file corresponding to the switch.
if (find_uio_dev_file_name(device_io_name, switch_device_name, 0) < 0)
{
std::cerr << "Cannot find the FPGA uio device file corresponding to device name " << switch_device_name << std::endl;
LOG(ERROR) << "Cannot find the FPGA uio device file corresponding to device name " << switch_device_name;
// stop the receiver
queue_->push(pmt::make_any(command_event_make(200, 0)));
std::cerr << "Cannot find the FPGA uio device file corresponding to device name " << switch_device_name << '\n';
item_size_ = 0;
return;
}
@ -204,10 +201,8 @@ Ad9361FpgaSignalSource::Ad9361FpgaSignalSource(const ConfigurationInterface *con
}
else
{
std::cerr << "file_signal_source: Unable to open the samples file " << filename0.c_str() << '\n';
LOG(ERROR) << "file_signal_source: Unable to open the samples file " << filename0.c_str();
// stop the receiver
queue_->push(pmt::make_any(command_event_make(200, 0)));
std::cerr << "SignalSource: Unable to open the samples file " << filename0.c_str() << '\n';
item_size_ = 0;
return;
}
std::streamsize ss = std::cout.precision();
@ -234,10 +229,8 @@ Ad9361FpgaSignalSource::Ad9361FpgaSignalSource(const ConfigurationInterface *con
}
else
{
std::cerr << "file_signal_source: Unable to open the samples file " << filename1.c_str() << '\n';
LOG(ERROR) << "file_signal_source: Unable to open the samples file " << filename1.c_str();
// stop the receiver
queue_->push(pmt::make_any(command_event_make(200, 0)));
std::cerr << "SignalSource: Unable to open the samples file " << filename1.c_str() << '\n';
item_size_ = 0;
return;
}
std::streamsize ss = std::cout.precision();
@ -384,8 +377,7 @@ Ad9361FpgaSignalSource::Ad9361FpgaSignalSource(const ConfigurationInterface *con
catch (const std::runtime_error &e)
{
std::cerr << "Exception cached when configuring the RX chain: " << e.what() << '\n';
// stop the receiver
queue_->push(pmt::make_any(command_event_make(200, 0)));
item_size_ = 0;
return;
}
// LOCAL OSCILLATOR DDS GENERATOR FOR DUAL FREQUENCY OPERATION
@ -420,8 +412,7 @@ Ad9361FpgaSignalSource::Ad9361FpgaSignalSource(const ConfigurationInterface *con
catch (const std::runtime_error &e)
{
std::cerr << "Exception cached when configuring the TX carrier: " << e.what() << '\n';
// stop the receiver
queue_->push(pmt::make_any(command_event_make(200, 0)));
item_size_ = 0;
return;
}
}
@ -438,10 +429,8 @@ Ad9361FpgaSignalSource::Ad9361FpgaSignalSource(const ConfigurationInterface *con
// find the uio device file corresponding to the buffer monitor
if (find_uio_dev_file_name(device_io_name_buffer_monitor, buffer_monitor_device_name, 0) < 0)
{
std::cerr << "Cannot find the FPGA uio device file corresponding to device name " << buffer_monitor_device_name << std::endl;
LOG(ERROR) << "Cannot find the FPGA uio device file corresponding to device name " << buffer_monitor_device_name;
// stop the receiver
queue_->push(pmt::make_any(command_event_make(200, 0)));
std::cerr << "Cannot find the FPGA uio device file corresponding to device name " << buffer_monitor_device_name << '\n';
item_size_ = 0;
return;
}
@ -458,20 +447,16 @@ Ad9361FpgaSignalSource::Ad9361FpgaSignalSource(const ConfigurationInterface *con
// find the uio device file corresponding to the dynamic bit selector 0 module.
if (find_uio_dev_file_name(device_io_name_dyn_bit_sel_0, dyn_bit_sel_device_name, 0) < 0)
{
std::cerr << "Cannot find the FPGA uio device file corresponding to device name " << dyn_bit_sel_device_name << std::endl;
LOG(ERROR) << "Cannot find the FPGA uio device file corresponding to device name " << dyn_bit_sel_device_name;
// stop the receiver
queue_->push(pmt::make_any(command_event_make(200, 0)));
std::cerr << "Cannot find the FPGA uio device file corresponding to device name " << dyn_bit_sel_device_name << '\n';
item_size_ = 0;
return;
}
// find the uio device file corresponding to the dynamic bit selector 1 module.
if (find_uio_dev_file_name(device_io_name_dyn_bit_sel_1, dyn_bit_sel_device_name, 1) < 0)
{
std::cerr << "Cannot find the FPGA uio device file corresponding to device name " << dyn_bit_sel_device_name << std::endl;
LOG(ERROR) << "Cannot find the FPGA uio device file corresponding to device name " << dyn_bit_sel_device_name;
// stop the receiver
queue_->push(pmt::make_any(command_event_make(200, 0)));
std::cerr << "Cannot find the FPGA uio device file corresponding to device name " << dyn_bit_sel_device_name << '\n';
item_size_ = 0;
return;
}
dynamic_bit_selection_fpga = std::make_shared<Fpga_dynamic_bit_selection>(device_io_name_dyn_bit_sel_0, device_io_name_dyn_bit_sel_1);
@ -553,6 +538,7 @@ Ad9361FpgaSignalSource::~Ad9361FpgaSignalSource()
}
}
void Ad9361FpgaSignalSource::start()
{
thread_file_to_dma = std::thread([&] { run_DMA_process(filename0, filename1, samples_to_skip_, item_size_, samples_, repeat_, dma_buff_offset_pos_, queue_); });
@ -571,8 +557,7 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0, const
}
catch (const std::ifstream::failure &e)
{
std::cerr << "Exception opening file " << filename0;
LOG(ERROR) << "Exception opening file " << filename0;
std::cerr << "Exception opening file " << filename0 << '\n';
// stop the receiver
queue->push(pmt::make_any(command_event_make(200, 0)));
return;
@ -588,8 +573,7 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0, const
}
catch (const std::ifstream::failure &e)
{
std::cerr << "Exception opening file " << filename1;
LOG(ERROR) << "Exception opening file " << filename1;
std::cerr << "Exception opening file " << filename1 << '\n';
// stop the receiver
queue->push(pmt::make_any(command_event_make(200, 0)));
return;
@ -605,7 +589,6 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0, const
catch (const std::ifstream::failure &e)
{
std::cerr << "Exception skipping initial samples file " << filename0 << '\n';
LOG(ERROR) << "Exception skipping initial samples file " << filename0;
// stop the receiver
queue->push(pmt::make_any(command_event_make(200, 0)));
return;
@ -620,7 +603,6 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0, const
catch (const std::ifstream::failure &e)
{
std::cerr << "Exception skipping initial samples file " << filename1 << '\n';
LOG(ERROR) << "Exception skipping initial samples file " << filename1;
// stop the receiver
queue->push(pmt::make_any(command_event_make(200, 0)));
return;
@ -641,7 +623,6 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0, const
if (tx_fd < 0)
{
std::cerr << "Cannot open loop device\n";
LOG(ERROR) << "Cannot open loop device";
// stop the receiver
queue->push(pmt::make_any(command_event_make(200, 0)));
return;
@ -680,7 +661,6 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0, const
catch (const std::ifstream::failure &e)
{
std::cerr << "Exception reading file " << filename0 << '\n';
LOG(ERROR) << "Exception reading file " << filename0;
break;
}
if (infile1)
@ -712,7 +692,6 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0, const
catch (const std::ifstream::failure &e)
{
std::cerr << "Exception reading file " << filename1 << '\n';
LOG(ERROR) << "Exception reading file " << filename1;
break;
}
if (infile1)
@ -741,7 +720,6 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0, const
if (num_bytes_sent != num_transferred_bytes)
{
std::cerr << "Error: DMA could not send all the required samples\n";
LOG(ERROR) << "Error: DMA could not send all the required samples";
break;
}
@ -763,7 +741,6 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0, const
catch (const std::ifstream::failure &e)
{
std::cerr << "Exception resetting the position of the next byte to be extracted to zero " << filename0 << '\n';
LOG(ERROR) << "Exception resetting the position of the next byte to be extracted to zero " << filename0;
break;
}
@ -776,7 +753,6 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0, const
catch (const std::ifstream::failure &e)
{
std::cerr << "Exception skipping initial samples file " << filename0 << '\n';
LOG(ERROR) << "Exception skipping initial samples file " << filename0;
break;
}
@ -789,7 +765,6 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0, const
catch (const std::ifstream::failure &e)
{
std::cerr << "Exception setting the position of the next byte to be extracted to zero " << filename1 << '\n';
LOG(ERROR) << "Exception resetting the position of the next byte to be extracted to zero " << filename1;
break;
}
@ -800,7 +775,6 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0, const
catch (const std::ifstream::failure &e)
{
std::cerr << "Exception skipping initial samples file " << filename1 << '\n';
LOG(ERROR) << "Exception skipping initial samples file " << filename1;
break;
}
}
@ -822,7 +796,6 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0, const
if (close(tx_fd) < 0)
{
std::cerr << "Error closing loop device " << '\n';
LOG(ERROR) << "Error closing loop device " << std::endl;
}
try
@ -832,7 +805,6 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0, const
catch (const std::ifstream::failure &e)
{
std::cerr << "Exception closing file " << filename0 << '\n';
LOG(ERROR) << "Exception closing file " << filename0 << std::endl;
}
if (num_freq_bands_ > 1)
@ -844,7 +816,6 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0, const
catch (const std::ifstream::failure &e)
{
std::cerr << "Exception closing file " << filename1 << '\n';
LOG(ERROR) << "Exception closing file " << filename1 << std::endl;
}
}
@ -871,6 +842,7 @@ void Ad9361FpgaSignalSource::run_dynamic_bit_selection_process()
}
}
void Ad9361FpgaSignalSource::run_buffer_monitor_process()
{
bool enable_ovf_check_buffer_monitor_active = true;

9
src/algorithms/signal_source/adapters/ad9361_fpga_signal_source.h
View File

@ -67,13 +67,13 @@ private:
const std::string buffer_monitor_device_name = "buffer_monitor"; // buffer monitor device name
const std::string default_dump_filename = std::string("FPGA_buffer_monitor_dump.dat");
// perform dynamic bit selection every 500 ms by default
static const uint32_t Gain_control_period_ms = 500;
const uint32_t Gain_control_period_ms = 500;
// check buffer overflow and perform buffer monitoring every 1s by default
static const uint32_t buffer_monitor_period_ms = 1000;
const uint32_t buffer_monitor_period_ms = 1000;
// buffer overflow and buffer monitoring initial delay
static const uint32_t buffer_monitoring_initial_delay_ms = 2000;
const uint32_t buffer_monitoring_initial_delay_ms = 2000;
// sample block size when running in post-processing mode
static const int sample_block_size = 16384;
const int sample_block_size = 16384;
void run_DMA_process(const std::string &Filename1,
const std::string &Filename2,
@ -139,7 +139,6 @@ private:
bool enable_DMA_;
bool enable_dynamic_bit_selection_;
bool enable_ovf_check_buffer_monitor_active_;
bool enable_ovf_check_buffer_monitor_;
bool dump_;
bool rf_shutdown_;

19
src/core/libs/uio_fpga.cc
View File

@ -19,10 +19,11 @@
#include "gnss_sdr_filesystem.h"
#include <algorithm> // sort
#include <cstdlib> // atoi, size_t
#include <fstream> // ifstream
#include <iostream> // cout
#include <locale> // isdigit
#include <sstream> // std::stringstream
#include <exception>
#include <fstream> // ifstream
#include <iostream> // cout
#include <locale> // isdigit
#include <sstream> // std::stringstream
#include <vector>
@ -188,7 +189,15 @@ int32_t find_uio_num(const std::string &device_name, uint32_t device_num)
int32_t find_uio_dev_file_name(std::string &device_file_name, const std::string &device_name, uint32_t device_num)
{
int32_t uio_num = find_uio_num(device_name, device_num);
int32_t uio_num = 0;
try
{
uio_num = find_uio_num(device_name, device_num);
}
catch (const std::exception &e)
{
return -1;
}
if (uio_num >= 0)
{
std::stringstream device_file_name_tmp;

43
src/core/receiver/gnss_flowgraph.cc
View File

@ -306,7 +306,7 @@ void GNSSFlowgraph::connect()
{
if (connect_fpga_flowgraph() != 0)
{
LOG(ERROR) << "Unable to connect flowgraph with FPFA off-loading";
std::cerr << "Unable to connect flowgraph with FPGA off-loading\n";
print_help();
return;
}
@ -315,7 +315,7 @@ void GNSSFlowgraph::connect()
{
if (connect_desktop_flowgraph() != 0)
{
LOG(ERROR) << "Unable to connect flowgraph";
std::cerr << "Unable to connect flowgraph\n";
print_help();
return;
}
@ -323,7 +323,7 @@ void GNSSFlowgraph::connect()
#else
if (connect_desktop_flowgraph() != 0)
{
LOG(ERROR) << "Unable to connect flowgraph";
std::cerr << "Unable to connect flowgraph\n";
print_help();
return;
}
@ -521,7 +521,26 @@ int GNSSFlowgraph::disconnect_desktop_flowgraph()
#if ENABLE_FPGA
int GNSSFlowgraph::connect_fpga_flowgraph()
{
// Check that the Signal Source has been instantiated successfully
for (auto& src : sig_source_)
{
if (src == nullptr)
{
help_hint_ += " * Undefined SignalSource.implementation in the configuration file.\n";
return 1;
}
if (src->item_size() == 0)
{
help_hint_ += " * The global configuration parameter GNSS-SDR.enable_FPGA is set to true,\n";
help_hint_ += " but gnss-sdr does not appear to be executed in an FPGA-equipped platform,\n";
help_hint_ += " or there are some required files that are missing.\n";
return 1;
}
}
// Connect blocks to the top_block
if (connect_channels() != 0)
{
return 1;
@ -951,7 +970,16 @@ int GNSSFlowgraph::connect_fpga_sample_counter()
}
catch (const std::exception& e)
{
LOG(ERROR) << "Can't connect FPGA sample counter: " << e.what();
std::string reported_error(e.what());
if (std::string::npos != reported_error.find(std::string("filesystem")))
{
help_hint_ += " * The global configuration parameter GNSS-SDR.enable_FPGA is set to true,\n";
help_hint_ += " but gnss-sdr does not appear to be executed in an FPGA-equipped platform.\n";
}
else
{
LOG(ERROR) << reported_error;
}
top_block_->disconnect_all();
return 1;
}
@ -979,6 +1007,13 @@ int GNSSFlowgraph::disconnect_fpga_sample_counter()
int GNSSFlowgraph::connect_signal_sources_to_signal_conditioners()
{
if (enable_fpga_offloading_)
{
help_hint_ += " * The global configuration parameter GNSS-SDR.enable_FPGA is set to true,\n";
help_hint_ += " but gnss-sdr was not compiled with the -DENABLE_FPGA=ON building option.\n";
top_block_->disconnect_all();
return 1;
}
unsigned int signal_conditioner_ID = 0;
for (int i = 0; i < sources_count_; i++)
{

2
src/tests/unit-tests/signal-processing-blocks/acquisition/galileo_e1_pcps_ambiguous_acquisition_test_fpga.cc
View File

@ -1,6 +1,6 @@
/*!
* \file galileo_e1_pcps_acquisition_test_fpga.cc
* \brief This class implements an acquisition test Galileo FPFA acquisition
* \brief This class implements an acquisition test Galileo FPGA acquisition
* \authors <ul>
* <li> Marc Majoral, 2019. mmajoral(at)cttc.cat
* <li> Luis Esteve, 2012. luis(at)epsilon-formacion.com