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Remove the EZDMA driver, fix time reporting when using the FPGA, and include minor fixes for the dynamic bit selection, the AD9361 FPGA signal source, and the FPGA acquisition sampling factor parameter

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This commit is contained in:
Marc Majoral 2023-12-20 16:32:40 +01:00 committed by Carles Fernandez
parent 071f78202d
commit 8b512d997b
21 changed files with 138 additions and 109 deletions
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2
src/algorithms/acquisition/adapters/galileo_e1_pcps_ambiguous_acquisition_fpga.cc
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@ -44,7 +44,7 @@ GalileoE1PcpsAmbiguousAcquisitionFpga::GalileoE1PcpsAmbiguousAcquisitionFpga(
out_streams_(out_streams),
acquire_pilot_(configuration->property(role + ".acquire_pilot", false))
{
acq_parameters_.SetFromConfiguration(configuration, role_, fpga_buff_num, fpga_blk_exp, GALILEO_E1_CODE_CHIP_RATE_CPS, GALILEO_E1_B_CODE_LENGTH_CHIPS);
acq_parameters_.SetFromConfiguration(configuration, role_, fpga_buff_num, fpga_blk_exp, downsampling_factor_default, GALILEO_E1_CODE_CHIP_RATE_CPS, GALILEO_E1_B_CODE_LENGTH_CHIPS);
if (FLAGS_doppler_max != 0)
{

1
src/algorithms/acquisition/adapters/galileo_e1_pcps_ambiguous_acquisition_fpga.h
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@ -182,6 +182,7 @@ public:
void set_resampler_latency(uint32_t latency_samples __attribute__((unused))) override{};
private:
static const uint32_t downsampling_factor_default = 4;
static const uint32_t fpga_buff_num = 0; // L1/E1 band
static const uint32_t fpga_blk_exp = 13; // default block exponent

2
src/algorithms/acquisition/adapters/galileo_e5a_pcps_acquisition_fpga.cc
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@ -43,7 +43,7 @@ GalileoE5aPcpsAcquisitionFpga::GalileoE5aPcpsAcquisitionFpga(
acq_pilot_(configuration->property(role + ".acquire_pilot", false)),
acq_iq_(configuration->property(role + ".acquire_iq", false))
{
acq_parameters_.SetFromConfiguration(configuration, role_, fpga_buff_num, fpga_blk_exp, GALILEO_E5A_CODE_CHIP_RATE_CPS, GALILEO_E5A_CODE_LENGTH_CHIPS);
acq_parameters_.SetFromConfiguration(configuration, role_, fpga_buff_num, fpga_blk_exp, downsampling_factor_default, GALILEO_E5A_CODE_CHIP_RATE_CPS, GALILEO_E5A_CODE_LENGTH_CHIPS);
if (FLAGS_doppler_max != 0)
{

1
src/algorithms/acquisition/adapters/galileo_e5a_pcps_acquisition_fpga.h
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@ -189,6 +189,7 @@ public:
void set_resampler_latency(uint32_t latency_samples __attribute__((unused))) override{};
private:
static const uint32_t downsampling_factor_default = 1;
static const uint32_t fpga_buff_num = 1; // L5/E5a band
static const uint32_t fpga_blk_exp = 13; // default block exponent

2
src/algorithms/acquisition/adapters/galileo_e5b_pcps_acquisition_fpga.cc
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@ -43,7 +43,7 @@ GalileoE5bPcpsAcquisitionFpga::GalileoE5bPcpsAcquisitionFpga(const Configuration
acq_pilot_(configuration->property(role + ".acquire_pilot", false)),
acq_iq_(configuration->property(role + ".acquire_iq", false))
{
acq_parameters_.SetFromConfiguration(configuration, role_, fpga_buff_num, fpga_blk_exp, GALILEO_E5B_CODE_CHIP_RATE_CPS, GALILEO_E5B_CODE_LENGTH_CHIPS);
acq_parameters_.SetFromConfiguration(configuration, role_, fpga_buff_num, fpga_blk_exp, downsampling_factor_default, GALILEO_E5B_CODE_CHIP_RATE_CPS, GALILEO_E5B_CODE_LENGTH_CHIPS);
if (FLAGS_doppler_max != 0)
{
acq_parameters_.doppler_max = FLAGS_doppler_max;

1
src/algorithms/acquisition/adapters/galileo_e5b_pcps_acquisition_fpga.h
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@ -188,6 +188,7 @@ public:
void set_resampler_latency(uint32_t latency_samples __attribute__((unused))) override{};
private:
static const uint32_t downsampling_factor_default = 1;
static const uint32_t fpga_buff_num = 1; // E5b band
static const uint32_t fpga_blk_exp = 13; // default block exponent

2
src/algorithms/acquisition/adapters/gps_l1_ca_pcps_acquisition_fpga.cc
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@ -43,7 +43,7 @@ GpsL1CaPcpsAcquisitionFpga::GpsL1CaPcpsAcquisitionFpga(
in_streams_(in_streams),
out_streams_(out_streams)
{
acq_parameters_.SetFromConfiguration(configuration, role, fpga_buff_num, fpga_blk_exp, GPS_L1_CA_CODE_RATE_CPS, GPS_L1_CA_CODE_LENGTH_CHIPS);
acq_parameters_.SetFromConfiguration(configuration, role, fpga_buff_num, fpga_blk_exp, downsampling_factor_default, GPS_L1_CA_CODE_RATE_CPS, GPS_L1_CA_CODE_LENGTH_CHIPS);
DLOG(INFO) << "role " << role;

2
src/algorithms/acquisition/adapters/gps_l1_ca_pcps_acquisition_fpga.h
View File

@ -186,7 +186,7 @@ public:
private:
static const uint32_t NUM_PRNs = 32;
static const uint32_t downsampling_factor_default = 4;
static const uint32_t fpga_buff_num = 0; // L1/E1 band
static const uint32_t fpga_blk_exp = 10; // default block exponent

2
src/algorithms/acquisition/adapters/gps_l2_m_pcps_acquisition_fpga.cc
View File

@ -43,7 +43,7 @@ GpsL2MPcpsAcquisitionFpga::GpsL2MPcpsAcquisitionFpga(
in_streams_(in_streams),
out_streams_(out_streams)
{
acq_parameters_.SetFromConfiguration(configuration, role, fpga_buff_num, fpga_blk_exp, GPS_L2_M_CODE_RATE_CPS, GPS_L2_M_CODE_LENGTH_CHIPS);
acq_parameters_.SetFromConfiguration(configuration, role, fpga_buff_num, fpga_blk_exp, downsampling_factor_default, GPS_L2_M_CODE_RATE_CPS, GPS_L2_M_CODE_LENGTH_CHIPS);
LOG(INFO) << "role " << role;

1
src/algorithms/acquisition/adapters/gps_l2_m_pcps_acquisition_fpga.h
View File

@ -150,6 +150,7 @@ public:
void set_resampler_latency(uint32_t latency_samples __attribute__((unused))) override{};
private:
static const uint32_t downsampling_factor_default = 1;
static const uint32_t fpga_buff_num = 0; // L2 band
static const uint32_t fpga_blk_exp = 13; // default block exponent

2
src/algorithms/acquisition/adapters/gps_l5i_pcps_acquisition_fpga.cc
View File

@ -44,7 +44,7 @@ GpsL5iPcpsAcquisitionFpga::GpsL5iPcpsAcquisitionFpga(
in_streams_(in_streams),
out_streams_(out_streams)
{
acq_parameters_.SetFromConfiguration(configuration, role, fpga_buff_num, fpga_blk_exp, GPS_L5I_CODE_RATE_CPS, GPS_L5I_CODE_LENGTH_CHIPS);
acq_parameters_.SetFromConfiguration(configuration, role, fpga_buff_num, fpga_blk_exp, downsampling_factor_default, GPS_L5I_CODE_RATE_CPS, GPS_L5I_CODE_LENGTH_CHIPS);
LOG(INFO) << "role " << role;

2
src/algorithms/acquisition/adapters/gps_l5i_pcps_acquisition_fpga.h
View File

@ -186,7 +186,7 @@ public:
private:
static const uint32_t NUM_PRNs = 32;
static const uint32_t downsampling_factor_default = 1;
static const uint32_t fpga_buff_num = 1; // L5/E5a band
static const uint32_t fpga_blk_exp = 13; // default block exponent

4
src/algorithms/acquisition/libs/acq_conf_fpga.cc
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@ -23,7 +23,7 @@
#include <iostream>
void Acq_Conf_Fpga::SetFromConfiguration(const ConfigurationInterface *configuration,
const std::string &role, uint32_t sel_queue_fpga, uint32_t blk_exp, double chip_rate, double code_length_chips)
const std::string &role, uint32_t sel_queue_fpga, uint32_t blk_exp, uint32_t downsampling_factor_default, double chip_rate, double code_length_chips)
{
// sampling frequency
const int64_t fs_in_deprecated = configuration->property("GNSS-SDR.internal_fs_hz", fs_in);
@ -33,7 +33,7 @@ void Acq_Conf_Fpga::SetFromConfiguration(const ConfigurationInterface *configura
doppler_max = configuration->property(role + ".doppler_max", doppler_max);
// downsampling factor
downsampling_factor = configuration->property(role + ".downsampling_factor", downsampling_factor);
downsampling_factor = configuration->property(role + ".downsampling_factor", downsampling_factor_default);
fs_in = fs_in / downsampling_factor;

2
src/algorithms/acquisition/libs/acq_conf_fpga.h
View File

@ -35,7 +35,7 @@ class Acq_Conf_Fpga
public:
Acq_Conf_Fpga() = default;
void SetFromConfiguration(const ConfigurationInterface *configuration, const std::string &role, uint32_t sel_queue_fpga, uint32_t blk_exp, double chip_rate, double code_length_chips);
void SetFromConfiguration(const ConfigurationInterface *configuration, const std::string &role, uint32_t sel_queue_fpga, uint32_t blk_exp, uint32_t downsampling_factor_default, double chip_rate, double code_length_chips);
/* PCPS Acquisition configuration */
std::string device_name = "uio0";

32
src/algorithms/signal_source/adapters/ad9361_fpga_signal_source.cc
View File

@ -73,7 +73,7 @@ Ad9361FpgaSignalSource::Ad9361FpgaSignalSource(const ConfigurationInterface *con
tx_bandwidth_(configuration->property(role + ".tx_bandwidth", static_cast<uint64_t>(500000))),
Fpass_(configuration->property(role + ".Fpass", static_cast<float>(0.0))),
Fstop_(configuration->property(role + ".Fstop", static_cast<float>(0.0))),
num_freq_bands_(2),
num_input_files_(1),
dma_buff_offset_pos_(0),
in_stream_(in_stream),
out_stream_(out_stream),
@ -95,16 +95,14 @@ Ad9361FpgaSignalSource::Ad9361FpgaSignalSource(const ConfigurationInterface *con
{
const double seconds_to_skip = configuration->property(role + ".seconds_to_skip", 0.0);
const size_t header_size = configuration->property(role + ".header_size", 0);
const int num_ch_rx1 = configuration->property("Channels_1C.count", 0) +
configuration->property("Channels_1B.count", 0);
const int num_ch_rx2 = (configuration->property("Channels_L2.count", 0) > 0) ? configuration->property("Channels_L2.count", 0) : configuration->property("Channels_L5.count", 0) + configuration->property("Channels_5X.count", 0);
// number of frequency bands
if (num_ch_rx2 == 0)
{
num_freq_bands_ = 1;
}
const bool enable_rx1_band((configuration->property("Channels_1C.count", 0) > 0) ||
(configuration->property("Channels_1B.count", 0) > 0));
const bool enable_rx2_band((configuration->property("Channels_L2.count", 0) > 0) ||
(configuration->property("Channels_L5.count", 0) > 0) ||
(configuration->property("Channels_5X.count", 0) > 0));
const uint32_t num_freq_bands = ((enable_rx1_band == true) and (enable_rx2_band == true)) ? 2 : 1;
if (freq0_ == 0)
{
// use ".freq0"
@ -132,6 +130,7 @@ Ad9361FpgaSignalSource::Ad9361FpgaSignalSource(const ConfigurationInterface *con
if (filename0_.empty())
{
num_input_files_ = 2;
filename0_ = configuration->property(role + ".filename0", empty_string);
filename1_ = configuration->property(role + ".filename1", empty_string);
}
@ -141,7 +140,7 @@ Ad9361FpgaSignalSource::Ad9361FpgaSignalSource(const ConfigurationInterface *con
// if more than one input file are specified then the DMA transfer the samples to both the L1 and the L2/L5 frequency channels.
if (filename1_.empty())
{
if (num_ch_rx1 != 0)
if (enable_rx1_band)
{
dma_buff_offset_pos_ = 2;
}
@ -427,14 +426,14 @@ Ad9361FpgaSignalSource::Ad9361FpgaSignalSource(const ConfigurationInterface *con
return;
}
buffer_monitor_fpga = std::make_shared<Fpga_buffer_monitor>(device_io_name_buffer_monitor, num_freq_bands_, dump_, dump_filename);
buffer_monitor_fpga = std::make_shared<Fpga_buffer_monitor>(device_io_name_buffer_monitor, num_freq_bands, dump_, dump_filename);
thread_buffer_monitor = std::thread([&] { run_buffer_monitor_process(); });
}
// dynamic bits selection
if (enable_dynamic_bit_selection_)
{
dynamic_bit_selection_fpga = std::make_shared<Fpga_dynamic_bit_selection>(num_freq_bands_);
dynamic_bit_selection_fpga = std::make_shared<Fpga_dynamic_bit_selection>(enable_rx1_band, enable_rx2_band);
thread_dynamic_bit_selection = std::thread([&] { run_dynamic_bit_selection_process(); });
}
@ -559,7 +558,8 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0_, cons
}
}
// skip the initial samples if needed
// skip the initial samples if neededsrc/algorithms/signal_source/libs/ad9361_manager.cc
uint64_t bytes_to_skeep = samples_to_skip * item_size;
try
{
@ -607,7 +607,7 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0_, cons
// if only one frequency band is used then clear the samples corresponding to the unused frequency band
uint32_t dma_index = 0;
if (num_freq_bands_ == 1)
if (num_input_files_ == 1)
{
// if only one file is enabled then clear the samples corresponding to the frequency band that is not used.
for (int index0 = 0; index0 < (nread_elements); index0 += 2)
@ -660,7 +660,7 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0_, cons
}
// read filename 1 (if enabled)
if (num_freq_bands_ > 1)
if (num_input_files_ > 1)
{
dma_index = 0;
try
@ -781,7 +781,7 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0_, cons
std::cerr << "Exception closing file " << filename0_ << '\n';
}
if (num_freq_bands_ > 1)
if (num_input_files_ > 1)
{
try
{

6
src/algorithms/signal_source/adapters/ad9361_fpga_signal_source.h
View File

@ -23,11 +23,7 @@
#include "concurrent_queue.h"
#include "fpga_buffer_monitor.h"
#if INTPTR_MAX == INT64_MAX // 64-bit processor architecture
#include "fpga_dma-proxy.h"
#else
#include "fpga_ezdma.h"
#endif
#include "fpga_dynamic_bit_selection.h"
#include "fpga_switch.h"
#include "gnss_block_interface.h"
@ -145,7 +141,7 @@ private:
float Fpass_;
float Fstop_;
uint32_t num_freq_bands_;
uint32_t num_input_files_;
uint32_t dma_buff_offset_pos_;
uint32_t in_stream_;
uint32_t out_stream_;

9
src/algorithms/signal_source/libs/CMakeLists.txt
View File

@ -19,13 +19,8 @@ if(ENABLE_FPGA OR ENABLE_AD9361)
set(OPT_SIGNAL_SOURCE_LIB_HEADERS ${OPT_SIGNAL_SOURCE_LIB_HEADERS} fpga_dynamic_bit_selection.h)
set(OPT_SIGNAL_SOURCE_LIB_SOURCES ${OPT_SIGNAL_SOURCE_LIB_SOURCES} fpga_buffer_monitor.cc)
set(OPT_SIGNAL_SOURCE_LIB_HEADERS ${OPT_SIGNAL_SOURCE_LIB_HEADERS} fpga_buffer_monitor.h)
if(ARCH_64BITS)
set(OPT_SIGNAL_SOURCE_LIB_SOURCES ${OPT_SIGNAL_SOURCE_LIB_SOURCES} fpga_dma-proxy.cc)
set(OPT_SIGNAL_SOURCE_LIB_HEADERS ${OPT_SIGNAL_SOURCE_LIB_HEADERS} fpga_dma-proxy.h)
else()
set(OPT_SIGNAL_SOURCE_LIB_SOURCES ${OPT_SIGNAL_SOURCE_LIB_SOURCES} fpga_ezdma.cc)
set(OPT_SIGNAL_SOURCE_LIB_HEADERS ${OPT_SIGNAL_SOURCE_LIB_HEADERS} fpga_ezdma.h)
endif()
set(OPT_SIGNAL_SOURCE_LIB_SOURCES ${OPT_SIGNAL_SOURCE_LIB_SOURCES} fpga_dma-proxy.cc)
set(OPT_SIGNAL_SOURCE_LIB_HEADERS ${OPT_SIGNAL_SOURCE_LIB_HEADERS} fpga_dma-proxy.h)
endif()

10
src/algorithms/signal_source/libs/ad9361_manager.cc
View File

@ -337,6 +337,7 @@ bool config_ad9361_rx_local(uint64_t bandwidth_,
struct iio_channel *rx_chan0; // stream channel 0
struct iio_channel *rx_chan1; // stream channel 1
struct iio_channel *chn; // phy channel
struct iio_channel *lo_chn; // phy channel
int ret;
@ -419,12 +420,12 @@ bool config_ad9361_rx_local(uint64_t bandwidth_,
}
// Configure LO channel
std::cout << "* Acquiring " << RX_DEV_A << " LO RX channel 0\n";
if (!get_lo_chan(ad9361_phy, RX, 0, &chn))
if (!get_lo_chan(ad9361_phy, RX, 0, &lo_chn))
{
std::cout << "RX LO channel 0not found\n";
throw std::runtime_error("RX LO channel 0not found");
}
wr_ch_lli(chn, "frequency", freq0_);
wr_ch_lli(lo_chn, "frequency", freq0_);
if (enable_ad9361_b)
{
@ -485,7 +486,10 @@ bool config_ad9361_rx_local(uint64_t bandwidth_,
if (rx2_enable_)
{
iio_channel_enable(rx_chan1);
ad9361_fmcomms5_multichip_sync(ctx, FIXUP_INTERFACE_TIMING | CHECK_SAMPLE_RATES);
if (enable_ad9361_b)
{
ad9361_fmcomms5_multichip_sync(ctx, FIXUP_INTERFACE_TIMING | CHECK_SAMPLE_RATES);
}
}
if (!rx1_enable_ and !rx2_enable_)
{

143
src/algorithms/signal_source/libs/fpga_dynamic_bit_selection.cc
View File

@ -26,38 +26,24 @@
#include <iostream> // for cout
#include <sys/mman.h> // for mmap
Fpga_dynamic_bit_selection::Fpga_dynamic_bit_selection(uint32_t num_freq_bands)
: d_num_freq_bands(num_freq_bands)
Fpga_dynamic_bit_selection::Fpga_dynamic_bit_selection(bool enable_rx1_band, bool enable_rx2_band)
: d_enable_rx1_band(enable_rx1_band), d_enable_rx2_band(enable_rx2_band)
{
d_map_base = std::vector<volatile unsigned *>(d_num_freq_bands);
d_device_descriptors = std::vector<int>(d_num_freq_bands);
d_shift_out_bits = std::vector<uint32_t>(d_num_freq_bands);
for (uint32_t k = 0; k < d_num_freq_bands; k++)
if (d_enable_rx1_band)
{
// find the uio device file corresponding to the dynamic bit selector 0 module.
std::string device_name;
if (find_uio_dev_file_name(device_name, dyn_bit_sel_device_name, 0) < 0)
{
std::cerr << "Cannot find the FPGA uio device file corresponding to device name " << dyn_bit_sel_device_name << '\n';
return;
}
// dynamic bits selection corresponding to frequency band 1
if ((d_device_descriptors[k] = open(device_name.c_str(), O_RDWR | O_SYNC)) == -1)
{
LOG(WARNING) << "Cannot open deviceio" << device_name;
}
d_map_base[k] = reinterpret_cast<volatile unsigned *>(mmap(nullptr, FPGA_PAGE_SIZE,
PROT_READ | PROT_WRITE, MAP_SHARED, d_device_descriptors[k], 0));
open_device(&d_map_base_freq_band_1, d_dev_descr_freq_band_1, 0);
if (d_map_base[k] == reinterpret_cast<void *>(-1))
{
LOG(WARNING) << "Cannot map the FPGA dynamic bit selection module in frequency band 1 into tracking memory";
std::cout << "Could not map dynamic bit selection memory corresponding to frequency band 1.\n";
}
// init bit selection corresponding to frequency band 1
d_shift_out_bits_freq_band_1 = shift_out_bits_default;
d_map_base_freq_band_1[0] = d_shift_out_bits_freq_band_1;
}
if (d_enable_rx2_band)
{
open_device(&d_map_base_freq_band_2, d_dev_descr_freq_band_2, 1);
// init bit selection corresopnding to frequency band 1
d_shift_out_bits[k] = shift_out_bits_default;
d_map_base[k][0] = d_shift_out_bits[k];
// init bit selection corresponding to frequency band 1
d_shift_out_bits_freq_band_2 = shift_out_bits_default;
d_map_base_freq_band_2[0] = d_shift_out_bits_freq_band_2;
}
DLOG(INFO) << "Dynamic bit selection FPGA class created";
}
@ -65,48 +51,87 @@ Fpga_dynamic_bit_selection::Fpga_dynamic_bit_selection(uint32_t num_freq_bands)
Fpga_dynamic_bit_selection::~Fpga_dynamic_bit_selection()
{
close_devices();
if (d_enable_rx1_band)
{
close_device(d_map_base_freq_band_1, d_dev_descr_freq_band_1);
}
if (d_enable_rx2_band)
{
close_device(d_map_base_freq_band_2, d_dev_descr_freq_band_2);
}
}
void Fpga_dynamic_bit_selection::bit_selection()
{
for (uint32_t k = 0; k < d_num_freq_bands; k++)
if (d_enable_rx1_band)
{
// estimated signal power
uint32_t rx_signal_power = d_map_base[k][1];
bit_selection_per_rf_band(d_map_base_freq_band_1, d_shift_out_bits_freq_band_1);
}
// dynamic bit selection
if (rx_signal_power > Power_Threshold_High)
{
if (d_shift_out_bits[k] < shift_out_bit_max)
{
d_shift_out_bits[k] = d_shift_out_bits[k] + 1;
}
}
else if (rx_signal_power < Power_Threshold_Low)
{
if (d_shift_out_bits[k] > shift_out_bits_min)
{
d_shift_out_bits[k] = d_shift_out_bits[k] - 1;
}
}
// update bit selection corresopnding to frequency band 1
d_map_base[k][0] = d_shift_out_bits[k];
if (d_enable_rx2_band)
{
bit_selection_per_rf_band(d_map_base_freq_band_2, d_shift_out_bits_freq_band_2);
}
}
void Fpga_dynamic_bit_selection::close_devices()
void Fpga_dynamic_bit_selection::open_device(volatile unsigned **d_map_base, int &d_dev_descr, int freq_band)
{
for (uint32_t k = 0; k < d_num_freq_bands; k++)
// find the uio device file corresponding to the dynamic bit selector 0 module.
std::string device_name;
if (find_uio_dev_file_name(device_name, dyn_bit_sel_device_name, freq_band) < 0)
{
auto *aux = const_cast<unsigned *>(d_map_base[k]);
if (munmap(static_cast<void *>(aux), FPGA_PAGE_SIZE) == -1)
{
std::cout << "Failed to unmap memory uio\n";
}
close(d_device_descriptors[k]);
std::cerr << "Cannot find the FPGA uio device file corresponding to device name " << dyn_bit_sel_device_name << '\n';
std::cout << "Cannot find the FPGA uio device file corresponding to device name " << dyn_bit_sel_device_name << '\n';
return;
}
// dynamic bits selection corresponding to frequency band 1
if ((d_dev_descr = open(device_name.c_str(), O_RDWR | O_SYNC)) == -1)
{
LOG(WARNING) << "Cannot open deviceio" << device_name;
std::cout << "Cannot open deviceio" << device_name << std::endl;
}
*d_map_base = reinterpret_cast<volatile unsigned *>(mmap(nullptr, FPGA_PAGE_SIZE,
PROT_READ | PROT_WRITE, MAP_SHARED, d_dev_descr, 0));
if (*d_map_base == reinterpret_cast<void *>(-1))
{
LOG(WARNING) << "Cannot map the FPGA dynamic bit selection module in frequency band 1 into tracking memory";
std::cout << "Could not map dynamic bit selection memory corresponding to frequency band 1.\n";
}
}
void Fpga_dynamic_bit_selection::bit_selection_per_rf_band(volatile unsigned *d_map_base, uint32_t shift_out_bits)
{
// estimated signal power
uint32_t rx_signal_power = d_map_base[1];
// dynamic bit selection
if (rx_signal_power > Power_Threshold_High)
{
if (shift_out_bits < shift_out_bit_max)
{
shift_out_bits = shift_out_bits + 1;
}
}
else if (rx_signal_power < Power_Threshold_Low)
{
if (shift_out_bits > shift_out_bits_min)
{
shift_out_bits = shift_out_bits - 1;
}
}
// update bit selection corresopnding to frequency band 1
d_map_base[0] = shift_out_bits;
}
void Fpga_dynamic_bit_selection::close_device(volatile unsigned *d_map_base, int &d_dev_descr)
{
auto *aux = const_cast<unsigned *>(d_map_base);
if (munmap(static_cast<void *>(aux), FPGA_PAGE_SIZE) == -1)
{
std::cout << "Failed to unmap memory uio\n";
}
close(d_dev_descr);
}

19
src/algorithms/signal_source/libs/fpga_dynamic_bit_selection.h
View File

@ -43,7 +43,7 @@ public:
/*!
* \brief Constructor
*/
explicit Fpga_dynamic_bit_selection(uint32_t num_freq_bands);
explicit Fpga_dynamic_bit_selection(bool enable_rx1_band, bool enable_rx2_band);
/*!
* \brief Destructor
@ -69,13 +69,18 @@ private:
static const uint32_t Power_Threshold_High = 9000;
static const uint32_t Power_Threshold_Low = 3000;
void close_devices(void);
void open_device(volatile unsigned **d_map_base, int &d_dev_descr, int freq_band);
void bit_selection_per_rf_band(volatile unsigned *d_map_base, uint32_t shift_out_bits);
void close_device(volatile unsigned *d_map_base, int &d_dev_descr);
std::vector<volatile unsigned*> d_map_base;
std::vector<int> d_device_descriptors;
std::vector<uint32_t> d_shift_out_bits;
uint32_t d_num_freq_bands; // number of frequency bands
volatile unsigned *d_map_base_freq_band_1;
volatile unsigned *d_map_base_freq_band_2;
int d_dev_descr_freq_band_1;
int d_dev_descr_freq_band_2;
uint32_t d_shift_out_bits_freq_band_1;
uint32_t d_shift_out_bits_freq_band_2;
bool d_enable_rx1_band;
bool d_enable_rx2_band;
};

2
src/core/libs/gnss_sdr_fpga_sample_counter.cc
View File

@ -206,7 +206,7 @@ int gnss_sdr_fpga_sample_counter::general_work(int noutput_items __attribute__((
out[0].Channel_ID = -1;
out[0].fs = fs;
if ((sample_counter - last_sample_counter) > samples_per_report)
if ((sample_counter - last_sample_counter) >= samples_per_report)
{
last_sample_counter = sample_counter;