Carles Fernandez
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6836ac44fb
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Fix building for -DENABLE_PLUTOSDR=ON
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2024-08-19 14:21:59 +02:00 |
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Carles Fernandez
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126421f847
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Catch all exceptions
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2024-08-19 12:30:25 +02:00 |
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Carles Fernandez
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df1314945f
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Fix CMake lists
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2024-08-19 10:56:11 +02:00 |
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Carles Fernandez
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7aa19d9642
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Use lock_guard instead of unique_lock
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2024-08-18 10:57:40 +02:00 |
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Marc Majoral
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d0caa64c5f
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Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga_signal_sources
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2024-08-09 15:47:02 +02:00 |
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Carles Fernandez
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a19d260281
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Fix formatting
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2024-08-08 14:05:03 +02:00 |
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Xavier Guerrero-Pau
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c8c46bc3c5
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Moved decimation factor count variable to the class
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2024-08-08 12:03:46 +02:00 |
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Marc Majoral
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19a152c6ce
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Replaced the AD9361 FPGA signal source with the ADRV9361_Z7035 FPGA and the FMCOMMS5 FPGA signal sources.
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2024-07-30 22:28:52 +02:00 |
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Marc Majoral
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40cc8de587
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make clang-format happy
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2024-07-25 09:44:21 +02:00 |
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Marc Majoral
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2df08c48fa
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make cpplint happy
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2024-07-24 15:55:26 +02:00 |
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Marc Majoral
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ef3afccfbc
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make cpplint happy
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2024-07-24 15:28:07 +02:00 |
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Marc Majoral
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468e840eb1
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Fix FPGA-related CMakefile flags
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2024-07-24 13:22:03 +02:00 |
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Marc Majoral
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f2acb7dc2f
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fix FPGA signal source names for consistency
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2024-07-24 11:02:44 +02:00 |
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Marc Majoral
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5b06bc34bc
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Detect if the spidev driver is installed when the ENABLE_MAX2771 flag is set. Detect if the DMA proxy driver is installed when the ENABLE_DMA_PROXY flag is set. Check if ENABLE_FPGA is set when either ENABLE_MAX2771 or ENABLE_DMA_PROXY is set.
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2024-07-23 17:03:06 +02:00 |
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Marc Majoral
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4b715866b5
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fix signal source names for consistency
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2024-07-19 12:06:53 +02:00 |
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Marc Majoral
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9567e95e33
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Adjust cross-compilation flags to properly support FPGA signal sources
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2024-07-19 10:11:44 +02:00 |
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Marc Majoral
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d24c35854a
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Add the MAX2771_EVKIT FPGA signal source and the ENABLE_FPGA_MAX2771_EVKIT flag to enable it.
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2024-07-18 16:33:25 +02:00 |
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Marc Majoral
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ac7bdc919b
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Decouple the FPGA DMA signal source from the AD9361 FPGA signal source.
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2024-07-15 19:10:00 +02:00 |
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Carles Fernandez
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079ef0f07d
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Improve error handling of UDP connections
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2024-05-06 18:58:09 +02:00 |
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Carles Fernandez
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4515e67b3f
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Fixes for the embedded Abseil
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2024-05-01 08:39:22 +02:00 |
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Carles Fernandez
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95596b8f91
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Soft transition from Gflags and Glog to Abseil. Some CI fixes
|
2024-04-29 08:27:33 +02:00 |
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Carles Fernandez
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7e79945529
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Update Flexiband_Signal_Source to admit modern GNU Radio versions
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2024-04-05 13:37:45 +02:00 |
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Carles Fernandez
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f446bf3238
|
Add missing include
Fix compilation against glog-0.7.0
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2024-02-19 17:54:18 +01:00 |
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Carles Fernandez
|
fe5523c565
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Fix spelling errors detected by lintian
|
2024-01-23 14:42:46 +01:00 |
|
Carles Fernandez
|
9618918aee
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Improve formatting consistency
|
2023-12-21 14:46:27 +01:00 |
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Carles Fernandez
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c498809bfb
|
Better initialization for Fpga_dynamic_bit_selection constructor
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2023-12-21 14:25:01 +01:00 |
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Carles Fernandez
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4916c6c8e8
|
Fix member initializations, potential data race conditions, and minor performance issues detected by Coverity Scan
Never throw from main
|
2023-12-21 13:57:41 +01:00 |
|
Carles Fernandez
|
d8fabdb4ac
|
Add [[maybe_unused]] to silence warnings
|
2023-12-21 10:18:12 +01:00 |
|
Marc Majoral
|
dfbdd4bc76
|
fix comment
|
2023-12-20 18:56:04 +01:00 |
|
Marc Majoral
|
3df8b9e83f
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remove EZDMA files
|
2023-12-20 18:56:04 +01:00 |
|
Marc Majoral
|
8b512d997b
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Remove the EZDMA driver, fix time reporting when using the FPGA, and include minor fixes for the dynamic bit selection, the AD9361 FPGA signal source, and the FPGA acquisition sampling factor parameter
|
2023-12-20 18:56:04 +01:00 |
|
Carles Fernandez
|
4b60f8a7f2
|
Fix performance inefficiencies detected by Coverity Scan
|
2023-12-01 10:19:39 +01:00 |
|
Carles Fernandez
|
bd1f9e5ad9
|
Fix performance inefficiencies detected by Coverity Scan
|
2023-11-30 09:48:04 +01:00 |
|
Carles Fernandez
|
1818c88983
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Fix data race conditions and performance inefficiencies, update CHANGELOG
|
2023-11-28 18:06:41 +01:00 |
|
Carles Fernandez
|
9034ce44cb
|
Fix data race conditions detected by Coverity Scan
|
2023-11-28 09:48:59 +01:00 |
|
Carles Fernandez
|
5842f72f52
|
This cast is required in some environments
|
2023-11-14 15:12:16 +01:00 |
|
Carles Fernandez
|
7132ee720a
|
Remove useless casts
|
2023-11-14 13:42:44 +01:00 |
|
Carles Fernandez
|
392b557a0a
|
four_bit_cpx_file_signal_source: initialize all variables
|
2023-11-04 15:42:05 +01:00 |
|
Javier Arribas
|
e24a5df69e
|
Increase the IIO API FIFO size
|
2023-09-27 09:52:19 +02:00 |
|
Marc Majoral
|
5c0826b11e
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Optimize the use of the FPGA dynamic bit selection blocks. Reorder AD9361 FPGA signal source private members by size. use ssize_t write() return value.
|
2023-09-13 17:19:10 +02:00 |
|
Carles Fernandez
|
dd42c5c1b0
|
Improve formatting
|
2023-07-09 16:57:56 +02:00 |
|
Carles Fernandez
|
a29f52e2e4
|
Make clang-tidy happy
|
2023-07-05 19:37:35 +02:00 |
|
Javier Arribas
|
4f9a9068e9
|
Bug fix in iio signal source and ip packet source
|
2023-07-05 15:51:01 +02:00 |
|
Javier Arribas
|
8e42b55f8d
|
Code cleaning
|
2023-07-05 12:02:50 +02:00 |
|
Javier Arribas
|
1517bb1ab8
|
Make Clang-format happy
|
2023-07-05 11:37:33 +02:00 |
|
Javier Arribas
|
1cf508ad20
|
Code cleaning
|
2023-07-04 17:45:20 +02:00 |
|
Javier Arribas
|
be2e5d8d5e
|
Adding c2bits sample stream to UDP custom source
|
2023-06-09 14:09:18 +02:00 |
|
Javier Arribas
|
9e3cfd4997
|
Merge branch 'next' of github.com:gnss-sdr/gnss-sdr into pps_lime
|
2023-04-11 09:35:33 +02:00 |
|
Jim Melton
|
9c8dd1929d
|
REALLY suppress tags this time
|
2023-02-28 14:13:31 -07:00 |
|
Javier Arribas
|
ada631185b
|
Merge branch 'next' of github.com:gnss-sdr/gnss-sdr into pps_lime
|
2023-02-16 14:49:11 +01:00 |
|