2018-03-02 10:30:36 +00:00
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/*!
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* \file ad9361_fpga_signal_source.h
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2021-12-28 18:14:18 +00:00
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* \brief signal source for Analog Devices front-end AD9361 connected directly
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* to FPGA accelerators.
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* This source implements only the AD9361 control. It is NOT compatible with
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* conventional SDR acquisition and tracking blocks.
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* Please use the fmcomms2 source if conventional SDR acquisition and tracking
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* is selected in the configuration file.
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2018-03-02 10:30:36 +00:00
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*
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2020-07-28 14:57:15 +00:00
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* -----------------------------------------------------------------------------
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2018-03-02 10:30:36 +00:00
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*
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2020-12-30 12:35:06 +00:00
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* GNSS-SDR is a Global Navigation Satellite System software-defined receiver.
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2018-03-02 10:30:36 +00:00
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* This file is part of GNSS-SDR.
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*
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2020-12-30 12:35:06 +00:00
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* Copyright (C) 2010-2020 (see AUTHORS file for a list of contributors)
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2020-02-08 00:20:02 +00:00
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* SPDX-License-Identifier: GPL-3.0-or-later
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2018-03-02 10:30:36 +00:00
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*
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2020-07-28 14:57:15 +00:00
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* -----------------------------------------------------------------------------
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2018-03-02 10:30:36 +00:00
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*/
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2020-02-08 09:10:46 +00:00
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#ifndef GNSS_SDR_AD9361_FPGA_SIGNAL_SOURCE_H
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#define GNSS_SDR_AD9361_FPGA_SIGNAL_SOURCE_H
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2018-03-02 10:30:36 +00:00
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2019-07-16 15:41:12 +00:00
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#include "concurrent_queue.h"
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2021-02-13 16:10:43 +00:00
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#include "fpga_buffer_monitor.h"
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2022-12-05 18:18:31 +00:00
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#include "fpga_dma-proxy.h"
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2020-07-16 13:42:55 +00:00
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#include "fpga_dynamic_bit_selection.h"
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2018-04-05 13:05:46 +00:00
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#include "fpga_switch.h"
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2018-12-09 21:00:09 +00:00
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#include "gnss_block_interface.h"
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2021-02-15 22:34:48 +00:00
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#include "signal_source_base.h"
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2019-07-16 15:41:12 +00:00
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#include <pmt/pmt.h>
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2018-08-11 12:31:35 +00:00
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#include <cstdint>
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2019-08-17 11:56:54 +00:00
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#include <memory>
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2020-07-01 15:42:40 +00:00
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#include <mutex>
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2018-03-02 10:30:36 +00:00
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#include <string>
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2019-09-28 19:59:05 +00:00
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#include <thread>
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2018-03-02 10:30:36 +00:00
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2020-11-01 12:37:19 +00:00
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/** \addtogroup Signal_Source
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* \{ */
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/** \addtogroup Signal_Source_adapters
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* \{ */
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2018-03-02 10:30:36 +00:00
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class ConfigurationInterface;
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2021-02-09 22:47:34 +00:00
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class Ad9361FpgaSignalSource : public SignalSourceBase
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2018-03-02 10:30:36 +00:00
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{
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public:
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2020-06-29 07:07:41 +00:00
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Ad9361FpgaSignalSource(const ConfigurationInterface *configuration,
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2020-06-18 09:49:28 +00:00
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const std::string &role, unsigned int in_stream,
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unsigned int out_stream, Concurrent_Queue<pmt::pmt_t> *queue);
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2018-03-02 10:30:36 +00:00
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2018-05-01 10:02:50 +00:00
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~Ad9361FpgaSignalSource();
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2018-03-02 10:30:36 +00:00
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2020-11-29 09:15:28 +00:00
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void start() override;
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2020-09-09 08:34:23 +00:00
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2018-03-02 10:30:36 +00:00
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inline size_t item_size() override
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{
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return item_size_;
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}
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void connect(gr::top_block_sptr top_block) override;
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void disconnect(gr::top_block_sptr top_block) override;
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gr::basic_block_sptr get_left_block() override;
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gr::basic_block_sptr get_right_block() override;
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private:
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const std::string switch_device_name = std::string("AXIS_Switch_v1_0_0"); // Switch UIO device name
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const std::string dyn_bit_sel_device_name = std::string("dynamic_bits_selector"); // Switch dhnamic bit selector device name
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const std::string buffer_monitor_device_name = std::string("buffer_monitor"); // buffer monitor device name
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const std::string default_dump_filename = std::string("FPGA_buffer_monitor_dump.dat");
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const std::string default_rf_port_select = std::string("A_BALANCED");
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const std::string default_gain_mode = std::string("slow_attack");
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2022-04-28 16:41:31 +00:00
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const std::string empty_string;
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const double default_tx_attenuation_db = -10.0;
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const double default_manual_gain_rx1 = 64.0;
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const double default_manual_gain_rx2 = 64.0;
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const uint64_t default_bandwidth = 12500000;
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2020-07-16 13:42:55 +00:00
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// perform dynamic bit selection every 500 ms by default
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2021-02-23 20:40:53 +00:00
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const uint32_t Gain_control_period_ms = 500;
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2021-02-13 16:10:43 +00:00
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// check buffer overflow and perform buffer monitoring every 1s by default
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const uint32_t buffer_monitor_period_ms = 1000;
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// buffer overflow and buffer monitoring initial delay
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const uint32_t buffer_monitoring_initial_delay_ms = 2000;
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2021-02-19 12:03:22 +00:00
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// sample block size when running in post-processing mode
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const int sample_block_size = 16384;
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2021-02-19 12:03:22 +00:00
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2021-02-24 11:08:10 +00:00
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void run_DMA_process(const std::string &filename0,
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const std::string &filename1,
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2021-02-19 12:03:22 +00:00
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uint64_t &samples_to_skip,
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size_t &item_size,
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int64_t &samples,
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2021-02-19 12:03:22 +00:00
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bool &repeat,
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uint32_t &dma_buff_offset_pos,
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Concurrent_Queue<pmt::pmt_t> *queue);
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2020-06-24 20:27:51 +00:00
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2020-08-27 10:48:20 +00:00
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void run_dynamic_bit_selection_process();
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2021-02-13 16:10:43 +00:00
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void run_buffer_monitor_process();
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2020-07-16 13:42:55 +00:00
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2020-06-24 20:27:51 +00:00
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std::thread thread_file_to_dma;
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2020-07-16 13:42:55 +00:00
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std::thread thread_dynamic_bit_selection;
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2021-02-13 16:10:43 +00:00
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std::thread thread_buffer_monitor;
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2020-06-24 20:27:51 +00:00
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std::shared_ptr<Fpga_Switch> switch_fpga;
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2020-07-16 13:42:55 +00:00
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std::shared_ptr<Fpga_dynamic_bit_selection> dynamic_bit_selection_fpga;
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2021-02-13 16:10:43 +00:00
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std::shared_ptr<Fpga_buffer_monitor> buffer_monitor_fpga;
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2022-04-28 16:41:31 +00:00
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std::shared_ptr<Fpga_DMA> dma_fpga;
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2021-12-28 18:14:18 +00:00
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std::mutex dma_mutex;
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std::mutex dynamic_bit_selection_mutex;
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std::mutex buffer_monitor_mutex;
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Concurrent_Queue<pmt::pmt_t> *queue_;
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2018-03-02 10:30:36 +00:00
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std::string gain_mode_rx1_;
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std::string gain_mode_rx2_;
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std::string rf_port_select_;
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std::string filter_file_;
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2019-10-09 18:50:06 +00:00
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std::string filter_source_;
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std::string filter_filename_;
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2022-04-28 16:41:31 +00:00
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std::string filename0_;
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std::string filename1_;
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2020-06-24 20:27:51 +00:00
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double rf_gain_rx1_;
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double rf_gain_rx2_;
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2023-09-13 15:19:10 +00:00
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double scale_dds_dbfs_;
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double phase_dds_deg_;
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double tx_attenuation_db_;
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2022-05-13 16:12:25 +00:00
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uint64_t freq0_; // frequency of local oscillator for ADRV9361-A 0
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uint64_t freq1_; // frequency of local oscillator for ADRV9361-B (if present)
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2020-06-24 20:27:51 +00:00
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uint64_t sample_rate_;
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uint64_t bandwidth_;
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2021-12-28 18:14:18 +00:00
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uint64_t samples_to_skip_;
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int64_t samples_;
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2023-09-13 15:19:10 +00:00
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uint64_t freq_dds_tx_hz_;
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uint64_t freq_rf_tx_hz_;
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uint64_t tx_bandwidth_;
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2019-10-09 18:50:06 +00:00
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float Fpass_;
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float Fstop_;
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2023-12-20 15:32:40 +00:00
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uint32_t num_input_files_;
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2021-12-28 18:14:18 +00:00
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uint32_t dma_buff_offset_pos_;
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2018-08-11 12:31:35 +00:00
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uint32_t in_stream_;
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uint32_t out_stream_;
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2021-02-13 16:10:43 +00:00
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int32_t switch_position_;
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2019-09-28 19:59:05 +00:00
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2023-09-13 15:19:10 +00:00
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size_t item_size_;
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bool enable_dds_lo_;
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2020-06-24 20:27:51 +00:00
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bool filter_auto_;
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bool quadrature_;
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bool rf_dc_;
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bool bb_dc_;
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bool rx1_enable_;
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2020-06-25 00:50:07 +00:00
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bool rx2_enable_;
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2019-10-01 20:26:30 +00:00
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bool enable_DMA_;
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2020-07-16 13:42:55 +00:00
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bool enable_dynamic_bit_selection_;
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2021-02-15 10:53:16 +00:00
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bool enable_ovf_check_buffer_monitor_active_;
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bool dump_;
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2019-10-13 21:38:06 +00:00
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bool rf_shutdown_;
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2021-02-19 12:03:22 +00:00
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bool repeat_;
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2018-03-02 10:30:36 +00:00
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};
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2020-11-01 12:37:19 +00:00
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/** \} */
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/** \} */
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2020-02-08 09:10:46 +00:00
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#endif // GNSS_SDR_AD9361_FPGA_SIGNAL_SOURCE_H
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