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58 Commits

Author SHA1 Message Date
Marc Majoral 8b512d997b Remove the EZDMA driver, fix time reporting when using the FPGA, and include minor fixes for the dynamic bit selection, the AD9361 FPGA signal source, and the FPGA acquisition sampling factor parameter 2023-12-20 18:56:04 +01:00
Marc Majoral 5c0826b11e
Optimize the use of the FPGA dynamic bit selection blocks. Reorder AD9361 FPGA signal source private members by size. use ssize_t write() return value. 2023-09-13 17:19:10 +02:00
Marc Majoral 4ce4682ea8 use separate files for the Xilinx DMA-proxy and the ezdma drivers 2022-12-05 19:18:31 +01:00
Marc Majoral a1d8d8c19d make the ad9361_manager functions flexible to allow the use of two AD9361 devices when using the FPGA. 2022-05-13 18:12:25 +02:00
Marc Majoral 916b12eef6 fix code for 32-bit processor architecture 2022-04-29 12:16:48 +02:00
Marc Majoral 3f8e22b255 added support for the Xilinx dma-proxy driver when using 64-bit processor architectures. 2022-04-28 18:41:31 +02:00
Carles Fernandez 05a7d2413d
Prefer initialization to assignment in constructors in some signal sources 2021-12-28 19:14:18 +01:00
Marc Majoral 27470787a0 proper initialization of samples_to_skip_. Change samples_ from uint64_t to int64_t for the proper checking of the number of samples to process. 2021-03-05 19:02:40 +01:00
Carles Fernandez 5d78b87dbb
Apply clang tidy checks: readability-isolate-declaration, readability-inconsistent-declaration-parameter-name 2021-02-24 12:08:10 +01:00
Carles Fernandez 07b401e3bc
Improve error messages in case of wrong configuration for the FPGA offloading flowgraph 2021-02-23 21:40:53 +01:00
Marc Majoral f85a653285 stop the receiver in a controlled way on EOF or error condition. 
+ add support for the following signal source configuration options: samples, repeat, seconds_to_skip, header_size
+ remove unused header files
 2021-02-19 13:03:22 +01:00
Carles Fernandez 73a728b3f6
Merge branch 'feature/signal_source_interface' of https://github.com/jwmelto/gnss-sdr into jwmelto-feature/signal_source_interface 2021-02-18 09:03:03 +01:00
Jim Melton 6e04a42c8a
clang-format 
This was much worse than I thought. I had run clang-format at some point, but
apparently I subsequently made some non-compliant changes in pretty much every
file I touched.
 2021-02-15 15:34:48 -07:00
Jim Melton 41c7a7ad7d
fix whitespace 2021-02-15 13:46:12 -07:00
Jim Melton 78362e7cba add signal_source_interface 
also adds a base implementation that most signal sources should inherit from.
The gen_signal_source is inexplicably different (probably as a test fixture,
commonality was not valued).

Only the file_signal_source has been tested; all the sources are modified in the same
way, but we all know the only proof of correctness is testing.

The block factory was simplified a bit. Handling for legacy config files was pulled out
of the flowgraph; now when the "0" instance of a component (Foo0) is created, if there is
no config for it, then the legacy version (Foo) will be tried. This is different from
passing -1 for the item number (which is still supported). Theoretically, all existing
config files should still work.
 2021-02-15 11:47:13 -07:00
Jim Melton 8407acb7a7 WIP: initial commit for collaboration 2021-02-15 11:47:13 -07:00
Marc Majoral c0e4b2aee5 dump the buffer monitor results to a file 2021-02-15 11:53:16 +01:00
Marc Majoral 03e8f97d2e real-time FPGA receiver buffer monitoring 2021-02-13 17:10:43 +01:00
Carles Fernandez 7308745f05
Apply more concise file header format 
Re-license CMake scripts with BSD-3-Clause
 2020-12-30 13:35:06 +01:00
Carles Fernandez 9523ebdffd
Add override keyword 2020-11-29 10:15:28 +01:00
Marc Majoral 3047051835 The dynamic bit selector modules determine the uio device file that is assigned to them using the hardware accelerator device name in the FPGA. The Switch device name is not configurable. 2020-11-27 11:24:44 +01:00
Marc Majoral a53109c718 The sample counter, the Acquisition and the Switch determine the uio device file that is assigned to them using the hardware accelerator device name in the FPGA 2020-11-26 17:07:15 +01:00
Carles Fernandez 287284261c
Make use of Doxygen grouping feature 
Improve Modules page in generated HTML documentation
 2020-11-01 13:37:19 +01:00
Marc Majoral 933873c265 When using the FPGA in post-processing mode, start the DMA after instantiating the complete flowgraph, not before. 2020-09-10 10:08:25 +02:00
Carles Fernandez a9472dea30
Remove redundant void (clang-tidy modernize-redundant-void-arg) 2020-08-27 12:48:20 +02:00
Carles Fernandez 499de7a9f1
Update file headers 2020-07-28 16:57:15 +02:00
Marc Majoral 98f1287f0e dynamic bit selection based on the estimated power of the received signal. 2020-07-16 15:42:55 +02:00
Marc Majoral 975f22f53d fixed program termination when using the FPGA in post-processing mode: the DMA process was not properly checking enable_DMA. 2020-07-01 17:42:40 +02:00
Carles Fernandez 2b3d4b321d
Make the adapters take the configuration pointer as const 2020-06-29 09:07:41 +02:00
Carles Fernandez 5a3db5a53d
Add debug internal logging for destructors. Sort destructor order 2020-06-25 02:50:07 +02:00
Carles Fernandez df7c466de0
Sort data members in headers 2020-06-24 22:27:51 +02:00
Carles Fernandez 81af1a531b
Redesign of pointer management 
Avoid indirection caused by passing shared_ptr by reference

The block factory does not have responsability on the lifetime of their inputs

Define std::make_unique when using C++11 and make use of it

Printers are turned into unique_ptr to express ownership

Printers do not participate on the lifelime of the data, so they take const raw pointers

Modernize tests code
 2020-06-18 11:49:28 +02:00
Carles Fernandez 865a54ddff
Apply clang-format 2020-04-03 00:17:22 +02:00
Carles Fernandez 5f974a8f17
Replace boost::shared_ptr by std::shared_ptr 2020-04-02 13:23:20 +02:00
Carles Fernandez 955348b080
Remove trailing underscore in header guards 2020-02-08 10:10:46 +01:00
Carles Fernandez 4d0d263280
Make the software package compliant with the REUSE Specification v3.0 (see https://reuse.software/spec/) 
Update license headers to SPDX format (see https://spdx.org/)
Add license to all files
Add CI job in GitHub Actions to ensure compliance
 2020-02-08 01:20:02 +01:00
Carles Fernandez a9b0ff184d
Add energy-saving options for AD9361 
New flag rf_shutdown, true by default, allows setting the RX and TX streams ON when set to false.
New parameters rx1_enable and rx2_enable, true by default, allow to disable the secondary RX channel when not used
 2019-10-13 23:38:06 +02:00
Carles Fernandez e4a39188f5
Implement FIR filter configuration 2019-10-09 20:50:06 +02:00
Carles Fernandez daa30c992c Remove unused parameters 2019-10-08 14:47:28 +02:00
Carles Fernandez bdabbf7f85 Implement phase_dds_deg parameter, fix guard for tx_bandwidth 2019-10-08 12:57:37 +02:00
Carles Fernandez 48a62594eb
Add work on RF configuration parameters for AD9361 2019-10-07 22:45:09 +02:00
Marc Majoral d20284fbc0 removed unused parameters 2019-10-02 15:25:46 +02:00
Marc Majoral b932c5ef98 added the enable_DMA_ flag, which is used to stop the DMA when the user quits gnss-sdr, and the receiver is using the FPGA and the receiver is working in post-processing mode. 2019-10-01 22:26:30 +02:00
Carles Fernandez 453c0cd249
Inject file(s) via DMA if switch_position=0 in Ad9361_Fpga_Signal_Source 2019-09-28 21:59:05 +02:00
Carles Fernandez 4dc30da649 Remove unused variables 2019-09-23 14:34:44 +02:00
Carles Fernandez 24872c02dc
Uniformize header guards 2019-09-07 16:42:22 +02:00
Carles Fernandez c31d9dea40
Fix errors risen by include_what_you_use 2019-08-17 13:56:54 +02:00
Carles Fernandez a4d6800e22
Update copyright year 
Applied on files changed since last release
clang-format applied
 2019-07-26 12:38:20 +02:00
Javier Arribas 1313edd716 Partial implementation of the new event queue and its dependencies. Still NOT usable 2019-07-16 17:41:12 +02:00
Carles Fernandez 07259159af Apply clang-tidy checks 2019-02-22 21:34:15 +00:00