osmarks/documentation
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Create ‘emerald_rapids’

Browse Source
This commit is contained in:
osmarks
2025-12-25 11:39:54 +00:00
committed by wikimind
parent 411a1aae98
commit 55cd4e3b80
1 changed files with 5 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
emerald_rapids.myco Normal file
View File

@@ -0,0 +1,5 @@
Emerald Rapids is [[Intel]]'s fifth generation of "Xeon Scalable" server [[central processing unit|CPU]]s, succeeding [[Sapphire Rapids]]. Emerald Rapids uses the same core design as Sapphire Rapids, but a redesigned chiplet layout (two die instead of four) and much more [[L3 cache]].
Emerald Rapids uses the [[Eagle Stream]] platform, with 8-channel [[DDR5]] up to 5600MT/s (varies by SKU) and 80 PCIe 5.0 lanes.
=> https://newsletter.semianalysis.com/p/intel-emerald-rapids-backtracks-on