Marc Majoral
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4ce4682ea8
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use separate files for the Xilinx DMA-proxy and the ezdma drivers
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2022-12-05 19:18:31 +01:00 |
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Jim Melton
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36a1e4c18d
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convert from vector to stream
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2022-09-20 15:39:14 -06:00 |
|
Into Pääkkönen
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e161545155
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add options for changing usrp device arguments
Signed-off-by: Into Pääkkönen <into.paakkonen@aalto.fi>
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2022-08-26 23:15:29 +03:00 |
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Carles Fernandez
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56ae0c043c
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CMake: Improve spdlog handling
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2022-08-23 13:02:04 +02:00 |
|
Carles Fernandez
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cd3be22798
|
Fix error with C++14 (invalid conversion from const char* to char*)
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2022-08-12 20:09:11 +02:00 |
|
Jim Melton
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09d8e3b9e9
|
clang-tidy claims this is more correct
|
2022-08-10 22:41:38 -06:00 |
|
Jim Melton
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4e9faa5793
|
cpplint
|
2022-08-10 21:26:10 -06:00 |
|
Jim Melton
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2eae3ef43a
|
implement dump
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2022-08-10 20:21:12 -06:00 |
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Jim Melton
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b24141ca72
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add ZMQ signal source
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2022-08-10 17:37:57 -06:00 |
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Carles Fernandez
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6ec452a7c0
|
Allow the CMake project to be a sub-project
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2022-07-28 10:37:36 +02:00 |
|
Vladisslav P
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3491fed625
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osmosdr signal source: implement bandwidth selection
New config file parameter:
SignalSource.if_bw=<bandwidth in Hz>
Signed-off-by: Vladisslav P <vladisslav2011@gmail.com>
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2022-07-06 08:25:50 +03:00 |
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Carles Fernandez
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342d378fe3
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Remove using directive
|
2022-06-29 00:07:51 +02:00 |
|
Carles Fernandez
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7c854cdfe7
|
Remove unused declaration
|
2022-06-28 17:34:22 +02:00 |
|
Carles Fernandez
|
8b84158b18
|
Fix memory access
|
2022-06-15 07:02:52 +02:00 |
|
Carles Fernandez
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7612a5e411
|
Fix building in 32-bit archs
|
2022-06-03 09:40:58 +02:00 |
|
Carles Fernandez
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037ad07478
|
Apply clang-tidy
|
2022-05-31 07:34:12 +02:00 |
|
Marc Majoral
|
4c278cb3df
|
removed commented code
|
2022-05-30 11:12:38 +02:00 |
|
Marc Majoral
|
6e368622e2
|
Prefer initialization to assignment in constructors
|
2022-05-30 09:02:22 +02:00 |
|
Marc Majoral
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a1a4666399
|
Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga_ad-fmcomms5_compatibility
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2022-05-23 17:52:34 +02:00 |
|
Marc Majoral
|
8131bdffc5
|
perform fmComms5 specific mult-chip sync configuration
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2022-05-20 16:54:00 +02:00 |
|
Marc Majoral
|
da47cadcff
|
fix ad9361_manager comments
|
2022-05-19 15:49:50 +02:00 |
|
Marc Majoral
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923398fa5e
|
fixed disable_ad9361_rx_local
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2022-05-19 15:33:56 +02:00 |
|
Carles Fernandez
|
592ba0325d
|
Fix clang-format job
|
2022-05-19 15:10:34 +02:00 |
|
Jean-Michel Friedt
|
c7f3994683
|
add XTRX gain setting and reading (osmocom source)
|
2022-05-19 15:00:29 +02:00 |
|
Marc Majoral
|
ab310a367a
|
fix gain_rx2
|
2022-05-18 18:04:43 +02:00 |
|
Marc Majoral
|
6b9941dd13
|
fix the configuration of the second AD9361 when it is present
|
2022-05-17 19:29:02 +02:00 |
|
Marc Majoral
|
4e37fa45ad
|
fix AD9361 configuration
|
2022-05-17 15:40:43 +02:00 |
|
Javier Arribas
|
9ef62fadb8
|
Adding Over-the-Wire sample format config option for the UHD source
|
2022-05-17 14:53:25 +02:00 |
|
Marc Majoral
|
38ed8ced4e
|
configure the AD9361 digital filter on a per RX-channel basis. Keep the LO is the same for all RX channels in the same device.
|
2022-05-17 10:49:13 +02:00 |
|
Marc Majoral
|
a1d8d8c19d
|
make the ad9361_manager functions flexible to allow the use of two AD9361 devices when using the FPGA.
|
2022-05-13 18:12:25 +02:00 |
|
Marc Majoral
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c2141f99fb
|
update the AD9361 in_voltage1_hardwaregain only if the gain mode is set to manual
|
2022-05-12 17:53:27 +02:00 |
|
Marc Majoral
|
e6f3222e4a
|
make the FPGA ad9361 signal source config_ad9361_rx_local function compatible with the AD-FMCOMMS5 analog front-end
|
2022-05-10 09:53:27 +02:00 |
|
Marc Majoral
|
c3ec1074db
|
make cmakelint happy
|
2022-04-29 12:45:35 +02:00 |
|
Marc Majoral
|
916b12eef6
|
fix code for 32-bit processor architecture
|
2022-04-29 12:16:48 +02:00 |
|
Marc Majoral
|
d346e763f8
|
use std::array
|
2022-04-29 10:41:44 +02:00 |
|
Marc Majoral
|
ea172f0d36
|
move all DMA control to Fpga_DMA class
|
2022-04-28 22:33:29 +02:00 |
|
Marc Majoral
|
e740244a63
|
removed the code that was commented out and the file headers that were not used
|
2022-04-28 21:24:15 +02:00 |
|
Marc Majoral
|
4244944814
|
fix filename0 and filename1 assignment
|
2022-04-28 19:09:26 +02:00 |
|
Marc Majoral
|
3f8e22b255
|
added support for the Xilinx dma-proxy driver when using 64-bit processor architectures.
|
2022-04-28 18:41:31 +02:00 |
|
Marc Majoral
|
d3bd4ed626
|
Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fix_FPGA_IP_address_ranges
|
2022-04-19 15:55:30 +02:00 |
|
Marc Majoral
|
337c9c7d1f
|
set the FPGA page size to 0x1000 for compatibility with the FPGA IP cores compiled for the ZynqMP
|
2022-04-19 15:53:00 +02:00 |
|
Carles Fernandez
|
70b79323ce
|
Fix building against latest GNU Radio main branch
|
2022-03-30 16:12:21 +02:00 |
|
Carles Fernandez
|
0f65cbeb91
|
Fix defects detected by Coverity Scan 2021.12.1: Declaring variable data without initializer
|
2022-02-17 17:28:34 +01:00 |
|
Stefan van der Linden
|
20218290f7
|
Removed unused include
|
2022-02-08 16:26:37 +01:00 |
|
Stefan van der Linden
|
77c682e8b3
|
Removed unnecessary buffer
|
2022-02-08 12:51:51 +01:00 |
|
Stefan van der Linden
|
e2551648b9
|
Added FIFO ibyte support and code cleanups
Additional intermediate buffering improves performance
|
2022-02-03 17:03:50 +01:00 |
|
Carles Fernandez
|
05a7d2413d
|
Prefer initialization to assignment in constructors in some signal sources
|
2021-12-28 19:14:18 +01:00 |
|
Carles Fernandez
|
26964a365a
|
Fix program termination when usign extended intergration times
Reorder private data members, initialize them in constructor list
|
2021-12-28 13:59:57 +01:00 |
|
Carles Fernandez
|
bfb9bc88b9
|
CI: make clang-tidy happy
|
2021-12-17 19:24:05 +01:00 |
|
Carles Fernandez
|
aae48af5d4
|
Warn about missing SignalSource.sampling_frequency parameter
|
2021-12-17 14:05:36 +01:00 |
|