Carles Fernandez
ecdd5f4e57
Add more extensive use of cstdint typenames
2018-08-12 00:04:09 +02:00
Carles Fernandez
273ce31029
Add more extensive use of cstdint typenames
2018-08-11 23:03:41 +02:00
Carles Fernandez
0126c26cd2
Fix typo
2018-08-11 20:51:59 +02:00
Carles Fernandez
49c480018c
Fix warning
2018-08-11 20:50:06 +02:00
Carles Fernandez
b2db6abdaa
Add more extensive use of cstdint typenames
2018-08-11 14:31:35 +02:00
Carles Fernandez
201c5ccd79
Add more extensive use of cstdint typenames
2018-08-11 13:56:24 +02:00
Carles Fernandez
d41ed73a00
Add more extensive use of cstdint typenames
2018-08-11 13:12:33 +02:00
Carles Fernandez
05a1806c8f
Merge branch 'fpga' of https://github.com/mmajoral/gnss-sdr into merge-marc
2018-08-11 12:56:52 +02:00
Carles Fernandez
f6af31b81f
Add more extensive use of cstdint typenames
2018-08-11 11:44:23 +02:00
Carles Fernandez
4404516289
Add more extensive use of cstdint typenames
2018-08-11 11:42:07 +02:00
Carles Fernandez
7c763abbbc
Add more extensive use of cstdint typenames
2018-08-11 10:34:25 +02:00
Carles Fernandez
35daf5a5e5
Fixes for 32-bit archs
2018-08-11 09:52:26 +02:00
Carles Fernandez
2b65c1b550
Replace unsigned long int by uint64_t and long int by int64_t in tests
2018-08-10 21:16:10 +02:00
Carles Fernandez
6b1611b3a9
Replace unsigned long int by uint64_t and long int by int64_t. Fixes #199
2018-08-10 20:34:03 +02:00
Marc Majoral
f14ad930d5
declared the 64-bit variables as long long ints instead of long ints in the FPGA related files.
...
Variables declared as long ints are interpreted as 32-bit variables in the ARM architecture and 64-bit variables in the X86-64 architecture.
2018-08-10 16:42:53 +02:00
Marc Majoral
b1524a3afe
implemented 64-bit global sample counter
...
started programming the FPGA tracking unit tests
2018-08-10 13:12:06 +02:00
Javier Arribas
2517e7bb31
Replacing software sample counter with hardware sample counter if FPGA is enabled. Fix a compilation bug when ENABLE_FPGA is selected
2018-08-10 11:53:40 +02:00
Marc Majoral
3b154c57c2
fixed some cmakefiles to allow for the correct compilation of the gnss-sdr with the FPGA option and the unit test extra options at the same time.
2018-08-10 10:04:47 +02:00
Carles Fernandez
66bfbffe89
Add AVX implementation
2018-08-09 22:00:22 +02:00
Carles Fernandez
c5f10cd56c
Add sse4_1 implementation
2018-08-09 21:08:58 +02:00
Carles Fernandez
4f588058d0
Initialize all variables
2018-08-09 20:14:42 +02:00
Carles Fernandez
25ebeb746a
Read number of executed dwells
2018-08-09 12:56:27 +02:00
Carles Fernandez
2cc2e93d10
Fix make_two_steps option
2018-08-09 12:47:20 +02:00
Marc Majoral
557d25d3ea
Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga
2018-08-08 18:23:38 +02:00
Carles Fernandez
18173bcbff
Fix warning
2018-08-08 18:20:30 +02:00
Carles Fernandez
727cc115c4
Fix kernel
2018-08-08 18:20:09 +02:00
Carles Fernandez
69803b55da
Remove stream_to_vector in generic acquisition block
2018-08-08 15:02:29 +02:00
Marc Majoral
ee132f445f
Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga
2018-08-08 14:25:12 +02:00
Carles Fernandez
0b5c827eda
Add Doppler rate in fast_resampler kernel. Still not used
2018-08-08 12:03:58 +02:00
Carles Fernandez
33215c89ac
Fix building
2018-08-08 09:52:06 +02:00
Carles Fernandez
46ed90eb50
Fix building of unit testing extra tests
2018-08-08 09:35:19 +02:00
Carles Fernandez
4854cafe5d
Fix building and warnings
2018-08-08 09:34:15 +02:00
Javier Arribas
37834c2029
GPS acquisition adapter fix to be coherent with the stream to vector size of acquisition engine
2018-08-07 20:17:54 +02:00
Javier Arribas
27f8b1fe61
Improving tracking pull-in test and hybrid observables test. Now observables test uses double differences
2018-08-07 20:16:43 +02:00
Javier Arribas
91203d2393
Observable generation performance improvement and RX time synchronization to multiple of 20 ms
2018-08-07 20:06:47 +02:00
Javier Arribas
19c5220886
Prepare the tracking configuration to allow a specific pull-in loops bandwidth
2018-08-07 20:05:35 +02:00
Javier Arribas
b47d7826eb
Adding an option to SDR sample counter to modulate the observable generation rate. It defaults to 20 ms interval (50 Hz)
2018-08-07 20:04:44 +02:00
Javier Arribas
00f03a679a
Add missing break
2018-08-07 19:59:44 +02:00
Javier Arribas
5c24826d70
Telemetry decoders improvements
2018-08-07 19:57:50 +02:00
Marc Majoral
b1a7031e52
solved some bugs in GPS L5
...
removed check for sign in multicorrelator results: this is not necessary anymore
did some other minor maintenances
2018-08-07 18:56:54 +02:00
Javier Arribas
856eaf1881
Unified tracking algorithm improvement
2018-08-03 12:05:40 +02:00
Javier Arribas
83021ccfff
Use by default the new fast local code resampler
2018-08-03 11:40:11 +02:00
Javier Arribas
47e1ba1923
Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into next
2018-08-03 11:02:28 +02:00
Javier Arribas
a23231479f
Adding new gnss-sdr volk kernel for a faster local signal replica generation
2018-08-03 11:02:01 +02:00
Álvaro Cebrián Juan
4eb68fd99b
Fix CTTC coordinates
2018-08-02 19:30:45 +02:00
Marc Majoral
daedfc3e01
adapted the FPGA tracking class according to the latest changes in the next branch
2018-08-02 17:32:59 +02:00
Javier Arribas
f9573987a2
Improving freq xlating fir filter adapter configuration
2018-08-02 12:46:08 +02:00
Marc Majoral
7e246dea29
Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga
2018-08-01 18:59:40 +02:00
Marc Majoral
bb33faea21
improved existing code
...
started the GPS L2 FPGA class implementation (not finished yet)
implemented the GPS L5 FPGA class (not tested yet)
implemented the Galileo E5 FPGA class (not tested yet)
The code is still "dirty": it is yet to be cleaned of debug comments/code and any possible redundant code and not used variables.
2018-08-01 15:55:40 +02:00
Javier Arribas
06015f82b3
Considering GPS and Galileo PRN ranges in tracking pull-in test
2018-08-01 15:51:46 +02:00
