mirror of
https://github.com/gnss-sdr/gnss-sdr
synced 2024-12-15 12:40:35 +00:00
207 lines
8.5 KiB
C
207 lines
8.5 KiB
C
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/*
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* Machine generated by "edit-gpif". Do not edit by hand.
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*/
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// This program configures the General Programmable Interface (GPIF) for FX2.
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// Please do not modify sections of text which are marked as "DO NOT EDIT ...".
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//
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// DO NOT EDIT ...
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// GPIF Initialization
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// Interface Timing Async
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// Internal Ready Init IntRdy=1
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// CTL Out Tristate-able Binary
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// SingleWrite WF Select 1
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// SingleRead WF Select 0
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// FifoWrite WF Select 3
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// FifoRead WF Select 2
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// Data Bus Idle Drive Tristate
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// END DO NOT EDIT
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// DO NOT EDIT ...
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// GPIF Wave Names
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// Wave 0 = Single R
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// Wave 1 = Single W
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// Wave 2 = FIFO Rea
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// Wave 3 = FIFO Wri
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// GPIF Ctrl Outputs Level
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// CTL 0 = BOGUS CMOS
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// CTL 1 = CTL1 CMOS
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// CTL 2 = CTL2 CMOS
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// CTL 3 = CTL3 CMOS
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// CTL 4 = CTL4 CMOS
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// CTL 5 = CTL5 CMOS
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// GPIF Rdy Inputs
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// RDY0 = ADC_CLK
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// RDY1 = RDY1
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// RDY2 = RDY2
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// RDY3 = RDY3
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// RDY4 = RDY4
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// RDY5 = TCXpire
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// FIFOFlag = FIFOFlag
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// IntReady = IntReady
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// END DO NOT EDIT
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// DO NOT EDIT ...
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//
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// GPIF Waveform 0: Single R
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//
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// Interval 0 1 2 3 4 5 6 Idle (7)
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// _________ _________ _________ _________ _________ _________ _________ _________
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//
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// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
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// DataMode NO Data NO Data NO Data NO Data NO Data NO Data NO Data
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// NextData SameData SameData SameData SameData SameData SameData SameData
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// Int Trig No Int No Int No Int No Int No Int No Int No Int
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// IF/Wait Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
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// Term A
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// LFunc
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// Term B
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// Branch1
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// Branch0
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// Re-Exec
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// Sngl/CRC Default Default Default Default Default Default Default
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// BOGUS 0 0 0 0 0 0 0 0
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// CTL1 0 0 0 0 0 0 0 0
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// CTL2 0 0 0 0 0 0 0 0
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// CTL3 0 0 0 0 0 0 0 0
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// CTL4 0 0 0 0 0 0 0 0
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// CTL5 0 0 0 0 0 0 0 0
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//
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// END DO NOT EDIT
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// DO NOT EDIT ...
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//
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// GPIF Waveform 1: Single W
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//
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// Interval 0 1 2 3 4 5 6 Idle (7)
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// _________ _________ _________ _________ _________ _________ _________ _________
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//
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// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
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// DataMode NO Data NO Data NO Data NO Data NO Data NO Data NO Data
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// NextData SameData SameData SameData SameData SameData SameData SameData
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// Int Trig No Int No Int No Int No Int No Int No Int No Int
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// IF/Wait Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
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// Term A
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// LFunc
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// Term B
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// Branch1
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// Branch0
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// Re-Exec
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// Sngl/CRC Default Default Default Default Default Default Default
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// BOGUS 0 0 0 0 0 0 0 0
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// CTL1 0 0 0 0 0 0 0 0
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// CTL2 0 0 0 0 0 0 0 0
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// CTL3 0 0 0 0 0 0 0 0
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// CTL4 0 0 0 0 0 0 0 0
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// CTL5 0 0 0 0 0 0 0 0
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//
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// END DO NOT EDIT
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// DO NOT EDIT ...
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//
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// GPIF Waveform 2: FIFO Rea
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//
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// Interval 0 1 2 3 4 5 6 Idle (7)
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// _________ _________ _________ _________ _________ _________ _________ _________
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//
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// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
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// DataMode Activate Activate Activate Activate Activate Activate Activate
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// NextData SameData SameData SameData SameData SameData SameData SameData
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// Int Trig No Int No Int No Int No Int No Int No Int No Int
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// IF/Wait IF Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
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// Term A FIFOFlag
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// LFunc AND
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// Term B FIFOFlag
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// Branch1 ThenIdle
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// Branch0 Else 0
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// Re-Exec No
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// Sngl/CRC Default Default Default Default Default Default Default
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// BOGUS 0 0 0 0 0 0 0 0
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// CTL1 0 0 0 0 0 0 0 0
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// CTL2 0 0 0 0 0 0 0 0
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// CTL3 0 0 0 0 0 0 0 0
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// CTL4 0 0 0 0 0 0 0 0
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// CTL5 0 0 0 0 0 0 0 0
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//
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// END DO NOT EDIT
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// DO NOT EDIT ...
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//
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// GPIF Waveform 3: FIFO Wri
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//
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// Interval 0 1 2 3 4 5 6 Idle (7)
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// _________ _________ _________ _________ _________ _________ _________ _________
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//
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// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
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// DataMode Activate Activate Activate Activate Activate Activate Activate
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// NextData SameData SameData SameData SameData SameData SameData SameData
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// Int Trig No Int No Int No Int No Int No Int No Int No Int
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// IF/Wait IF Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
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// Term A FIFOFlag
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// LFunc AND
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// Term B FIFOFlag
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// Branch1 ThenIdle
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// Branch0 Else 0
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// Re-Exec No
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// Sngl/CRC Default Default Default Default Default Default Default
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// BOGUS 0 0 0 0 0 0 0 0
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// CTL1 0 0 0 0 0 0 0 0
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// CTL2 0 0 0 0 0 0 0 0
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// CTL3 0 0 0 0 0 0 0 0
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// CTL4 0 0 0 0 0 0 0 0
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// CTL5 0 0 0 0 0 0 0 0
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//
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// END DO NOT EDIT
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// GPIF Program Code
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// DO NOT EDIT ...
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// #include "fx2.h"
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// #include "fx2regs.h"
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// #include "fx2sdly.h" // SYNCDELAY macro
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// END DO NOT EDIT
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// DO NOT EDIT ...
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const char WaveData[128] =
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{
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// Wave 0
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/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
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/* Opcode*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* Output*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
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// Wave 1
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/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
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/* Opcode*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* Output*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
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// Wave 2
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/* LenBr */ 0x38, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
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/* Opcode*/ 0x03, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00,
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/* Output*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* LFun */ 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
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// Wave 3
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/* LenBr */ 0x38, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
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/* Opcode*/ 0x03, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00,
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/* Output*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* LFun */ 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
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};
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// END DO NOT EDIT
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// DO NOT EDIT ...
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const char FlowStates[36] =
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{
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/* Wave 0 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* Wave 1 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* Wave 2 FlowStates */ 0x80,0xED,0x00,0x00,0x00,0x00,0x03,0x02,0x00,
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/* Wave 3 FlowStates */ 0x80,0xEE,0x00,0x00,0x00,0x00,0x03,0x02,0x00,
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};
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// END DO NOT EDIT
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// DO NOT EDIT ...
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const char InitData[7] =
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{
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/* Regs */ 0xA0,0x00,0x00,0x00,0xAE,0x4E,0x00
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};
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// END DO NOT EDIT
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// TO DO: You may add additional code below.
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