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Commit Graph

6 Commits

Author SHA1 Message Date
Calvin Rose
25b7c74089 More work on register allocation and spilling.
Setup frontend.janet to show the basics of what is going on. Currently
emitting "fake" instructions just to hash out the idea.

One apparent issue is how we handle register spilling during variable
argument IR instructions (function calls). Arguments should come
_before_ the function call not after.
2024-06-05 17:50:11 -05:00
Calvin Rose
7ea118f248 Begin work on simple x64 backend.
Introduce register allocation, spilling, etc. First implementation
will likely emit textual assembly and use a very bad register allocation
algorithm.
2024-06-03 08:35:08 -05:00
Calvin Rose
480c5b5e9d Change how labels are recorded.
Disallow jumping to arbitrary instructions - instead, only allow jumps
to label ids. This will make various transformations and validations
easier since adding or remove instructions does not break jumps.
2024-06-02 09:43:33 -05:00
Calvin Rose
08e6051af8 More work on sysir compiler - basic function calls (without prototypes). 2024-05-15 07:24:15 -05:00
Calvin Rose
745567a2e0 More work on frontend. 2024-05-09 22:22:38 -05:00
Calvin Rose
ef2dfcd7c3 More work on a proof of concept frontend.
Basic frontend being prototyped in examples/sysir/frontend.janet. Still
a lot of work needs to be done here, and some of this code will
eventually move to C most likely, but this is a good way to better
exercise our backend.

Type inference - at the very least _forward_ inference, is the most
needed change here. While one could do this in the compiler
frontend, doing so in sysir/asm is not so much of an issue. "Inference"
here means inserting "bind" instructions when there is only a single
type that will work correctly.
2024-05-05 14:45:00 -05:00