mirrors/gnss-sdr
1
0
Fork 0
mirror of https://github.com/gnss-sdr/gnss-sdr synced 2024-11-16 06:44:57 +00:00
Code Issues Releases Wiki Activity
9499fe434b
gnss-sdr/firmware/GN3S_v2/lib/delay.sym
Javier Arribas b849b20a8c Added optional support for Sparkfun SiGe GN3S USB GPS RF sampler: 
- Added a pre-compiled custom GN3S firmware.
- Added a fully-compliant GNU Radio source block for GN3S USB dongle. It can be used also from GNU Radio companion and from Python applications.
- Added a new GN3S_Signal_Source block. It is possible to disable the GN3S signal source compilation. See README.

git-svn-id: https://svn.code.sf.net/p/gnss-sdr/code/trunk@217 64b25241-fba3-4117-9849-534c7e92360d
2012-07-30 15:46:07 +00:00

381 lines
28 KiB
Plaintext
Raw Blame History

This file contains invisible Unicode characters

This file contains invisible Unicode characters that are indistinguishable to humans but may be processed differently by a computer. If you think that this is intentional, you can safely ignore this warning. Use the Escape button to reveal them.

ASxxxx Assembler V01.70 + NoICE + SDCC mods + Flat24 Feb-1999 (Intel 8051), page 1.
Symbol Table
A 00D6
AC 00D6
ACC 00E0
ACC.0 00E0
ACC.1 00E1
ACC.2 00E2
ACC.3 00E3
ACC.4 00E4
ACC.5 00E5
ACC.6 00E6
ACC.7 00E7
B 00F0
B.0 00F0
B.1 00F1
B.2 00F2
B.3 00F3
B.4 00F4
B.5 00F5
B.6 00F6
B.7 00F7
CPRL2 00C8
CT2 00C9
CY 00D7
DPH 0083
DPL 0082
EA 00AF
ES 00AC
ET0 00A9
ET1 00AB
ET2 00AD
EX0 00A8
EX1 00AA
EXEN2 00CB
EXF2 00CE
F0 00D5
IE 00A8
IE.0 00A8
IE.1 00A9
IE.2 00AA
IE.3 00AB
IE.4 00AC
IE.5 00AD
IE.7 00AF
IE0 0089
IE1 008B
INT0 00B2
INT1 00B3
IP 00B8
IP.0 00B8
IP.1 00B9
IP.2 00BA
IP.3 00BB
IP.4 00BC
IP.5 00BD
IT0 0088
IT1 008A
OV 00D2
P 00D0
P0 0080
P0.0 0080
P0.1 0081
P0.2 0082
P0.3 0083
P0.4 0084
P0.5 0085
P0.6 0086
P0.7 0087
P1 0090
P1.0 0090
P1.1 0091
P1.2 0092
P1.3 0093
P1.4 0094
P1.5 0095
P1.6 0096
P1.7 0097
P2 00A0
P2.0 00A0
P2.1 00A1
P2.2 00A2
P2.3 00A3
P2.4 00A4
P2.5 00A5
P2.6 00A6
P2.7 00A7
P3 00B0
P3.0 00B0
P3.1 00B1
P3.2 00B2
P3.3 00B3
P3.4 00B4
P3.5 00B5
P3.6 00B6
P3.7 00B7
PCON 0087
PS 00BC
PSW 00D0
PSW.0 00D0
PSW.1 00D1
PSW.2 00D2
PSW.3 00D3
PSW.4 00D4
PSW.5 00D5
PSW.6 00D6
PSW.7 00D7
PT0 00B9
PT1 00BB
PT2 00BD
PX0 00B8
PX1 00BA
RB8 009A
RCAP2H 00CB
RCAP2L 00CA
RCLK 00CD
REN 009C
RI 0098
RS0 00D3
RS1 00D4
RXD 00B0
SBUF 0099
SCON 0098
SCON.0 0098
SCON.1 0099
SCON.2 009A
SCON.3 009B
SCON.4 009C
SCON.5 009D
SCON.6 009E
SCON.7 009F
SM0 009F
SM1 009E
SM2 009D
SP 0081
T2CON 00C8
T2CON.0 00C8
T2CON.1 00C9
T2CON.2 00CA
T2CON.3 00CB
T2CON.4 00CC
T2CON.5 00CD
T2CON.6 00CE
T2CON.7 00CF
TB8 009B
TCLK 00CC
TCON 0088
TCON.0 0088
TCON.1 0089
TCON.2 008A
TCON.3 008B
TCON.4 008C
TCON.5 008D
TCON.6 008E
TCON.7 008F
TF0 008D
TF1 008F
TF2 00CF
TH0 008C
TH1 008D
TH2 00CD
TI 0099
TL0 008A
TL1 008B
TL2 00CC
TMOD 0089
TR0 008C
TR1 008E
TR2 00CA
TXD 00B1
14 _mdelay 0014 GR
14 _mdelay1 0009 R
14 _udelay 0001 GR
14 _udelay1 0000 R
a 00D6
ac 00D6
acc 00E0
acc.0 00E0
acc.1 00E1
acc.2 00E2
acc.3 00E3
acc.4 00E4
acc.5 00E5
acc.6 00E6
acc.7 00E7
ar0 = 0000
ar1 = 0001
ar2 = 0002
ar3 = 0003
ar4 = 0004
ar5 = 0005
ar6 = 0006
ar7 = 0007
b 00F0
b.0 00F0
b.1 00F1
b.2 00F2
b.3 00F3
b.4 00F4
b.5 00F5
b.6 00F6
b.7 00F7
cprl2 00C8
ct2 00C9
cy 00D7
dph 0083
dpl 0082
ea 00AF
es 00AC
et0 00A9
et1 00AB
et2 00AD
ex0 00A8
ex1 00AA
exen2 00CB
exf2 00CE
f0 00D5
ie 00A8
ie.0 00A8
ie.1 00A9
ie.2 00AA
ie.3 00AB
ie.4 00AC
ie.5 00AD
ie.7 00AF
ie0 0089
ie1 008B
int0 00B2
int1 00B3
ip 00B8
ip.0 00B8
ip.1 00B9
ip.2 00BA
ip.3 00BB
ip.4 00BC
ip.5 00BD
it0 0088
it1 008A
ov 00D2
p 00D0
p0 0080
p0.0 0080
p0.1 0081
p0.2 0082
p0.3 0083
p0.4 0084
p0.5 0085
p0.6 0086
p0.7 0087
p1 0090
p1.0 0090
p1.1 0091
p1.2 0092
p1.3 0093
p1.4 0094
p1.5 0095
p1.6 0096
p1.7 0097
p2 00A0
p2.0 00A0
p2.1 00A1
p2.2 00A2
p2.3 00A3
p2.4 00A4
p2.5 00A5
p2.6 00A6
p2.7 00A7
p3 00B0
p3.0 00B0
p3.1 00B1
p3.2 00B2
p3.3 00B3
p3.4 00B4
p3.5 00B5
p3.6 00B6
p3.7 00B7
pcon 0087
ps 00BC
psw 00D0
psw.0 00D0
psw.1 00D1
psw.2 00D2
psw.3 00D3
psw.4 00D4
psw.5 00D5
psw.6 00D6
psw.7 00D7
pt0 00B9
pt1 00BB
pt2 00BD
px0 00B8
px1 00BA
rb8 009A
rcap2h 00CB
rcap2l 00CA
rclk 00CD
ren 009C
ri 0098
rs0 00D3
rs1 00D4
rxd 00B0
sbuf 0099
scon 0098
scon.0 0098
scon.1 0099
scon.2 009A
scon.3 009B
scon.4 009C
scon.5 009D
scon.6 009E
scon.7 009F
sm0 009F
sm1 009E
sm2 009D
sp 0081
t2con 00C8
t2con.0 00C8
t2con.1 00C9
t2con.2 00CA
t2con.3 00CB
t2con.4 00CC
t2con.5 00CD
t2con.6 00CE
t2con.7 00CF
tb8 009B
tclk 00CC
tcon 0088
tcon.0 0088
tcon.1 0089
tcon.2 008A
tcon.3 008B
tcon.4 008C
tcon.5 008D
tcon.6 008E
tcon.7 008F
tf0 008D
tf1 008F
tf2 00CF
th0 008C
th1 008D
th2 00CD
ti 0099
tl0 008A
tl1 008B
tl2 00CC
tmod 0089
tr0 008C
tr1 008E
tr2 00CA
txd 00B1
ASxxxx Assembler V01.70 + NoICE + SDCC mods + Flat24 Feb-1999 (Intel 8051), page 2.
Area Table
0 _CODE size 0 flags 0
1 RSEG size 0 flags 0
2 REG_BANK_0 size 8 flags 4
3 DSEG size 0 flags 0
4 OSEG size 0 flags 4
5 ISEG size 0 flags 0
6 IABS size 0 flags 8
7 BSEG size 0 flags 80
8 PSEG size 0 flags 50
9 XSEG size 0 flags 40
A XABS size 0 flags 48
B HOME size 0 flags 20
C GSINIT0 size 0 flags 20
D GSINIT1 size 0 flags 20
E GSINIT2 size 0 flags 20
F GSINIT3 size 0 flags 20
10 GSINIT4 size 0 flags 20
11 GSINIT5 size 0 flags 20
12 GSINIT size 0 flags 20
13 GSFINAL size 0 flags 20
14 CSEG size 25 flags 20
15 CONST size 0 flags 20
16 CABS size 0 flags 28
Reference in New Issue View Git Blame Copy Permalink