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https://github.com/gnss-sdr/gnss-sdr
synced 2024-06-25 22:43:14 +00:00
343 lines
16 KiB
C++
343 lines
16 KiB
C++
/*!
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* \file galileo_e1_dll_pll_veml_tracking_fpga.cc
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* \brief Adapts a DLL+PLL VEML (Very Early Minus Late) tracking loop block
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* to a TrackingInterface for Galileo E1 signals for the FPGA
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* \author Marc Majoral, 2019. mmajoral(at)cttc.cat
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*
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* Code DLL + carrier PLL according to the algorithms described in:
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* K.Borre, D.M.Akos, N.Bertelsen, P.Rinder, and S.H.Jensen,
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* A Software-Defined GPS and Galileo Receiver. A Single-Frequency
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* Approach, Birkhauser, 2007
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*
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* -------------------------------------------------------------------------
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*
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* Copyright (C) 2010-2019 (see AUTHORS file for a list of contributors)
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*
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* GNSS-SDR is a software defined Global Navigation
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* Satellite Systems receiver
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*
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* This file is part of GNSS-SDR.
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*
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* GNSS-SDR is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* GNSS-SDR is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GNSS-SDR. If not, see <https://www.gnu.org/licenses/>.
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*
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* -------------------------------------------------------------------------
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*/
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#include "galileo_e1_dll_pll_veml_tracking_fpga.h"
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#include "Galileo_E1.h"
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#include "configuration_interface.h"
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#include "display.h"
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#include "dll_pll_conf_fpga.h"
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#include "galileo_e1_signal_processing.h"
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#include "gnss_sdr_flags.h"
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#include <glog/logging.h>
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#include <volk_gnsssdr/volk_gnsssdr.h>
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#include <array>
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// the following flags are FPGA-specific and they are using arrange the values of the local code in the way the FPGA
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// expects. This arrangement is done in the initialisation to avoid consuming unnecessary clock cycles during tracking.
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#define LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY 0x0C000000 // flag that enables WE (Write Enable) of the local code FPGA
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#define LOCAL_CODE_FPGA_CORRELATOR_SELECT_COUNT 0x20000000 // flag that selects the writing of the pilot code in the FPGA (as opposed to the data code)
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GalileoE1DllPllVemlTrackingFpga::GalileoE1DllPllVemlTrackingFpga(
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ConfigurationInterface* configuration, const std::string& role,
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unsigned int in_streams, unsigned int out_streams) : role_(role), in_streams_(in_streams), out_streams_(out_streams)
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{
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Dll_Pll_Conf_Fpga trk_param_fpga = Dll_Pll_Conf_Fpga();
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DLOG(INFO) << "role " << role;
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//################# CONFIGURATION PARAMETERS ########################
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int32_t fs_in_deprecated = configuration->property("GNSS-SDR.internal_fs_hz", 2048000);
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int32_t fs_in = configuration->property("GNSS-SDR.internal_fs_sps", fs_in_deprecated);
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trk_param_fpga.fs_in = fs_in;
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bool dump = configuration->property(role + ".dump", false);
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trk_param_fpga.dump = dump;
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std::string default_dump_filename = "./track_ch";
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std::string dump_filename = configuration->property(role + ".dump_filename", default_dump_filename);
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trk_param_fpga.dump_filename = dump_filename;
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bool dump_mat = configuration->property(role + ".dump_mat", true);
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trk_param_fpga.dump_mat = dump_mat;
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trk_param_fpga.high_dyn = configuration->property(role + ".high_dyn", false);
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if (configuration->property(role + ".smoother_length", 10) < 1)
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{
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trk_param_fpga.smoother_length = 1;
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std::cout << TEXT_RED << "WARNING: Gal. E1. smoother_length must be bigger than 0. It has been set to 1" << TEXT_RESET << std::endl;
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}
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else
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{
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trk_param_fpga.smoother_length = configuration->property(role + ".smoother_length", 10);
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}
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float pll_bw_hz = configuration->property(role + ".pll_bw_hz", 5.0);
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if (FLAGS_pll_bw_hz != 0.0)
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{
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pll_bw_hz = static_cast<float>(FLAGS_pll_bw_hz);
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}
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trk_param_fpga.pll_bw_hz = pll_bw_hz;
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float dll_bw_hz = configuration->property(role + ".dll_bw_hz", 0.5);
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if (FLAGS_dll_bw_hz != 0.0)
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{
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dll_bw_hz = static_cast<float>(FLAGS_dll_bw_hz);
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}
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trk_param_fpga.dll_bw_hz = dll_bw_hz;
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float pll_bw_narrow_hz = configuration->property(role + ".pll_bw_narrow_hz", 2.0);
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trk_param_fpga.pll_bw_narrow_hz = pll_bw_narrow_hz;
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float dll_bw_narrow_hz = configuration->property(role + ".dll_bw_narrow_hz", 0.25);
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trk_param_fpga.dll_bw_narrow_hz = dll_bw_narrow_hz;
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int dll_filter_order = configuration->property(role + ".dll_filter_order", 2);
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if (dll_filter_order < 1)
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{
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LOG(WARNING) << "dll_filter_order parameter must be 1, 2 or 3. Set to 1.";
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dll_filter_order = 1;
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}
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if (dll_filter_order > 3)
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{
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LOG(WARNING) << "dll_filter_order parameter must be 1, 2 or 3. Set to 3.";
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dll_filter_order = 3;
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}
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trk_param_fpga.dll_filter_order = dll_filter_order;
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int pll_filter_order = configuration->property(role + ".pll_filter_order", 3);
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if (pll_filter_order < 2)
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{
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LOG(WARNING) << "pll_filter_order parameter must be 2 or 3. Set to 2.";
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pll_filter_order = 2;
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}
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if (pll_filter_order > 3)
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{
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LOG(WARNING) << "pll_filter_order parameter must be 2 or 3. Set to 3.";
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pll_filter_order = 3;
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}
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trk_param_fpga.pll_filter_order = pll_filter_order;
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if (pll_filter_order == 2)
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{
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trk_param_fpga.fll_filter_order = 1;
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}
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if (pll_filter_order == 3)
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{
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trk_param_fpga.fll_filter_order = 2;
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}
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bool enable_fll_pull_in = configuration->property(role + ".enable_fll_pull_in", false);
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trk_param_fpga.enable_fll_pull_in = enable_fll_pull_in;
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float fll_bw_hz = configuration->property(role + ".fll_bw_hz", 35.0);
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trk_param_fpga.fll_bw_hz = fll_bw_hz;
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float pull_in_time_s = configuration->property(role + ".pull_in_time_s", 2.0);
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trk_param_fpga.pull_in_time_s = pull_in_time_s;
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int32_t extend_correlation_symbols = configuration->property(role + ".extend_correlation_symbols", 1);
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float early_late_space_chips = configuration->property(role + ".early_late_space_chips", 0.15);
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trk_param_fpga.early_late_space_chips = early_late_space_chips;
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float very_early_late_space_chips = configuration->property(role + ".very_early_late_space_chips", 0.5);
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trk_param_fpga.very_early_late_space_chips = very_early_late_space_chips;
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float early_late_space_narrow_chips = configuration->property(role + ".early_late_space_narrow_chips", 0.15);
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trk_param_fpga.early_late_space_narrow_chips = early_late_space_narrow_chips;
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float very_early_late_space_narrow_chips = configuration->property(role + ".very_early_late_space_narrow_chips", 0.5);
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trk_param_fpga.very_early_late_space_narrow_chips = very_early_late_space_narrow_chips;
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bool track_pilot = configuration->property(role + ".track_pilot", false);
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if (extend_correlation_symbols < 1)
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{
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extend_correlation_symbols = 1;
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std::cout << TEXT_RED << "WARNING: Galileo E1. extend_correlation_symbols must be bigger than 0. Coherent integration has been set to 1 symbol (4 ms)" << TEXT_RESET << std::endl;
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}
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else if (!track_pilot and extend_correlation_symbols > 1)
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{
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extend_correlation_symbols = 1;
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std::cout << TEXT_RED << "WARNING: Galileo E1. Extended coherent integration is not allowed when tracking the data component. Coherent integration has been set to 4 ms (1 symbol)" << TEXT_RESET << std::endl;
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}
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if ((extend_correlation_symbols > 1) and (pll_bw_narrow_hz > pll_bw_hz or dll_bw_narrow_hz > dll_bw_hz))
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{
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std::cout << TEXT_RED << "WARNING: Galileo E1. PLL or DLL narrow tracking bandwidth is higher than wide tracking one" << TEXT_RESET << std::endl;
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}
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trk_param_fpga.track_pilot = track_pilot;
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d_track_pilot = track_pilot;
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trk_param_fpga.extend_correlation_symbols = extend_correlation_symbols;
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int32_t vector_length = std::round(fs_in / (GALILEO_E1_CODE_CHIP_RATE_HZ / GALILEO_E1_B_CODE_LENGTH_CHIPS));
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trk_param_fpga.vector_length = vector_length;
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trk_param_fpga.system = 'E';
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std::array<char, 3> sig_{'1', 'B', '\0'};
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std::memcpy(trk_param_fpga.signal, sig_.data(), 3);
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trk_param_fpga.cn0_samples = configuration->property(role + ".cn0_samples", trk_param_fpga.cn0_samples);
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trk_param_fpga.cn0_min = configuration->property(role + ".cn0_min", trk_param_fpga.cn0_min);
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trk_param_fpga.max_code_lock_fail = configuration->property(role + ".max_lock_fail", trk_param_fpga.max_code_lock_fail);
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trk_param_fpga.max_carrier_lock_fail = configuration->property(role + ".max_carrier_lock_fail", trk_param_fpga.max_carrier_lock_fail);
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trk_param_fpga.carrier_lock_th = configuration->property(role + ".carrier_lock_th", trk_param_fpga.carrier_lock_th);
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// int32_t max_lock_fail = configuration->property(role + ".max_lock_fail", 50);
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// if (FLAGS_max_lock_fail != 50)
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// {
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// max_lock_fail = FLAGS_max_lock_fail;
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// }
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// trk_param_fpga.max_lock_fail = max_lock_fail;
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// FPGA configuration parameters
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std::string default_device_name = "/dev/uio";
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std::string device_name = configuration->property(role + ".devicename", default_device_name);
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trk_param_fpga.device_name = device_name;
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uint32_t device_base = configuration->property(role + ".device_base", 15);
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trk_param_fpga.device_base = device_base;
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trk_param_fpga.multicorr_type = 1; // 0 -> 3 correlators, 1 -> 5 correlators
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//################# PRE-COMPUTE ALL THE CODES #################
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uint32_t code_samples_per_chip = 2;
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d_ca_codes = static_cast<int32_t*>(volk_gnsssdr_malloc(static_cast<int32_t>(GALILEO_E1_B_CODE_LENGTH_CHIPS) * code_samples_per_chip * GALILEO_E1_NUMBER_OF_CODES * sizeof(int32_t), volk_gnsssdr_get_alignment()));
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float* ca_codes_f;
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float* data_codes_f = nullptr;
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d_data_codes = nullptr;
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if (d_track_pilot)
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{
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d_data_codes = static_cast<int32_t*>(volk_gnsssdr_malloc((static_cast<uint32_t>(GALILEO_E1_B_CODE_LENGTH_CHIPS)) * code_samples_per_chip * GALILEO_E1_NUMBER_OF_CODES * sizeof(int32_t), volk_gnsssdr_get_alignment()));
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}
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ca_codes_f = static_cast<float*>(volk_gnsssdr_malloc(static_cast<int32_t>(GALILEO_E1_B_CODE_LENGTH_CHIPS) * code_samples_per_chip * sizeof(float), volk_gnsssdr_get_alignment()));
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if (d_track_pilot)
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{
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data_codes_f = static_cast<float*>(volk_gnsssdr_malloc((static_cast<uint32_t>(GALILEO_E1_B_CODE_LENGTH_CHIPS)) * code_samples_per_chip * sizeof(float), volk_gnsssdr_get_alignment()));
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}
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for (uint32_t PRN = 1; PRN <= GALILEO_E1_NUMBER_OF_CODES; PRN++)
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{
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std::array<char, 3> data_signal = {'1', 'B', '\0'};
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if (d_track_pilot)
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{
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std::array<char, 3> pilot_signal = {'1', 'C', '\0'};
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galileo_e1_code_gen_sinboc11_float(gsl::span<float>(ca_codes_f, static_cast<int32_t>(GALILEO_E1_B_CODE_LENGTH_CHIPS) * code_samples_per_chip), pilot_signal, PRN);
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galileo_e1_code_gen_sinboc11_float(gsl::span<float>(data_codes_f, static_cast<uint32_t>(GALILEO_E1_B_CODE_LENGTH_CHIPS) * code_samples_per_chip), data_signal, PRN);
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// The code is generated as a series of 1s and -1s. In order to store the values using only one bit, a -1 is stored as a 0 in the FPGA
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for (uint32_t s = 0; s < 2 * GALILEO_E1_B_CODE_LENGTH_CHIPS; s++)
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{
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auto tmp_value = static_cast<int32_t>(ca_codes_f[s]);
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if (tmp_value < 0)
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{
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tmp_value = 0;
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}
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tmp_value = tmp_value | LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY;
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d_ca_codes[static_cast<int32_t>(GALILEO_E1_B_CODE_LENGTH_CHIPS) * 2 * (PRN - 1) + s] = tmp_value;
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tmp_value = static_cast<int32_t>(data_codes_f[s]);
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if (tmp_value < 0)
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{
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tmp_value = 0;
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}
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tmp_value = tmp_value | LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY | LOCAL_CODE_FPGA_CORRELATOR_SELECT_COUNT;
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d_data_codes[static_cast<int32_t>(GALILEO_E1_B_CODE_LENGTH_CHIPS) * 2 * (PRN - 1) + s] = tmp_value;
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}
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}
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else
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{
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galileo_e1_code_gen_sinboc11_float(gsl::span<float>(ca_codes_f, static_cast<int32_t>(GALILEO_E1_B_CODE_LENGTH_CHIPS) * code_samples_per_chip), data_signal, PRN);
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// The code is generated as a series of 1s and -1s. In order to store the values using only one bit, a -1 is stored as a 0 in the FPGA
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for (uint32_t s = 0; s < 2 * GALILEO_E1_B_CODE_LENGTH_CHIPS; s++)
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{
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auto tmp_value = static_cast<int32_t>(ca_codes_f[s]);
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if (tmp_value < 0)
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{
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tmp_value = 0;
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}
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tmp_value = tmp_value | LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY;
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d_ca_codes[static_cast<int32_t>(GALILEO_E1_B_CODE_LENGTH_CHIPS) * 2 * (PRN - 1) + s] = tmp_value;
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}
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}
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}
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volk_gnsssdr_free(ca_codes_f);
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if (d_track_pilot)
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{
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volk_gnsssdr_free(data_codes_f);
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}
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trk_param_fpga.ca_codes = d_ca_codes;
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trk_param_fpga.data_codes = d_data_codes;
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trk_param_fpga.code_length_chips = GALILEO_E1_B_CODE_LENGTH_CHIPS;
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trk_param_fpga.code_samples_per_chip = code_samples_per_chip; // 2 sample per chip
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trk_param_fpga.extended_correlation_in_fpga = false;
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trk_param_fpga.extend_fpga_integration_periods = 1; // (number of FPGA integrations that are combined in the SW)
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trk_param_fpga.fpga_integration_period = 1; // (number of symbols that are effectively integrated in the FPGA)
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//################# MAKE TRACKING GNURadio object ###################
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tracking_fpga_sc = dll_pll_veml_make_tracking_fpga(trk_param_fpga);
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channel_ = 0;
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DLOG(INFO) << "tracking(" << tracking_fpga_sc->unique_id() << ")";
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}
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GalileoE1DllPllVemlTrackingFpga::~GalileoE1DllPllVemlTrackingFpga()
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{
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volk_gnsssdr_free(d_ca_codes);
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if (d_track_pilot)
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{
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volk_gnsssdr_free(d_data_codes);
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}
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}
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void GalileoE1DllPllVemlTrackingFpga::stop_tracking()
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{
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tracking_fpga_sc->stop_tracking();
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}
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void GalileoE1DllPllVemlTrackingFpga::start_tracking()
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{
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tracking_fpga_sc->start_tracking();
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}
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/*
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* Set tracking channel unique ID
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*/
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void GalileoE1DllPllVemlTrackingFpga::set_channel(unsigned int channel)
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{
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channel_ = channel;
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tracking_fpga_sc->set_channel(channel);
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}
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void GalileoE1DllPllVemlTrackingFpga::set_gnss_synchro(Gnss_Synchro* p_gnss_synchro)
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{
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tracking_fpga_sc->set_gnss_synchro(p_gnss_synchro);
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}
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void GalileoE1DllPllVemlTrackingFpga::connect(gr::top_block_sptr top_block)
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{
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if (top_block)
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{ /* top_block is not null */
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};
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// nothing to connect, now the tracking uses gr_sync_decimator
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}
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void GalileoE1DllPllVemlTrackingFpga::disconnect(gr::top_block_sptr top_block)
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{
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if (top_block)
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{ /* top_block is not null */
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};
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// nothing to disconnect, now the tracking uses gr_sync_decimator
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}
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gr::basic_block_sptr GalileoE1DllPllVemlTrackingFpga::get_left_block()
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{
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return tracking_fpga_sc;
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}
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gr::basic_block_sptr GalileoE1DllPllVemlTrackingFpga::get_right_block()
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{
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return tracking_fpga_sc;
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}
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