mirror of
https://github.com/gnss-sdr/gnss-sdr
synced 2024-12-15 04:30:33 +00:00
b849b20a8c
- Added a pre-compiled custom GN3S firmware. - Added a fully-compliant GNU Radio source block for GN3S USB dongle. It can be used also from GNU Radio companion and from Python applications. - Added a new GN3S_Signal_Source block. It is possible to disable the GN3S signal source compilation. See README. git-svn-id: https://svn.code.sf.net/p/gnss-sdr/code/trunk@217 64b25241-fba3-4117-9849-534c7e92360d
66 lines
2.1 KiB
C++
66 lines
2.1 KiB
C++
/* -*- c++ -*- */
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/*
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* Copyright 2003 Free Software Foundation, Inc.
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*
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* This file is part of GNU Radio
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*
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* GNU Radio is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* GNU Radio is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GNU Radio; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
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* Boston, MA 02111-1307, USA.
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*/
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#ifndef _SYNCDELAY_H_
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#define _SYNCDELAY_H_
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/*
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* Magic delay required between access to certain xdata registers (TRM page 15-106).
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* For our configuration, 48 MHz FX2 / 48 MHz IFCLK, we need three cycles. Each
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* NOP is a single cycle....
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*
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* From TRM page 15-105:
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*
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* Under certain conditions, some read and write access to the FX2 registers must
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* be separated by a "synchronization delay". The delay is necessary only under the
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* following conditions:
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*
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* - between a write to any register in the 0xE600 - 0xE6FF range and a write to one
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* of the registers listed below.
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*
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* - between a write to one of the registers listed below and a read from any register
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* in the 0xE600 - 0xE6FF range.
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*
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* Registers which require a synchronization delay:
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*
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* FIFORESET FIFOPINPOLAR
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* INPKTEND EPxBCH:L
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* EPxFIFOPFH:L EPxAUTOINLENH:L
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* EPxFIFOCFG EPxGPIFFLGSEL
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* PINFLAGSAB PINFLAGSCD
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* EPxFIFOIE EPxFIFOIRQ
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* GPIFIE GPIFIRQ
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* UDMACRCH:L GPIFADRH:L
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* GPIFTRIG EPxGPIFTRIG
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* OUTPKTEND REVCTL
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* GPIFTCB3 GPIFTCB2
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* GPIFTCB1 GPIFTCB0
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*/
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/*
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* FIXME ensure that the peep hole optimizer isn't screwing us
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*/
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#define SYNCDELAY _asm nop; nop; nop; _endasm
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#define NOP _asm nop; _endasm
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#endif /* _SYNCDELAY_H_ */
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