mirror of
https://github.com/gnss-sdr/gnss-sdr
synced 2024-12-15 12:40:35 +00:00
b849b20a8c
- Added a pre-compiled custom GN3S firmware. - Added a fully-compliant GNU Radio source block for GN3S USB dongle. It can be used also from GNU Radio companion and from Python applications. - Added a new GN3S_Signal_Source block. It is possible to disable the GN3S signal source compilation. See README. git-svn-id: https://svn.code.sf.net/p/gnss-sdr/code/trunk@217 64b25241-fba3-4117-9849-534c7e92360d
180 lines
11 KiB
Plaintext
180 lines
11 KiB
Plaintext
1 ;--------------------------------------------------------
|
|
2 ; File Created by SDCC : free open source ANSI-C Compiler
|
|
3 ; Version 2.9.0 #5416 (Feb 3 2010) (UNIX)
|
|
4 ; This file was generated Mon Jul 30 11:40:52 2012
|
|
5 ;--------------------------------------------------------
|
|
6 .module delay
|
|
7 .optsdcc -mmcs51 --model-small
|
|
8
|
|
9 ;--------------------------------------------------------
|
|
10 ; Public variables in this module
|
|
11 ;--------------------------------------------------------
|
|
12 .globl _mdelay
|
|
13 .globl _udelay
|
|
14 ;--------------------------------------------------------
|
|
15 ; special function registers
|
|
16 ;--------------------------------------------------------
|
|
17 .area RSEG (DATA)
|
|
18 ;--------------------------------------------------------
|
|
19 ; special function bits
|
|
20 ;--------------------------------------------------------
|
|
21 .area RSEG (DATA)
|
|
22 ;--------------------------------------------------------
|
|
23 ; overlayable register banks
|
|
24 ;--------------------------------------------------------
|
|
25 .area REG_BANK_0 (REL,OVR,DATA)
|
|
0000 26 .ds 8
|
|
27 ;--------------------------------------------------------
|
|
28 ; internal ram data
|
|
29 ;--------------------------------------------------------
|
|
30 .area DSEG (DATA)
|
|
31 ;--------------------------------------------------------
|
|
32 ; overlayable items in internal ram
|
|
33 ;--------------------------------------------------------
|
|
34 .area OSEG (OVR,DATA)
|
|
35 ;--------------------------------------------------------
|
|
36 ; indirectly addressable internal ram data
|
|
37 ;--------------------------------------------------------
|
|
38 .area ISEG (DATA)
|
|
39 ;--------------------------------------------------------
|
|
40 ; absolute internal ram data
|
|
41 ;--------------------------------------------------------
|
|
42 .area IABS (ABS,DATA)
|
|
43 .area IABS (ABS,DATA)
|
|
44 ;--------------------------------------------------------
|
|
45 ; bit data
|
|
46 ;--------------------------------------------------------
|
|
47 .area BSEG (BIT)
|
|
48 ;--------------------------------------------------------
|
|
49 ; paged external ram data
|
|
50 ;--------------------------------------------------------
|
|
51 .area PSEG (PAG,XDATA)
|
|
52 ;--------------------------------------------------------
|
|
53 ; external ram data
|
|
54 ;--------------------------------------------------------
|
|
55 .area XSEG (XDATA)
|
|
56 ;--------------------------------------------------------
|
|
57 ; absolute external ram data
|
|
58 ;--------------------------------------------------------
|
|
59 .area XABS (ABS,XDATA)
|
|
60 ;--------------------------------------------------------
|
|
61 ; external initialized ram data
|
|
62 ;--------------------------------------------------------
|
|
63 .area HOME (CODE)
|
|
64 .area GSINIT0 (CODE)
|
|
65 .area GSINIT1 (CODE)
|
|
66 .area GSINIT2 (CODE)
|
|
67 .area GSINIT3 (CODE)
|
|
68 .area GSINIT4 (CODE)
|
|
69 .area GSINIT5 (CODE)
|
|
70 .area GSINIT (CODE)
|
|
71 .area GSFINAL (CODE)
|
|
72 .area CSEG (CODE)
|
|
73 ;--------------------------------------------------------
|
|
74 ; global & static initialisations
|
|
75 ;--------------------------------------------------------
|
|
76 .area HOME (CODE)
|
|
77 .area GSINIT (CODE)
|
|
78 .area GSFINAL (CODE)
|
|
79 .area GSINIT (CODE)
|
|
80 ;--------------------------------------------------------
|
|
81 ; Home
|
|
82 ;--------------------------------------------------------
|
|
83 .area HOME (CODE)
|
|
84 .area HOME (CODE)
|
|
85 ;--------------------------------------------------------
|
|
86 ; code
|
|
87 ;--------------------------------------------------------
|
|
88 .area CSEG (CODE)
|
|
89 ;------------------------------------------------------------
|
|
90 ;Allocation info for local variables in function 'udelay1'
|
|
91 ;------------------------------------------------------------
|
|
92 ;------------------------------------------------------------
|
|
93 ; delay.c:27: udelay1 (void) _naked
|
|
94 ; -----------------------------------------
|
|
95 ; function udelay1
|
|
96 ; -----------------------------------------
|
|
0000 97 _udelay1:
|
|
98 ; naked function: no prologue.
|
|
99 ; delay.c:31: _endasm;
|
|
100 ; lcall that got us here took 4 bus cycles
|
|
0000 22 101 ret ; 4 bus cycles
|
|
102
|
|
103 ; naked function: no epilogue.
|
|
104 ;------------------------------------------------------------
|
|
105 ;Allocation info for local variables in function 'udelay'
|
|
106 ;------------------------------------------------------------
|
|
107 ;usecs Allocated to registers r2
|
|
108 ;------------------------------------------------------------
|
|
109 ; delay.c:38: udelay (unsigned char usecs)
|
|
110 ; -----------------------------------------
|
|
111 ; function udelay
|
|
112 ; -----------------------------------------
|
|
0001 113 _udelay:
|
|
0002 114 ar2 = 0x02
|
|
0003 115 ar3 = 0x03
|
|
0004 116 ar4 = 0x04
|
|
0005 117 ar5 = 0x05
|
|
0006 118 ar6 = 0x06
|
|
0007 119 ar7 = 0x07
|
|
0000 120 ar0 = 0x00
|
|
0001 121 ar1 = 0x01
|
|
0001 AA 82 122 mov r2,dpl
|
|
123 ; delay.c:40: do {
|
|
0003 124 00101$:
|
|
125 ; delay.c:41: udelay1 ();
|
|
0003 12s00r00 126 lcall _udelay1
|
|
127 ; delay.c:42: } while (--usecs != 0);
|
|
0006 DA FB 128 djnz r2,00101$
|
|
0008 22 129 ret
|
|
130 ;------------------------------------------------------------
|
|
131 ;Allocation info for local variables in function 'mdelay1'
|
|
132 ;------------------------------------------------------------
|
|
133 ;------------------------------------------------------------
|
|
134 ; delay.c:54: mdelay1 (void) _naked
|
|
135 ; -----------------------------------------
|
|
136 ; function mdelay1
|
|
137 ; -----------------------------------------
|
|
0009 138 _mdelay1:
|
|
139 ; naked function: no prologue.
|
|
140 ; delay.c:65: _endasm;
|
|
141
|
|
0009 90 FB 50 142 mov dptr,#(-1200 & 0xffff)
|
|
000C 143 002$:
|
|
000C A3 144 inc dptr ; 3 bus cycles
|
|
000D E5 82 145 mov a, dpl ; 2 bus cycles
|
|
000F 45 83 146 orl a, dph ; 2 bus cycles
|
|
0011 70 F9 147 jnz 002$ ; 3 bus cycles
|
|
148
|
|
0013 22 149 ret
|
|
150
|
|
151 ; naked function: no epilogue.
|
|
152 ;------------------------------------------------------------
|
|
153 ;Allocation info for local variables in function 'mdelay'
|
|
154 ;------------------------------------------------------------
|
|
155 ;msecs Allocated to registers r2 r3
|
|
156 ;------------------------------------------------------------
|
|
157 ; delay.c:69: mdelay (unsigned int msecs)
|
|
158 ; -----------------------------------------
|
|
159 ; function mdelay
|
|
160 ; -----------------------------------------
|
|
0014 161 _mdelay:
|
|
0014 AA 82 162 mov r2,dpl
|
|
0016 AB 83 163 mov r3,dph
|
|
164 ; delay.c:71: do {
|
|
0018 165 00101$:
|
|
166 ; delay.c:72: mdelay1 ();
|
|
0018 12s00r09 167 lcall _mdelay1
|
|
168 ; delay.c:73: } while (--msecs != 0);
|
|
001B 1A 169 dec r2
|
|
001C BA FF 01 170 cjne r2,#0xff,00108$
|
|
001F 1B 171 dec r3
|
|
0020 172 00108$:
|
|
0020 EA 173 mov a,r2
|
|
0021 4B 174 orl a,r3
|
|
0022 70 F4 175 jnz 00101$
|
|
0024 22 176 ret
|
|
177 .area CSEG (CODE)
|
|
178 .area CONST (CODE)
|
|
179 .area CABS (ABS,CODE)
|