Marc Majoral
2b46c79ba7
optimized the process of computing and writing the fft of the local code to the acquisition HW accelerator.
...
The writing of the local code is still performed by processor instructions in a loop.
THe FPGA L2 classes were updated accordingly.
2019-03-26 12:26:08 +01:00
Marc Majoral
905a85670c
currently optimizing the FPGA-related code
2019-03-25 19:45:54 +01:00
Carles Fernandez
41036c1538
Fix kernel
2019-03-24 19:53:51 +01:00
Carles Fernandez
d8f1e4b437
Increase required accuracy in 32-bit rotator_dot_prod test results
2019-03-24 19:35:53 +01:00
Carles Fernandez
441ff637eb
Fix AVX implementation
...
Samples that are remanent from num_points / 16 were not adecuately integrated
2019-03-24 13:50:12 +01:00
Carles Fernandez
b0199e1061
Improve style consistency
2019-03-23 14:24:49 +01:00
Carles Fernandez
7587d5fd4b
Update changelog
2019-03-23 13:59:31 +01:00
Carles Fernandez
026f045b93
Clean anotations (remove trailing /)
2019-03-23 13:15:25 +01:00
Carles Fernandez
1b0697fdf9
Simplify script
2019-03-23 12:59:49 +01:00
Carles Fernandez
28ade25157
Improve OpenSSL detection in Homebrew and messages if it fails
2019-03-23 12:57:45 +01:00
Carles Fernandez
b0f971fc56
Remove wrong lines from old script
2019-03-23 11:31:53 +01:00
Carles Fernandez
e2d3ad53a1
Add openSUSE to the list of distributions, reorder alphabetically
2019-03-23 11:28:50 +01:00
Carles Fernandez
a94e74def2
Search for generic BLAS and LAPACK implementations
2019-03-23 00:43:01 +01:00
Marc Majoral
2bae20d2fd
Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga
...
added second acquisition to reduce the time between acquisition and tracking when using the FPGA
moved the process of writing of the tracking local code to the HW accelerator from the start_tracking() function to the set_gnss_synchro() function (this is only applicable for the FPGA case)
there was a bug in the computation of the tracking starting position for the L1/E1 band when using the FPGA, only high sample counter values (>31 bits) were affected, due to a uint64_t*float mult.
2019-03-22 19:03:46 +01:00
Javier Arribas
c877e74565
-Adding more FPGA helpers to channel operations
2019-03-22 18:11:45 +01:00
Javier Arribas
f9b450bc80
Adding channel modifications for FPGA acceleration
2019-03-22 16:03:09 +01:00
Carles Fernandez
52aa4290d8
Update suggested glog and armadillo versions if built manually
2019-03-22 13:45:52 +01:00
Carles Fernandez
cb59c1cc83
Fix bug in MacOS when BeiDou was enabled in rtklib.h
...
The BLAS and LAPACK implementations that come with the Accelerate Framework (soft-linked in /usr/bin) caused a random crash when exiting the program, only if the variable ENABDS was set. This bug disappears when linking to the libraries that Homebrew or Macports install, or when manually downloaded, built and installed by the user
2019-03-22 11:00:13 +01:00
Carles Fernandez
c2917939ba
Update glog vesion to 0.4.0
2019-03-22 09:33:29 +01:00
Carles Fernandez
33403dedea
Fix high_dynamics correlator
2019-03-21 21:10:56 +01:00
Carles Fernandez
6a17a33d6f
Expose more tracking parameters to the configuration: filters order, FLL usage, pull-in time
2019-03-21 19:21:39 +01:00
Carles Fernandez
446d3baf32
Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into next
2019-03-20 20:56:47 +01:00
Carles Fernandez
88b60aa6b1
Remove unused includes
2019-03-20 18:08:39 +01:00
Carles Fernandez
f3d91bbd38
Remove unused includes
2019-03-20 18:00:37 +01:00
Marc Majoral
e6b661494c
moved to 16 bits per local code.
2019-03-20 16:59:32 +01:00
Javier Arribas
55b1f316ed
Removing gnuradio block inheritance in FPGA acquisition
2019-03-20 16:57:50 +01:00
Marc Majoral
6da82535ba
Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga
2019-03-20 16:35:55 +01:00
Carles Fernandez
8a52c20e28
Add missing override keyword
2019-03-20 15:44:59 +01:00
Javier Arribas
0be8c657de
Reducing the latency in the acquisition to tracking transition
2019-03-20 15:13:17 +01:00
Carles Fernandez
994f192636
Fix warning if put_time is not present
2019-03-19 21:11:21 +01:00
Carles Fernandez
10d73da839
Fix typo
2019-03-19 20:39:23 +01:00
Carles Fernandez
c8d27eb97c
Move contructor to the beginning of the file
2019-03-19 20:37:42 +01:00
Carles Fernandez
296d6d66c9
Move constants to implementation, fix typos in comments
2019-03-19 20:16:59 +01:00
Carles Fernandez
4bc4fb9988
Remove misleading comment
2019-03-19 19:53:51 +01:00
Carles Fernandez
5d423f3c59
Fix overflow
2019-03-19 19:51:54 +01:00
Javier Arribas
16ead9c613
Removing innecessary usleep
2019-03-19 18:18:44 +01:00
Marc Majoral
a24d26f427
set the default sampling frequency of the HW source to 12.5 Msps and the default bandpass bandwidth to 12.5 MHz + other minor changes
2019-03-19 10:14:09 +01:00
Carles Fernandez
3cd1e70706
Fix defects detected by Coverity Scan
2019-03-19 07:53:21 +01:00
Carles Fernandez
7fae75380f
Fix run-tests: disconnect internal async channels in destructor
2019-03-18 22:59:47 +01:00
Carles Fernandez
620f0ab77e
Remove clang-format label
2019-03-18 22:23:51 +01:00
Javier Arribas
df46cdeb65
Add missing message ports to trackings
2019-03-18 21:49:59 +01:00
Carles Fernandez
2afcbb7803
Fix warning
2019-03-18 21:47:36 +01:00
Javier Arribas
cac6fa7f84
Add missing message ports to trackings
2019-03-18 21:35:55 +01:00
Carles Fernandez
c754f77417
Add BeiDou B3I, reorder signals from higher to lower frequency
2019-03-18 21:28:15 +01:00
Carles Fernandez
2f14432067
Apply formatting
2019-03-18 19:50:02 +01:00
Carles Fernandez
b0c19c03f3
Apply formatting
2019-03-18 19:41:41 +01:00
Marc Majoral
bef7e42fb9
Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into fpga
2019-03-18 19:37:19 +01:00
Javier Arribas
48180c967a
Replacing PLL/DLL fixed order loop filters with DLL/PLL/FLL order-configurable filters. Adding PLL false lock protection by using telemetry validation flag
2019-03-18 19:35:40 +01:00
Carles Fernandez
018b97fe7b
Merge branch 'dmiralles2009-bds_b3i' into next. Add BeiDou B3I processing chain
2019-03-18 19:32:46 +01:00
Carles Fernandez
597ef26092
Minor fixes
2019-03-18 19:28:35 +01:00
