Marc Majoral
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8b512d997b
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Remove the EZDMA driver, fix time reporting when using the FPGA, and include minor fixes for the dynamic bit selection, the AD9361 FPGA signal source, and the FPGA acquisition sampling factor parameter
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2023-12-20 18:56:04 +01:00 |
Marc Majoral
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5c0826b11e
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Optimize the use of the FPGA dynamic bit selection blocks. Reorder AD9361 FPGA signal source private members by size. use ssize_t write() return value.
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2023-09-13 17:19:10 +02:00 |
Marc Majoral
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740a2762bc
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Initialize the dynamic bit selection shift register
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2021-11-15 12:47:33 +01:00 |
Carles Fernandez
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d6d1fff743
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Apply clang-tidy fixes when -DENABLE_FPGA=ON
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2021-01-25 22:07:59 +01:00 |
Carles Fernandez
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7308745f05
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Apply more concise file header format
Re-license CMake scripts with BSD-3-Clause
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2020-12-30 13:35:06 +01:00 |
Carles Fernandez
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499de7a9f1
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Update file headers
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2020-07-28 16:57:15 +02:00 |
Carles Fernandez
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08fa55c585
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Add missing includes, use \n instead of endl
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2020-07-16 19:07:58 +02:00 |
Marc Majoral
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98f1287f0e
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dynamic bit selection based on the estimated power of the received signal.
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2020-07-16 15:42:55 +02:00 |