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Code cleaning: remove tabulators, remove multiple blank lines

This commit is contained in:
Carles Fernandez 2017-03-13 20:54:25 +01:00
parent 507bc86cc9
commit ef5cb645a7
9 changed files with 290 additions and 336 deletions
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36
src/algorithms/tracking/adapters/gps_l1_ca_dll_pll_c_aid_tracking_fpga.cc
View File

@ -3,7 +3,7 @@
* \brief Implementation of an adapter of a DLL+PLL tracking loop block
* for GPS L1 C/A to a TrackingInterface
* \author Marc Majoral, 2017. mmajoral(at)cttc.cat
* Carlos Aviles, 2010. carlos.avilesr(at)googlemail.com
* Carlos Aviles, 2010. carlos.avilesr(at)googlemail.com
* Javier Arribas, 2011. jarribas(at)cttc.es
*
* Code DLL + carrier PLL according to the algorithms described in:
@ -48,7 +48,7 @@ using google::LogMessage;
GpsL1CaDllPllCAidTrackingFpga::GpsL1CaDllPllCAidTrackingFpga(
ConfigurationInterface* configuration, std::string role,
unsigned int in_streams, unsigned int out_streams) :
role_(role), in_streams_(in_streams), out_streams_(out_streams)
role_(role), in_streams_(in_streams), out_streams_(out_streams)
{
DLOG(INFO) << "role " << role;
//################# CONFIGURATION PARAMETERS ########################
@ -102,8 +102,8 @@ GpsL1CaDllPllCAidTrackingFpga::GpsL1CaDllPllCAidTrackingFpga(
else
{
item_size_ = sizeof(lv_16sc_t);
// LOG(WARNING) << item_type_ << " unknown tracking item type";
item_size_ = sizeof(lv_16sc_t);
// LOG(WARNING) << item_type_ << " unknown tracking item type";
LOG(WARNING) << item_type_ << " the tracking item type for the FPGA tracking test has to be cshort";
}
channel_ = 0;
@ -112,7 +112,7 @@ GpsL1CaDllPllCAidTrackingFpga::GpsL1CaDllPllCAidTrackingFpga(
GpsL1CaDllPllCAidTrackingFpga::~GpsL1CaDllPllCAidTrackingFpga()
{
printf("gspl1cadllpllcaidtrackingfpga destructor called\n");
LOG(INFO) << "gspl1cadllpllcaidtrackingfpga destructor called";
}
@ -125,11 +125,12 @@ void GpsL1CaDllPllCAidTrackingFpga::start_tracking()
}
else
{
// LOG(WARNING) << item_type_ << " unknown tracking item type";
// LOG(WARNING) << item_type_ << " unknown tracking item type";
LOG(WARNING) << item_type_ << " the tracking item type for the FPGA tracking test has to be cshort";
}
}
/*
* Set tracking channel unique ID
*/
@ -143,11 +144,12 @@ void GpsL1CaDllPllCAidTrackingFpga::set_channel(unsigned int channel)
}
else
{
// LOG(WARNING) << item_type_ << " unknown tracking item type";
LOG(WARNING) << item_type_ << " the tracking item type for the FPGA tracking test has to be cshort";
// LOG(WARNING) << item_type_ << " unknown tracking item type";
LOG(WARNING) << item_type_ << " the tracking item type for the FPGA tracking test has to be cshort";
}
}
void GpsL1CaDllPllCAidTrackingFpga::set_gnss_synchro(Gnss_Synchro* p_gnss_synchro)
{
if (item_type_.compare("cshort") == 0)
@ -156,44 +158,42 @@ void GpsL1CaDllPllCAidTrackingFpga::set_gnss_synchro(Gnss_Synchro* p_gnss_synchr
}
else
{
// LOG(WARNING) << item_type_ << " unknown tracking item type";
LOG(WARNING) << item_type_ << " the tracking item type for the FPGA tracking test has to be cshort";
// LOG(WARNING) << item_type_ << " unknown tracking item type";
LOG(WARNING) << item_type_ << " the tracking item type for the FPGA tracking test has to be cshort";
}
}
void GpsL1CaDllPllCAidTrackingFpga::connect(gr::top_block_sptr top_block)
{
if(top_block) { /* top_block is not null */};
//nothing to connect, now the tracking uses gr_sync_decimator
}
void GpsL1CaDllPllCAidTrackingFpga::disconnect(gr::top_block_sptr top_block)
{
if(top_block) { /* top_block is not null */};
//nothing to disconnect, now the tracking uses gr_sync_decimator
}
// CONVERT TO SOURCE
gr::basic_block_sptr GpsL1CaDllPllCAidTrackingFpga::get_left_block()
{
if (item_type_.compare("cshort") == 0)
{
return tracking_fpga_sc;
}
else
{
//LOG(WARNING) << item_type_ << " unknown tracking item type";
LOG(WARNING) << item_type_ << " the tracking item type for the FPGA tracking test has to be cshort";
LOG(WARNING) << item_type_ << " the tracking item type for the FPGA tracking test has to be cshort";
return nullptr;
}
}
gr::basic_block_sptr GpsL1CaDllPllCAidTrackingFpga::get_right_block()
{
if (item_type_.compare("cshort") == 0)
@ -203,7 +203,7 @@ gr::basic_block_sptr GpsL1CaDllPllCAidTrackingFpga::get_right_block()
else
{
//LOG(WARNING) << item_type_ << " unknown tracking item type";
LOG(WARNING) << item_type_ << " the tracking item type for the FPGA tracking test has to be cshort";
LOG(WARNING) << item_type_ << " the tracking item type for the FPGA tracking test has to be cshort";
return nullptr;
}
}

3
src/algorithms/tracking/adapters/gps_l1_ca_dll_pll_c_aid_tracking_fpga.h
View File

@ -52,8 +52,7 @@ class ConfigurationInterface;
class GpsL1CaDllPllCAidTrackingFpga : public TrackingInterface
{
public:
GpsL1CaDllPllCAidTrackingFpga(ConfigurationInterface* configuration,
GpsL1CaDllPllCAidTrackingFpga(ConfigurationInterface* configuration,
std::string role,
unsigned int in_streams,
unsigned int out_streams);

8
src/algorithms/tracking/gnuradio_blocks/gps_l1_ca_dll_pll_c_aid_tracking_fpga_sc.cc
View File

@ -309,8 +309,6 @@ gps_l1_ca_dll_pll_c_aid_tracking_fpga_sc::~gps_l1_ca_dll_pll_c_aid_tracking_fpga
int gps_l1_ca_dll_pll_c_aid_tracking_fpga_sc::general_work (int noutput_items __attribute__((unused)), gr_vector_int &ninput_items __attribute__((unused)),
gr_vector_const_void_star &input_items, gr_vector_void_star &output_items)
{
// Block input data and block output stream pointers
Gnss_Synchro **out = (Gnss_Synchro **) &output_items[0];
@ -321,8 +319,6 @@ int gps_l1_ca_dll_pll_c_aid_tracking_fpga_sc::general_work (int noutput_items __
double CURRENT_INTEGRATION_TIME_S = 0.0;
double CORRECTED_INTEGRATION_TIME_S = 0.0;
if (d_enable_tracking == true)
{
// Fill the acquisition data
@ -655,11 +651,11 @@ void gps_l1_ca_dll_pll_c_aid_tracking_fpga_sc::set_channel(unsigned int channel)
d_dump_filename.append(".dat");
d_dump_file.exceptions (std::ifstream::failbit | std::ifstream::badbit);
d_dump_file.open(d_dump_filename.c_str(), std::ios::out | std::ios::binary);
LOG(INFO) << "Tracking dump enabled on channel " << d_channel << " Log file: " << d_dump_filename.c_str() << std::endl;
LOG(INFO) << "Tracking dump enabled on channel " << d_channel << " Log file: " << d_dump_filename.c_str();
}
catch (const std::ifstream::failure* e)
{
LOG(WARNING) << "channel " << d_channel << " Exception opening trk dump file " << e->what() << std::endl;
LOG(WARNING) << "channel " << d_channel << " Exception opening trk dump file " << e->what();
}
}
}

2
src/algorithms/tracking/gnuradio_blocks/gps_l1_ca_dll_pll_c_aid_tracking_fpga_sc.h
View File

@ -2,7 +2,7 @@
* \file gps_l1_ca_dll_pll_c_aid_tracking_fpga_sc.h
* \brief Interface of a code DLL + carrier PLL tracking block
* \author Marc Majoral, 2017. mmajoral(at)cttc.cat
* Carlos Aviles, 2010. carlos.avilesr(at)googlemail.com
* Carlos Aviles, 2010. carlos.avilesr(at)googlemail.com
* Javier Arribas, 2011. jarribas(at)cttc.es
*
* Code DLL + carrier PLL according to the algorithms described in:

371
src/algorithms/tracking/libs/fpga_multicorrelator_8sc.cc
View File

@ -2,9 +2,9 @@
* \file fpga_multicorrelator_8sc.cc
* \brief High optimized FPGA vector correlator class
* \authors <ul>
* <li> Marc Majoral, 2017. mmajoral(at)cttc.cat
* <li> Javier Arribas, 2015. jarribas(at)cttc.es
* </ul>
* <li> Marc Majoral, 2017. mmajoral(at)cttc.cat
* <li> Javier Arribas, 2015. jarribas(at)cttc.es
* </ul>
*
* Class that controls and executes a high optimized vector correlator
* class in the FPGA
@ -77,7 +77,6 @@ bool fpga_multicorrelator_8sc::init(
int n_correlators)
{
size_t size = max_signal_length_samples * sizeof(lv_16sc_t);
d_n_correlators = n_correlators;
// instantiate variable length vectors
@ -87,12 +86,13 @@ bool fpga_multicorrelator_8sc::init(
return true;
}
void fpga_multicorrelator_8sc::set_initial_sample(int samples_offset)
{
d_initial_sample_counter = samples_offset;
d_initial_sample_counter = samples_offset;
}
bool fpga_multicorrelator_8sc::set_local_code_and_taps(
int code_length_chips,
const lv_16sc_t* local_code_in,
@ -102,12 +102,9 @@ bool fpga_multicorrelator_8sc::set_local_code_and_taps(
d_shifts_chips = shifts_chips;
d_code_length_chips = code_length_chips;
fpga_multicorrelator_8sc::fpga_configure_tracking_gps_local_code();
return true;
}
@ -122,15 +119,10 @@ bool fpga_multicorrelator_8sc::set_output_vectors(lv_16sc_t* corr_out)
void fpga_multicorrelator_8sc::update_local_code(int correlator_length_samples, float rem_code_phase_chips, float code_phase_step_chips)
{
d_rem_code_phase_chips = rem_code_phase_chips;
d_rem_code_phase_chips = rem_code_phase_chips;
fpga_multicorrelator_8sc::fpga_compute_code_shift_parameters();
fpga_multicorrelator_8sc::fpga_configure_code_parameters_in_fpga();
}
@ -141,9 +133,8 @@ bool fpga_multicorrelator_8sc::Carrier_wipeoff_multicorrelator_resampler(
float code_phase_step_chips,
int signal_length_samples)
{
update_local_code(signal_length_samples, rem_code_phase_chips, code_phase_step_chips);
d_rem_carrier_phase_in_rad = rem_carrier_phase_in_rad;
d_code_phase_step_chips = code_phase_step_chips;
d_phase_step_rad = phase_step_rad;
@ -151,18 +142,17 @@ bool fpga_multicorrelator_8sc::Carrier_wipeoff_multicorrelator_resampler(
fpga_multicorrelator_8sc::fpga_compute_signal_parameters_in_fpga();
fpga_multicorrelator_8sc::fpga_configure_signal_parameters_in_fpga();
fpga_multicorrelator_8sc::fpga_launch_multicorrelator_fpga();
fpga_multicorrelator_8sc::fpga_launch_multicorrelator_fpga();
int irq_count;
ssize_t nb;
// wait for interrupt
nb=read(d_fd, &irq_count, sizeof(irq_count));
if (nb != sizeof(irq_count))
{
printf("Tracking_module Read failed to retrive 4 bytes!\n");
printf("Tracking_module Interrupt number %d\n", irq_count);
}
if (nb != sizeof(irq_count))
{
printf("Tracking_module Read failed to retrive 4 bytes!\n");
printf("Tracking_module Interrupt number %d\n", irq_count);
}
fpga_multicorrelator_8sc::read_tracking_gps_results();
@ -182,265 +172,254 @@ fpga_multicorrelator_8sc::fpga_multicorrelator_8sc()
fpga_multicorrelator_8sc::~fpga_multicorrelator_8sc()
{
close(d_fd);
}
bool fpga_multicorrelator_8sc::free()
{
// unlock the hardware
fpga_multicorrelator_8sc::unlock_channel(); // unlock the channel
fpga_multicorrelator_8sc::unlock_channel(); // unlock the channel
// free the FPGA dynamically created variables
if (d_initial_index != nullptr)
{
{
volk_gnsssdr_free(d_initial_index);
d_initial_index = nullptr;
}
}
if (d_initial_interp_counter != nullptr)
{
{
volk_gnsssdr_free(d_initial_interp_counter);
d_initial_interp_counter = nullptr;
}
}
return true;
}
void fpga_multicorrelator_8sc::set_channel(unsigned int channel)
{
d_channel = channel;
snprintf(d_device_io_name, MAX_LENGTH_DEVICEIO_NAME, "/dev/uio%d",d_channel);
printf("Opening Device Name : %s\n", d_device_io_name);
if ((d_fd = open(d_device_io_name, O_RDWR | O_SYNC )) == -1)
{
LOG(WARNING) << "Cannot open deviceio" << d_device_io_name;
}
{
LOG(WARNING) << "Cannot open deviceio" << d_device_io_name;
}
d_map_base = (volatile unsigned *)mmap(NULL, PAGE_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, d_fd,0);
if (d_map_base == (void *) -1)
{
LOG(WARNING) << "Cannot map the FPGA tracking module " << d_channel << "into user memory";
}
{
LOG(WARNING) << "Cannot map the FPGA tracking module " << d_channel << "into user memory";
}
// sanity check : check test register
unsigned writeval = 0x55AA;
unsigned readval;
readval = fpga_multicorrelator_8sc::fpga_acquisition_test_register(writeval);
if (writeval != readval)
{
LOG(WARNING) << "Test register sanity check failed";
}
{
LOG(WARNING) << "Test register sanity check failed";
}
else
{
printf("Test register sanity check success !\n");
}
{
LOG(INFO) << "Test register sanity check success !";
}
}
unsigned fpga_multicorrelator_8sc::fpga_acquisition_test_register(unsigned writeval)
{
unsigned readval;
// write value to test register
d_map_base[15] = writeval;
// read value from test register
readval = d_map_base[15];
// return read value
return readval;
unsigned readval;
// write value to test register
d_map_base[15] = writeval;
// read value from test register
readval = d_map_base[15];
// return read value
return readval;
}
void fpga_multicorrelator_8sc::fpga_configure_tracking_gps_local_code(void)
{
int k,s;
unsigned temp;
unsigned *ena_write_signals;
ena_write_signals = new unsigned[d_n_correlators];
ena_write_signals[0]= 0x00000000;
ena_write_signals[1]= 0x20000000;
for (s=2;s<d_n_correlators;s++)
{
ena_write_signals[s]= ena_write_signals[s-1]*2; //0x40000000;
}
int k,s;
unsigned temp;
unsigned *ena_write_signals;
ena_write_signals = new unsigned[d_n_correlators];
ena_write_signals[0] = 0x00000000;
ena_write_signals[1] = 0x20000000;
for (s = 2; s < d_n_correlators; s++)
{
ena_write_signals[s]= ena_write_signals[s-1]*2; //0x40000000;
}
for (s=0;s<d_n_correlators;s++)
{
// clear memory address counter
d_map_base[11] = 0x10000000;
// write correlator 0
for (k=0;k< d_code_length_chips;k++)
{
if (lv_creal(d_local_code_in[k]) == 1)
{
temp = 1;
}
else
{
temp = 0;
}
d_map_base[11] = 0x0C000000 | (temp & 0xFFFF) | ena_write_signals[s];
for (s = 0; s < d_n_correlators; s++)
{
// clear memory address counter
d_map_base[11] = 0x10000000;
// write correlator 0
for (k = 0; k < d_code_length_chips; k++)
{
if (lv_creal(d_local_code_in[k]) == 1)
{
temp = 1;
}
else
{
temp = 0;
}
d_map_base[11] = 0x0C000000 | (temp & 0xFFFF) | ena_write_signals[s];
}
}
}
}
delete [] ena_write_signals;
delete [] ena_write_signals;
}
void fpga_multicorrelator_8sc::fpga_compute_code_shift_parameters(void)
{
float tempvalues[3];
float tempvalues2[3];
float tempvalues3[3];
int i;
float tempvalues[3];
float tempvalues2[3];
float tempvalues3[3];
int i;
for (i=0;i<d_n_correlators;i++)
{
// initial index calculation
tempvalues[i] = floor(d_shifts_chips[i] + d_rem_code_phase_chips);
if (tempvalues[i] < 0)
{
tempvalues2[i] = tempvalues[i] + d_code_length_chips; // % operator does not work as in Matlab with negative numbers
}
else
{
tempvalues2[i] = tempvalues[i];
}
d_initial_index[i] = (unsigned) ((int) tempvalues2[i]) % d_code_length_chips;
// initial interpolator counter calculation
tempvalues3[i] = fmod(d_shifts_chips[i]+ d_rem_code_phase_chips,1.0);
if (tempvalues3[i] < 0)
{
tempvalues3[i] = tempvalues3[i] + 1.0; // fmod operator does not work as in Matlab with negative numbers
}
d_initial_interp_counter[i] = (unsigned) floor(MAX_CODE_RESAMPLER_COUNTER * tempvalues3[i]);
}
for (i = 0; i < d_n_correlators; i++)
{
// initial index calculation
tempvalues[i] = floor(d_shifts_chips[i] + d_rem_code_phase_chips);
if (tempvalues[i] < 0)
{
tempvalues2[i] = tempvalues[i] + d_code_length_chips; // % operator does not work as in Matlab with negative numbers
}
else
{
tempvalues2[i] = tempvalues[i];
}
d_initial_index[i] = (unsigned) ((int) tempvalues2[i]) % d_code_length_chips;
// initial interpolator counter calculation
tempvalues3[i] = fmod(d_shifts_chips[i]+ d_rem_code_phase_chips,1.0);
if (tempvalues3[i] < 0)
{
tempvalues3[i] = tempvalues3[i] + 1.0; // fmod operator does not work as in Matlab with negative numbers
}
d_initial_interp_counter[i] = (unsigned) floor(MAX_CODE_RESAMPLER_COUNTER * tempvalues3[i]);
}
}
void fpga_multicorrelator_8sc::fpga_configure_code_parameters_in_fpga(void)
{
int i;
for (i=0;i<d_n_correlators;i++)
{
d_map_base[1+i] = d_initial_index[i];
d_map_base[1 + d_n_correlators + i] = d_initial_interp_counter[i];
}
d_map_base[8] = d_code_length_chips - 1; // number of samples - 1
int i;
for (i = 0; i < d_n_correlators; i++)
{
d_map_base[1+i] = d_initial_index[i];
d_map_base[1 + d_n_correlators + i] = d_initial_interp_counter[i];
}
d_map_base[8] = d_code_length_chips - 1; // number of samples - 1
}
void fpga_multicorrelator_8sc::fpga_compute_signal_parameters_in_fpga(void)
{
float d_rem_carrier_phase_in_rad_temp;
float d_phase_step_rad_int_temp;
float d_rem_carrier_phase_in_rad_temp;
float d_phase_step_rad_int_temp;
d_code_phase_step_chips_num = (unsigned) roundf(MAX_CODE_RESAMPLER_COUNTER*d_code_phase_step_chips);
d_code_phase_step_chips_num = (unsigned) roundf(MAX_CODE_RESAMPLER_COUNTER * d_code_phase_step_chips);
if (d_rem_carrier_phase_in_rad > M_PI)
{
d_rem_carrier_phase_in_rad_temp = -2*M_PI + d_rem_carrier_phase_in_rad;
}
else if (d_rem_carrier_phase_in_rad < - M_PI)
{
d_rem_carrier_phase_in_rad_temp = 2*M_PI + d_rem_carrier_phase_in_rad;
}
else
{
d_rem_carrier_phase_in_rad_temp = d_rem_carrier_phase_in_rad;
}
if (d_rem_carrier_phase_in_rad > M_PI)
{
d_rem_carrier_phase_in_rad_temp = -2*M_PI + d_rem_carrier_phase_in_rad;
}
else if (d_rem_carrier_phase_in_rad < - M_PI)
{
d_rem_carrier_phase_in_rad_temp = 2*M_PI + d_rem_carrier_phase_in_rad;
}
else
{
d_rem_carrier_phase_in_rad_temp = d_rem_carrier_phase_in_rad;
}
d_rem_carr_phase_rad_int = (int) roundf((fabs(d_rem_carrier_phase_in_rad_temp)/M_PI)*pow(2, PHASE_CARR_NBITS_FRAC));
d_rem_carr_phase_rad_int = (int) roundf((fabs(d_rem_carrier_phase_in_rad_temp)/M_PI)*pow(2, PHASE_CARR_NBITS_FRAC));
if (d_rem_carrier_phase_in_rad_temp < 0)
{
d_rem_carr_phase_rad_int = -d_rem_carr_phase_rad_int;
}
d_phase_step_rad_int = (int) roundf((fabs(d_phase_step_rad)/M_PI)*pow(2, PHASE_CARR_NBITS_FRAC)); // the FPGA accepts a range for the phase step between -pi and +pi
if (d_phase_step_rad < 0)
{
d_phase_step_rad_int = -d_phase_step_rad_int;
}
if (d_rem_carrier_phase_in_rad_temp < 0)
{
d_rem_carr_phase_rad_int = -d_rem_carr_phase_rad_int;
}
d_phase_step_rad_int = (int) roundf((fabs(d_phase_step_rad)/M_PI)*pow(2, PHASE_CARR_NBITS_FRAC)); // the FPGA accepts a range for the phase step between -pi and +pi
if (d_phase_step_rad < 0)
{
d_phase_step_rad_int = -d_phase_step_rad_int;
}
}
void fpga_multicorrelator_8sc::fpga_configure_signal_parameters_in_fpga(void)
{
d_map_base[0] = d_code_phase_step_chips_num;
d_map_base[7] = d_correlator_length_samples - 1;
d_map_base[9] = d_rem_carr_phase_rad_int;
d_map_base[10] = d_phase_step_rad_int;
d_map_base[12] = 0; // lock the channel
d_map_base[13] = d_initial_sample_counter;
d_map_base[0] = d_code_phase_step_chips_num;
d_map_base[7] = d_correlator_length_samples - 1;
d_map_base[9] = d_rem_carr_phase_rad_int;
d_map_base[10] = d_phase_step_rad_int;
d_map_base[12] = 0; // lock the channel
d_map_base[13] = d_initial_sample_counter;
}
void fpga_multicorrelator_8sc::fpga_launch_multicorrelator_fpga(void)
{
// enable interrupts
int reenable = 1;
write(d_fd, (void *)&reenable, sizeof(int));
// enable interrupts
int reenable = 1;
write(d_fd, (void *)&reenable, sizeof(int));
d_map_base[14] = 0; // writing anything to reg 14 launches the tracking
d_map_base[14] = 0; // writing anything to reg 14 launches the tracking
}
void fpga_multicorrelator_8sc::read_tracking_gps_results(void)
{
int *readval_real;
int *readval_imag;
int k;
readval_real= new int[d_n_correlators];
readval_imag= new int[d_n_correlators];
int *readval_real;
int *readval_imag;
int k;
readval_real = new int[d_n_correlators];
readval_imag = new int[d_n_correlators];
for (k=0;k<d_n_correlators;k++)
{
readval_real[k] = d_map_base[1 + k];
if (readval_real[k] >= 1048576) // 0x100000 (21 bits two's complement)
{
readval_real[k] = -2097152 + readval_real[k];
}
readval_real[k] = readval_real[k]*2; // the results are shifted two bits to the left due to the complex multiplier in the FPGA
for (k =0 ; k < d_n_correlators; k++)
{
readval_real[k] = d_map_base[1 + k];
if (readval_real[k] >= 1048576) // 0x100000 (21 bits two's complement)
{
readval_real[k] = -2097152 + readval_real[k];
}
readval_real[k] = readval_real[k] * 2; // the results are shifted two bits to the left due to the complex multiplier in the FPGA
}
for (k=0;k<d_n_correlators;k++)
{
readval_imag[k] = d_map_base[1 + d_n_correlators + k];
if (readval_imag[k] >= 1048576) // 0x100000 (21 bits two's complement)
{
readval_imag[k] = -2097152 + readval_imag[k];
}
readval_imag[k] = readval_imag[k]*2; // the results are shifted two bits to the left due to the complex multiplier in the FPGA
}
}
for (k = 0; k < d_n_correlators; k++)
{
readval_imag[k] = d_map_base[1 + d_n_correlators + k];
if (readval_imag[k] >= 1048576) // 0x100000 (21 bits two's complement)
{
readval_imag[k] = -2097152 + readval_imag[k];
}
readval_imag[k] = readval_imag[k] * 2; // the results are shifted two bits to the left due to the complex multiplier in the FPGA
}
for (k=0;k<d_n_correlators;k++)
{
d_corr_out[k] = lv_cmake(readval_real[k], readval_imag[k]);
}
delete[] readval_real;
delete[] readval_imag;
for (k = 0; k < d_n_correlators; k++)
{
d_corr_out[k] = lv_cmake(readval_real[k], readval_imag[k]);
}
delete[] readval_real;
delete[] readval_imag;
}
void fpga_multicorrelator_8sc::unlock_channel(void)
{
// unlock the channel to let the next samples go through
d_map_base[12] = 1; // unlock the channel
// unlock the channel to let the next samples go through
d_map_base[12] = 1; // unlock the channel
}

12
src/algorithms/tracking/libs/fpga_multicorrelator_8sc.h
View File

@ -61,22 +61,20 @@ public:
void set_initial_sample(int samples_offset);
private:
const lv_16sc_t *d_local_code_in;
lv_16sc_t *d_corr_out;
float *d_shifts_chips;
int d_code_length_chips;
int d_n_correlators;
// data related to the hardware module and the driver
char d_device_io_name[MAX_LENGTH_DEVICEIO_NAME]; // driver io name
int d_fd; // driver descriptor
volatile unsigned *d_map_base; // driver memory map
char d_device_io_name[MAX_LENGTH_DEVICEIO_NAME]; // driver io name
int d_fd; // driver descriptor
volatile unsigned *d_map_base; // driver memory map
// configuration data received from the interface
unsigned int d_channel; // channel number
unsigned d_ncorrelators; // number of correlators
unsigned int d_channel; // channel number
unsigned d_ncorrelators; // number of correlators
unsigned d_correlator_length_samples;
float d_rem_code_phase_chips;
float d_code_phase_step_chips;

8
src/tests/CMakeLists.txt
View File

@ -130,12 +130,12 @@ if(OPENCL_FOUND)
add_definitions(-DOPENCL_BLOCKS_TEST=1)
endif(OPENCL_FOUND)
if (ENABLE_CUDA)
add_definitions(-DCUDA_BLOCKS_TEST=1)
if(ENABLE_CUDA)
add_definitions(-DCUDA_BLOCKS_TEST=1)
endif(ENABLE_CUDA)
if (ENABLE_FPGA)
add_definitions(-DFPGA_BLOCKS_TEST=1)
if(ENABLE_FPGA)
add_definitions(-DFPGA_BLOCKS_TEST=1)
endif(ENABLE_FPGA)
################################################################################

8
src/tests/test_main.cc
View File

@ -119,6 +119,10 @@ DECLARE_string(log_dir);
#include "unit-tests/signal-processing-blocks/tracking/gpu_multicorrelator_test.cc"
#endif
#if FPGA_BLOCKS_TEST
#include "unit-tests/signal-processing-blocks/tracking/gps_l1_ca_dll_pll_tracking_test_fpga.cc"
#endif
#include "unit-tests/signal-processing-blocks/pvt/rtcm_test.cc"
#include "unit-tests/signal-processing-blocks/pvt/rtcm_printer_test.cc"
#include "unit-tests/signal-processing-blocks/pvt/rinex_printer_test.cc"
@ -132,9 +136,7 @@ DECLARE_string(log_dir);
#endif
#endif
#if FPGA_BLOCKS_TEST
#include "unit-tests/signal-processing-blocks/tracking/gps_l1_ca_dll_pll_tracking_test_fpga.cc"
#endif
// For GPS NAVIGATION (L1)
concurrent_queue<Gps_Acq_Assist> global_gps_acq_assist_queue;

178
src/tests/unit-tests/signal-processing-blocks/tracking/gps_l1_ca_dll_pll_tracking_test_fpga.cc
View File

@ -36,9 +36,9 @@
#include <iostream>
#include <unistd.h>
#include <armadillo>
#include <boost/thread.hpp> // to test the FPGA we have to create a simultaneous task to send the samples using the DMA and stop the test
#include <boost/thread.hpp>// to test the FPGA we have to create a simultaneous task to send the samples using the DMA and stop the test
#include <boost/chrono.hpp> // temporary for debugging
#include <stdio.h> // FPGA read input file
#include <stdio.h>// FPGA read input file
#include <gnuradio/top_block.h>
#include <gnuradio/blocks/file_source.h>
#include <gnuradio/analog/sig_source_waveform.h>
@ -68,111 +68,107 @@
#define MAX_INPUT_SAMPLES_TOTAL MAX_INPUT_SAMPLES_PER_TEST_CASE*MAX_NUM_TEST_CASES
#define DMA_TRANSFER_SIZE 2046
#define MIN_SAMPLES_REMAINING 20000 // number of remaining samples in the DMA that causes the CPU to stop the flowgraph (it has to be a bit alrger than 2x max packet size)
void wait(int seconds)
{
boost::this_thread::sleep_for(boost::chrono::seconds{seconds});
boost::this_thread::sleep_for(boost::chrono::seconds{seconds});
}
void send_tracking_gps_input_samples(FILE *ptr_myfile, int num_remaining_samples, gr::top_block_sptr top_block)
{
int sample_pointer;
int num_samples_transferred = 0;
static int flowgraph_stopped = 0;
int sample_pointer;
int num_samples_transferred = 0;
static int flowgraph_stopped = 0;
char *buffer;
char *buffer;
// DMA descriptor
int tx_fd;
tx_fd = open("/dev/loop_tx", O_WRONLY);
if ( tx_fd < 0 )
{
printf("can't open loop device\n");
exit(1);
}
// DMA descriptor
int tx_fd;
tx_fd = open("/dev/loop_tx", O_WRONLY);
if ( tx_fd < 0 )
{
printf("can't open loop device\n");
exit(1);
}
buffer=(char *)malloc(DMA_TRANSFER_SIZE);
if (!buffer)
{
fprintf(stderr, "Memory error!");
}
buffer = (char *)malloc(DMA_TRANSFER_SIZE);
if (!buffer)
{
fprintf(stderr, "Memory error!");
}
while(num_remaining_samples > 0)
{
if (num_remaining_samples < MIN_SAMPLES_REMAINING)
{
if (flowgraph_stopped == 0)
{
// stop top module
top_block->stop();
flowgraph_stopped = 1;
}
}
if (num_remaining_samples > DMA_TRANSFER_SIZE)
{
while(num_remaining_samples >0)
{
if (num_remaining_samples < MIN_SAMPLES_REMAINING)
{
if (flowgraph_stopped == 0)
{
// stop top module
top_block->stop();
flowgraph_stopped = 1;
}
}
if (num_remaining_samples > DMA_TRANSFER_SIZE)
{
fread(buffer, DMA_TRANSFER_SIZE, 1, ptr_myfile);
fread(buffer, DMA_TRANSFER_SIZE, 1, ptr_myfile);
assert( DMA_TRANSFER_SIZE == write(tx_fd, &buffer[0], DMA_TRANSFER_SIZE) );
num_remaining_samples = num_remaining_samples - DMA_TRANSFER_SIZE;
num_samples_transferred = num_samples_transferred + DMA_TRANSFER_SIZE;
}
else
{
fread(buffer, num_remaining_samples, 1, ptr_myfile);
assert( DMA_TRANSFER_SIZE == write(tx_fd, &buffer[0], DMA_TRANSFER_SIZE) );
num_remaining_samples = num_remaining_samples - DMA_TRANSFER_SIZE;
num_samples_transferred = num_samples_transferred + DMA_TRANSFER_SIZE;
}
else
{
fread(buffer, num_remaining_samples, 1, ptr_myfile);
assert( num_remaining_samples == write(tx_fd, &buffer[0], num_remaining_samples) );
num_samples_transferred = num_samples_transferred + num_remaining_samples;
num_remaining_samples = 0;
}
}
free(buffer);
close(tx_fd);
assert( num_remaining_samples == write(tx_fd, &buffer[0], num_remaining_samples) );
num_samples_transferred = num_samples_transferred + num_remaining_samples;
num_remaining_samples = 0;
}
}
free(buffer);
close(tx_fd);
}
// thread that sends the samples to the FPGA
void thread(gr::top_block_sptr top_block, const char * file_name)
{
// file descriptor
FILE *ptr_myfile;
int fileLen;
// file descriptor
FILE *ptr_myfile;
int fileLen;
ptr_myfile = fopen(file_name,"rb");
if (!ptr_myfile)
{
printf("Unable to open file!");
}
ptr_myfile=fopen(file_name,"rb");
if (!ptr_myfile)
{
printf("Unable to open file!");
}
fseek(ptr_myfile, 0, SEEK_END);
fileLen = ftell(ptr_myfile);
fseek(ptr_myfile, 0, SEEK_SET);
fseek(ptr_myfile, 0, SEEK_END);
fileLen=ftell(ptr_myfile);
fseek(ptr_myfile, 0, SEEK_SET);
wait(20); // wait for some time to give time to the other thread to program the device
wait(20); // wait for some time to give time to the other thread to program the device
//send_tracking_gps_input_samples(tx_fd, ptr_myfile, fileLen);
send_tracking_gps_input_samples(ptr_myfile, fileLen, top_block);
fclose(ptr_myfile);
//send_tracking_gps_input_samples(tx_fd, ptr_myfile, fileLen);
send_tracking_gps_input_samples(ptr_myfile, fileLen, top_block);
fclose(ptr_myfile);
}
// ######## GNURADIO BLOCK MESSAGE RECEVER #########
class GpsL1CADllPllTrackingTestFpga_msg_rx;
typedef boost::shared_ptr<GpsL1CADllPllTrackingTestFpga_msg_rx> GpsL1CADllPllTrackingTestFpga_msg_rx_sptr;
GpsL1CADllPllTrackingTestFpga_msg_rx_sptr GpsL1CADllPllTrackingTestFpga_msg_rx_make();
class GpsL1CADllPllTrackingTestFpga_msg_rx : public gr::block
{
private:
@ -185,11 +181,13 @@ public:
~GpsL1CADllPllTrackingTestFpga_msg_rx(); //!< Default destructor
};
GpsL1CADllPllTrackingTestFpga_msg_rx_sptr GpsL1CADllPllTrackingTestFpga_msg_rx_make()
{
return GpsL1CADllPllTrackingTestFpga_msg_rx_sptr(new GpsL1CADllPllTrackingTestFpga_msg_rx());
}
void GpsL1CADllPllTrackingTestFpga_msg_rx::msg_handler_events(pmt::pmt_t msg)
{
try
@ -204,24 +202,24 @@ void GpsL1CADllPllTrackingTestFpga_msg_rx::msg_handler_events(pmt::pmt_t msg)
}
}
GpsL1CADllPllTrackingTestFpga_msg_rx::GpsL1CADllPllTrackingTestFpga_msg_rx() :
gr::block("GpsL1CADllPllTrackingTestFpga_msg_rx", gr::io_signature::make(0, 0, 0), gr::io_signature::make(0, 0, 0))
gr::block("GpsL1CADllPllTrackingTestFpga_msg_rx", gr::io_signature::make(0, 0, 0), gr::io_signature::make(0, 0, 0))
{
this->message_port_register_in(pmt::mp("events"));
this->set_msg_handler(pmt::mp("events"), boost::bind(&GpsL1CADllPllTrackingTestFpga_msg_rx::msg_handler_events, this, _1));
rx_message = 0;
}
GpsL1CADllPllTrackingTestFpga_msg_rx::~GpsL1CADllPllTrackingTestFpga_msg_rx()
{}
// ###########################################################
class GpsL1CADllPllTrackingTestFpga: public ::testing::Test
{
public:
std::string generator_binary;
std::string p1;
@ -335,13 +333,13 @@ void GpsL1CADllPllTrackingTestFpga::configure_receiver()
config->set_property("Tracking_1C.early_late_space_chips", "0.5");
}
void GpsL1CADllPllTrackingTestFpga::check_results_doppler(arma::vec true_time_s,
arma::vec true_value,
arma::vec meas_time_s,
arma::vec meas_value)
{
//1. True value interpolation to match the measurement times
arma::vec true_value_interp;
arma::interp1(true_time_s, true_value, meas_time_s, true_value_interp);
@ -361,20 +359,18 @@ void GpsL1CADllPllTrackingTestFpga::check_results_doppler(arma::vec true_time_s,
double min_error = arma::min(err);
//5. report
std::cout << std::setprecision(10) << "TRK Doppler RMSE=" << rmse
<< ", mean=" << error_mean
<< ", stdev="<< sqrt(error_var) << " (max,min)=" << max_error << "," << min_error << " [Hz]" << std::endl;
}
void GpsL1CADllPllTrackingTestFpga::check_results_acc_carrier_phase(arma::vec true_time_s,
arma::vec true_value,
arma::vec meas_time_s,
arma::vec meas_value)
{
//1. True value interpolation to match the measurement times
arma::vec true_value_interp;
arma::interp1(true_time_s, true_value, meas_time_s, true_value_interp);
@ -394,26 +390,24 @@ void GpsL1CADllPllTrackingTestFpga::check_results_acc_carrier_phase(arma::vec tr
double min_error = arma::min(err);
//5. report
std::cout << std::setprecision(10) << "TRK acc carrier phase RMSE=" << rmse
<< ", mean=" << error_mean
<< ", stdev=" << sqrt(error_var) << " (max,min)=" << max_error << "," << min_error << " [Hz]" << std::endl;
}
void GpsL1CADllPllTrackingTestFpga::check_results_codephase(arma::vec true_time_s,
arma::vec true_value,
arma::vec meas_time_s,
arma::vec meas_value)
{
//1. True value interpolation to match the measurement times
arma::vec true_value_interp;
arma::interp1(true_time_s, true_value, meas_time_s, true_value_interp);
//2. RMSE
arma::vec err;
err = meas_value - true_value_interp;
arma::vec err2 = arma::square(err);
double rmse = sqrt(arma::mean(err2));
@ -427,16 +421,14 @@ void GpsL1CADllPllTrackingTestFpga::check_results_codephase(arma::vec true_time_
double min_error = arma::min(err);
//5. report
std::cout << std::setprecision(10) << "TRK code phase RMSE=" << rmse
<< ", mean=" << error_mean
<< ", stdev=" << sqrt(error_var) << " (max,min)=" << max_error << "," << min_error << " [Chips]" << std::endl;
}
TEST_F(GpsL1CADllPllTrackingTestFpga, ValidationOfResultsFpga)
{
configure_generator();
// DO not generate signal raw signal samples and observations RINEX file by default
@ -478,46 +470,38 @@ TEST_F(GpsL1CADllPllTrackingTestFpga, ValidationOfResultsFpga)
//restart the epoch counter
true_obs_data.restart();
std::cout << "Initial Doppler [Hz]=" << true_obs_data.doppler_l1_hz << " Initial code delay [Chips]=" << true_obs_data.prn_delay_chips << std::endl;
gnss_synchro.Acq_delay_samples = (GPS_L1_CA_CODE_LENGTH_CHIPS - true_obs_data.prn_delay_chips / GPS_L1_CA_CODE_LENGTH_CHIPS) * baseband_sampling_freq * GPS_L1_CA_CODE_PERIOD;
gnss_synchro.Acq_doppler_hz = true_obs_data.doppler_l1_hz;
gnss_synchro.Acq_samplestamp_samples = 0;
ASSERT_NO_THROW( {
tracking->set_channel(gnss_synchro.Channel_ID);
}) << "Failure setting channel." << std::endl;
ASSERT_NO_THROW( {
tracking->set_gnss_synchro(&gnss_synchro);
}) << "Failure setting gnss_synchro." << std::endl;
ASSERT_NO_THROW( {
tracking->connect(top_block);
}) << "Failure connecting tracking to the top_block." << std::endl;
ASSERT_NO_THROW( {
gr::blocks::null_sink::sptr sink = gr::blocks::null_sink::make(sizeof(Gnss_Synchro));
top_block->connect(tracking->get_right_block(), 0, sink, 0);
top_block->msg_connect(tracking->get_right_block(), pmt::mp("events"), msg_rx, pmt::mp("events"));
}) << "Failure connecting the blocks of tracking test." << std::endl;
tracking->start_tracking();
// assemble again the file name in a null terminated string (not available by default in the main program flow)
std::string file = "./" + filename_raw_data;
const char * file_name = file.c_str();
// start thread that sends the DMA samples to the FPGA
boost::thread t{thread, top_block, file_name};
EXPECT_NO_THROW( {
gettimeofday(&tv, NULL);
begin = tv.tv_sec * 1000000 + tv.tv_usec;
@ -530,9 +514,6 @@ TEST_F(GpsL1CADllPllTrackingTestFpga, ValidationOfResultsFpga)
// wait until child thread terminates
t.join();
//check results
//load the true values
long int nepoch = true_obs_data.num_epochs();
@ -602,4 +583,3 @@ TEST_F(GpsL1CADllPllTrackingTestFpga, ValidationOfResultsFpga)
std::cout << "Signal tracking completed in " << (end - begin) << " microseconds" << std::endl;
}