mirror of
https://github.com/gnss-sdr/gnss-sdr
synced 2024-07-02 01:43:20 +00:00
neon hook
This commit is contained in:
Carles Fernandez
parent
e400885800
commit
e66ac2f476
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@ -51,24 +51,24 @@
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*/
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static inline void volk_gnsssdr_16ic_x2_rotator_dot_prod_16ic_xn_generic(lv_16sc_t* result, const lv_16sc_t* in_common, const lv_32fc_t phase_inc, lv_32fc_t* phase, const lv_16sc_t** in_a, int num_a_vectors, unsigned int num_points)
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{
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lv_16sc_t tmp16;
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lv_32fc_t tmp32;
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for (int n_vec = 0; n_vec < num_a_vectors; n_vec++)
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{
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result[n_vec] = lv_cmake(0,0);
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}
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for (unsigned int n = 0; n < num_points; n++)
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{
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tmp16 = *in_common++;
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tmp32 = lv_cmake((float)lv_creal(tmp16), (float)lv_cimag(tmp16)) * (*phase);
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tmp16 = lv_cmake((int16_t)rintf(lv_creal(tmp32)), (int16_t)rintf(lv_cimag(tmp32)));
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(*phase) *= phase_inc;
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for (int n_vec = 0; n_vec < num_a_vectors; n_vec++)
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{
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lv_16sc_t tmp = tmp16 * in_a[n_vec][n];
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result[n_vec] = lv_cmake(sat_adds16i(lv_creal(result[n_vec]), lv_creal(tmp)), sat_adds16i(lv_cimag(result[n_vec]), lv_cimag(tmp)));
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}
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}
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lv_16sc_t tmp16;
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lv_32fc_t tmp32;
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for (int n_vec = 0; n_vec < num_a_vectors; n_vec++)
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{
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result[n_vec] = lv_cmake(0,0);
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}
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for (unsigned int n = 0; n < num_points; n++)
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{
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tmp16 = *in_common++;
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tmp32 = lv_cmake((float)lv_creal(tmp16), (float)lv_cimag(tmp16)) * (*phase);
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tmp16 = lv_cmake((int16_t)rintf(lv_creal(tmp32)), (int16_t)rintf(lv_cimag(tmp32)));
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(*phase) *= phase_inc;
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for (int n_vec = 0; n_vec < num_a_vectors; n_vec++)
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{
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lv_16sc_t tmp = tmp16 * in_a[n_vec][n];
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result[n_vec] = lv_cmake(sat_adds16i(lv_creal(result[n_vec]), lv_creal(tmp)), sat_adds16i(lv_cimag(result[n_vec]), lv_cimag(tmp)));
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}
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}
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}
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#endif /*LV_HAVE_GENERIC*/
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@ -87,150 +87,149 @@ static inline void volk_gnsssdr_16ic_x2_rotator_dot_prod_16ic_xn_generic(lv_16sc
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*/
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static inline void volk_gnsssdr_16ic_x2_rotator_dot_prod_16ic_xn_a_sse3(lv_16sc_t* out, const lv_16sc_t* in_common, const lv_32fc_t phase_inc, lv_32fc_t* phase, const lv_16sc_t** in_a, int num_a_vectors, unsigned int num_points)
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{
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lv_16sc_t dotProduct = lv_cmake(0,0);
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lv_16sc_t dotProduct = lv_cmake(0,0);
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const unsigned int sse_iters = num_points / 4;
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const unsigned int sse_iters = num_points / 4;
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const lv_16sc_t** _in_a = in_a;
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const lv_16sc_t* _in_common = in_common;
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lv_16sc_t* _out = out;
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const lv_16sc_t** _in_a = in_a;
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const lv_16sc_t* _in_common = in_common;
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lv_16sc_t* _out = out;
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__VOLK_ATTR_ALIGNED(16) lv_16sc_t dotProductVector[4];
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__VOLK_ATTR_ALIGNED(16) lv_16sc_t dotProductVector[4];
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//todo dyn mem reg
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//todo dyn mem reg
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__m128i* realcacc;
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__m128i* imagcacc;
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__m128i* realcacc;
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__m128i* imagcacc;
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realcacc = (__m128i*)calloc(num_a_vectors, sizeof(__m128i)); //calloc also sets memory to 0
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imagcacc = (__m128i*)calloc(num_a_vectors, sizeof(__m128i)); //calloc also sets memory to 0
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realcacc = (__m128i*)calloc(num_a_vectors, sizeof(__m128i)); //calloc also sets memory to 0
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imagcacc = (__m128i*)calloc(num_a_vectors, sizeof(__m128i)); //calloc also sets memory to 0
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__m128i a,b,c, c_sr, mask_imag, mask_real, real, imag, imag1,imag2, b_sl, a_sl, result;
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__m128i a,b,c, c_sr, mask_imag, mask_real, real, imag, imag1,imag2, b_sl, a_sl, result;
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mask_imag = _mm_set_epi8(255, 255, 0, 0, 255, 255, 0, 0, 255, 255, 0, 0, 255, 255, 0, 0);
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mask_real = _mm_set_epi8(0, 0, 255, 255, 0, 0, 255, 255, 0, 0, 255, 255, 0, 0, 255, 255);
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mask_imag = _mm_set_epi8(255, 255, 0, 0, 255, 255, 0, 0, 255, 255, 0, 0, 255, 255, 0, 0);
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mask_real = _mm_set_epi8(0, 0, 255, 255, 0, 0, 255, 255, 0, 0, 255, 255, 0, 0, 255, 255);
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// phase rotation registers
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__m128 pa, pb, two_phase_acc_reg, two_phase_inc_reg;
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__m128i pc1, pc2;
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__attribute__((aligned(16))) lv_32fc_t two_phase_inc[2];
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two_phase_inc[0] = phase_inc * phase_inc;
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two_phase_inc[1] = phase_inc * phase_inc;
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two_phase_inc_reg = _mm_load_ps((float*) two_phase_inc);
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__attribute__((aligned(16))) lv_32fc_t two_phase_acc[2];
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two_phase_acc[0] = (*phase);
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two_phase_acc[1] = (*phase) * phase_inc;
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two_phase_acc_reg = _mm_load_ps((float*)two_phase_acc);
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__m128 yl, yh, tmp1, tmp2, tmp3;
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lv_16sc_t tmp16;
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lv_32fc_t tmp32;
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// phase rotation registers
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__m128 pa, pb, two_phase_acc_reg, two_phase_inc_reg;
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__m128i pc1, pc2;
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__attribute__((aligned(16))) lv_32fc_t two_phase_inc[2];
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two_phase_inc[0] = phase_inc * phase_inc;
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two_phase_inc[1] = phase_inc * phase_inc;
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two_phase_inc_reg = _mm_load_ps((float*) two_phase_inc);
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__attribute__((aligned(16))) lv_32fc_t two_phase_acc[2];
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two_phase_acc[0] = (*phase);
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two_phase_acc[1] = (*phase) * phase_inc;
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two_phase_acc_reg = _mm_load_ps((float*)two_phase_acc);
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__m128 yl, yh, tmp1, tmp2, tmp3;
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lv_16sc_t tmp16;
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lv_32fc_t tmp32;
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for(unsigned int number = 0; number < sse_iters; number++)
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{
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// Phase rotation on operand in_common starts here:
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for(unsigned int number = 0; number < sse_iters; number++)
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{
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// Phase rotation on operand in_common starts here:
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pa = _mm_set_ps((float)(lv_cimag(_in_common[1])), (float)(lv_creal(_in_common[1])), (float)(lv_cimag(_in_common[0])), (float)(lv_creal(_in_common[0]))); // //load (2 byte imag, 2 byte real) x 2 into 128 bits reg
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//complex 32fc multiplication b=a*two_phase_acc_reg
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yl = _mm_moveldup_ps(two_phase_acc_reg); // Load yl with cr,cr,dr,dr
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yh = _mm_movehdup_ps(two_phase_acc_reg); // Load yh with ci,ci,di,di
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tmp1 = _mm_mul_ps(pa, yl); // tmp1 = ar*cr,ai*cr,br*dr,bi*dr
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pa = _mm_shuffle_ps(pa, pa, 0xB1); // Re-arrange x to be ai,ar,bi,br
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tmp2 = _mm_mul_ps(pa, yh); // tmp2 = ai*ci,ar*ci,bi*di,br*di
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pb = _mm_addsub_ps(tmp1, tmp2); // ar*cr-ai*ci, ai*cr+ar*ci, br*dr-bi*di, bi*dr+br*di
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pc1 = _mm_cvtps_epi32(pb); // convert from 32fc to 32ic
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pa = _mm_set_ps((float)(lv_cimag(_in_common[1])), (float)(lv_creal(_in_common[1])), (float)(lv_cimag(_in_common[0])), (float)(lv_creal(_in_common[0]))); // //load (2 byte imag, 2 byte real) x 2 into 128 bits reg
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//complex 32fc multiplication b=a*two_phase_acc_reg
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yl = _mm_moveldup_ps(two_phase_acc_reg); // Load yl with cr,cr,dr,dr
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yh = _mm_movehdup_ps(two_phase_acc_reg); // Load yh with ci,ci,di,di
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tmp1 = _mm_mul_ps(pa, yl); // tmp1 = ar*cr,ai*cr,br*dr,bi*dr
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pa = _mm_shuffle_ps(pa, pa, 0xB1); // Re-arrange x to be ai,ar,bi,br
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tmp2 = _mm_mul_ps(pa, yh); // tmp2 = ai*ci,ar*ci,bi*di,br*di
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pb = _mm_addsub_ps(tmp1, tmp2); // ar*cr-ai*ci, ai*cr+ar*ci, br*dr-bi*di, bi*dr+br*di
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pc1 = _mm_cvtps_epi32(pb); // convert from 32fc to 32ic
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//complex 32fc multiplication two_phase_acc_reg=two_phase_acc_reg*two_phase_inc_reg
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yl = _mm_moveldup_ps(two_phase_acc_reg); // Load yl with cr,cr,dr,dr
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yh = _mm_movehdup_ps(two_phase_acc_reg); // Load yh with ci,ci,di,di
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tmp1 = _mm_mul_ps(two_phase_inc_reg, yl); // tmp1 = ar*cr,ai*cr,br*dr,bi*dr
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tmp3 = _mm_shuffle_ps(two_phase_inc_reg, two_phase_inc_reg, 0xB1); // Re-arrange x to be ai,ar,bi,br
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tmp2 = _mm_mul_ps(tmp3, yh); // tmp2 = ai*ci,ar*ci,bi*di,br*di
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two_phase_acc_reg = _mm_addsub_ps(tmp1, tmp2); // ar*cr-ai*ci, ai*cr+ar*ci, br*dr-bi*di, bi*dr+br*di
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//complex 32fc multiplication two_phase_acc_reg=two_phase_acc_reg*two_phase_inc_reg
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yl = _mm_moveldup_ps(two_phase_acc_reg); // Load yl with cr,cr,dr,dr
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yh = _mm_movehdup_ps(two_phase_acc_reg); // Load yh with ci,ci,di,di
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tmp1 = _mm_mul_ps(two_phase_inc_reg, yl); // tmp1 = ar*cr,ai*cr,br*dr,bi*dr
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tmp3 = _mm_shuffle_ps(two_phase_inc_reg, two_phase_inc_reg, 0xB1); // Re-arrange x to be ai,ar,bi,br
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tmp2 = _mm_mul_ps(tmp3, yh); // tmp2 = ai*ci,ar*ci,bi*di,br*di
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two_phase_acc_reg = _mm_addsub_ps(tmp1, tmp2); // ar*cr-ai*ci, ai*cr+ar*ci, br*dr-bi*di, bi*dr+br*di
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//next two samples
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_in_common += 2;
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pa = _mm_set_ps((float)(lv_cimag(_in_common[1])), (float)(lv_creal(_in_common[1])), (float)(lv_cimag(_in_common[0])), (float)(lv_creal(_in_common[0]))); // //load (2 byte imag, 2 byte real) x 2 into 128 bits reg
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//complex 32fc multiplication b=a*two_phase_acc_reg
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yl = _mm_moveldup_ps(two_phase_acc_reg); // Load yl with cr,cr,dr,dr
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yh = _mm_movehdup_ps(two_phase_acc_reg); // Load yh with ci,ci,di,di
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tmp1 = _mm_mul_ps(pa, yl); // tmp1 = ar*cr,ai*cr,br*dr,bi*dr
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pa = _mm_shuffle_ps(pa, pa, 0xB1); // Re-arrange x to be ai,ar,bi,br
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tmp2 = _mm_mul_ps(pa, yh); // tmp2 = ai*ci,ar*ci,bi*di,br*di
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pb = _mm_addsub_ps(tmp1, tmp2); // ar*cr-ai*ci, ai*cr+ar*ci, br*dr-bi*di, bi*dr+br*di
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pc2 = _mm_cvtps_epi32(pb); // convert from 32fc to 32ic
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//next two samples
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_in_common += 2;
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pa = _mm_set_ps((float)(lv_cimag(_in_common[1])), (float)(lv_creal(_in_common[1])), (float)(lv_cimag(_in_common[0])), (float)(lv_creal(_in_common[0]))); // //load (2 byte imag, 2 byte real) x 2 into 128 bits reg
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//complex 32fc multiplication b=a*two_phase_acc_reg
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yl = _mm_moveldup_ps(two_phase_acc_reg); // Load yl with cr,cr,dr,dr
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yh = _mm_movehdup_ps(two_phase_acc_reg); // Load yh with ci,ci,di,di
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tmp1 = _mm_mul_ps(pa, yl); // tmp1 = ar*cr,ai*cr,br*dr,bi*dr
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pa = _mm_shuffle_ps(pa, pa, 0xB1); // Re-arrange x to be ai,ar,bi,br
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tmp2 = _mm_mul_ps(pa, yh); // tmp2 = ai*ci,ar*ci,bi*di,br*di
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pb = _mm_addsub_ps(tmp1, tmp2); // ar*cr-ai*ci, ai*cr+ar*ci, br*dr-bi*di, bi*dr+br*di
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pc2 = _mm_cvtps_epi32(pb); // convert from 32fc to 32ic
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//complex 32fc multiplication two_phase_acc_reg=two_phase_acc_reg*two_phase_inc_reg
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yl = _mm_moveldup_ps(two_phase_acc_reg); // Load yl with cr,cr,dr,dr
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yh = _mm_movehdup_ps(two_phase_acc_reg); // Load yh with ci,ci,di,di
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tmp1 = _mm_mul_ps(two_phase_inc_reg, yl); // tmp1 = ar*cr,ai*cr,br*dr,bi*dr
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tmp3 = _mm_shuffle_ps(two_phase_inc_reg, two_phase_inc_reg, 0xB1); // Re-arrange x to be ai,ar,bi,br
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tmp2 = _mm_mul_ps(tmp3, yh); // tmp2 = ai*ci,ar*ci,bi*di,br*di
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two_phase_acc_reg = _mm_addsub_ps(tmp1, tmp2); // ar*cr-ai*ci, ai*cr+ar*ci, br*dr-bi*di, bi*dr+br*di
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//complex 32fc multiplication two_phase_acc_reg=two_phase_acc_reg*two_phase_inc_reg
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yl = _mm_moveldup_ps(two_phase_acc_reg); // Load yl with cr,cr,dr,dr
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yh = _mm_movehdup_ps(two_phase_acc_reg); // Load yh with ci,ci,di,di
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tmp1 = _mm_mul_ps(two_phase_inc_reg, yl); // tmp1 = ar*cr,ai*cr,br*dr,bi*dr
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tmp3 = _mm_shuffle_ps(two_phase_inc_reg, two_phase_inc_reg, 0xB1); // Re-arrange x to be ai,ar,bi,br
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tmp2 = _mm_mul_ps(tmp3, yh); // tmp2 = ai*ci,ar*ci,bi*di,br*di
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two_phase_acc_reg = _mm_addsub_ps(tmp1, tmp2); // ar*cr-ai*ci, ai*cr+ar*ci, br*dr-bi*di, bi*dr+br*di
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// store four rotated in_common samples in the register b
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b = _mm_packs_epi32(pc1, pc2);// convert from 32ic to 16ic
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// store four rotated in_common samples in the register b
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b = _mm_packs_epi32(pc1, pc2);// convert from 32ic to 16ic
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//next two samples
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_in_common += 2;
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//next two samples
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_in_common += 2;
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for (int n_vec = 0; n_vec < num_a_vectors; n_vec++)
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{
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a = _mm_load_si128((__m128i*)&(_in_a[n_vec][number*4])); //load (2 byte imag, 2 byte real) x 4 into 128 bits reg
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for (int n_vec = 0; n_vec < num_a_vectors; n_vec++)
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{
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a = _mm_load_si128((__m128i*)&(_in_a[n_vec][number*4])); //load (2 byte imag, 2 byte real) x 4 into 128 bits reg
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c = _mm_mullo_epi16 (a, b); // a3.i*b3.i, a3.r*b3.r, ....
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c = _mm_mullo_epi16(a, b); // a3.i*b3.i, a3.r*b3.r, ....
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c_sr = _mm_srli_si128 (c, 2); // Shift a right by imm8 bytes while shifting in zeros, and store the results in dst.
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real = _mm_subs_epi16 (c, c_sr);
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c_sr = _mm_srli_si128(c, 2); // Shift a right by imm8 bytes while shifting in zeros, and store the results in dst.
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real = _mm_subs_epi16(c, c_sr);
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b_sl = _mm_slli_si128(b, 2); // b3.r, b2.i ....
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a_sl = _mm_slli_si128(a, 2); // a3.r, a2.i ....
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b_sl = _mm_slli_si128(b, 2); // b3.r, b2.i ....
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a_sl = _mm_slli_si128(a, 2); // a3.r, a2.i ....
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imag1 = _mm_mullo_epi16(a, b_sl); // a3.i*b3.r, ....
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imag2 = _mm_mullo_epi16(b, a_sl); // b3.i*a3.r, ....
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imag1 = _mm_mullo_epi16(a, b_sl); // a3.i*b3.r, ....
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imag2 = _mm_mullo_epi16(b, a_sl); // b3.i*a3.r, ....
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imag = _mm_adds_epi16(imag1, imag2);
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imag = _mm_adds_epi16(imag1, imag2);
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realcacc[n_vec] = _mm_adds_epi16 (realcacc[n_vec], real);
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imagcacc[n_vec] = _mm_adds_epi16 (imagcacc[n_vec], imag);
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realcacc[n_vec] = _mm_adds_epi16 (realcacc[n_vec], real);
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imagcacc[n_vec] = _mm_adds_epi16 (imagcacc[n_vec], imag);
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}
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}
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}
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}
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for (int n_vec = 0; n_vec < num_a_vectors; n_vec++)
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{
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realcacc[n_vec] = _mm_and_si128(realcacc[n_vec], mask_real);
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imagcacc[n_vec] = _mm_and_si128(imagcacc[n_vec], mask_imag);
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for (int n_vec=0;n_vec<num_a_vectors;n_vec++)
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{
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realcacc[n_vec] = _mm_and_si128 (realcacc[n_vec], mask_real);
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imagcacc[n_vec] = _mm_and_si128 (imagcacc[n_vec], mask_imag);
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result = _mm_or_si128(realcacc[n_vec], imagcacc[n_vec]);
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result = _mm_or_si128 (realcacc[n_vec], imagcacc[n_vec]);
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_mm_store_si128((__m128i*)dotProductVector, result); // Store the results back into the dot product vector
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dotProduct = lv_cmake(0,0);
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for (int i = 0; i < 4; ++i)
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{
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dotProduct = lv_cmake(sat_adds16i(lv_creal(dotProduct), lv_creal(dotProductVector[i])),
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sat_adds16i(lv_cimag(dotProduct), lv_cimag(dotProductVector[i])));
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}
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_out[n_vec] = dotProduct;
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}
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free(realcacc);
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free(imagcacc);
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_mm_store_si128((__m128i*)dotProductVector, result); // Store the results back into the dot product vector
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dotProduct = lv_cmake(0,0);
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for (int i = 0; i<4; ++i)
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{
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dotProduct = lv_cmake(sat_adds16i(lv_creal(dotProduct), lv_creal(dotProductVector[i])),
|
||||
sat_adds16i(lv_cimag(dotProduct), lv_cimag(dotProductVector[i])));
|
||||
}
|
||||
_out[n_vec] = dotProduct;
|
||||
}
|
||||
free(realcacc);
|
||||
free(imagcacc);
|
||||
_mm_store_ps((float*)two_phase_acc, two_phase_acc_reg);
|
||||
(*phase) = lv_cmake(two_phase_acc[0], two_phase_acc[0]);
|
||||
|
||||
_mm_store_ps((float*)two_phase_acc, two_phase_acc_reg);
|
||||
(*phase) = lv_cmake(two_phase_acc[0], two_phase_acc[0]);
|
||||
|
||||
for (int n_vec = 0; n_vec < num_a_vectors; n_vec++)
|
||||
{
|
||||
for(unsigned int n = sse_iters * 4; n < num_points; n++)
|
||||
{
|
||||
tmp16 = *in_common++;
|
||||
tmp32 = lv_cmake((float)lv_creal(tmp16), (float)lv_cimag(tmp16)) * (*phase);
|
||||
tmp16 = lv_cmake((int16_t)rintf(lv_creal(tmp32)), (int16_t)rintf(lv_cimag(tmp32)));
|
||||
(*phase) *= phase_inc;
|
||||
lv_16sc_t tmp = tmp16 * in_a[n_vec][n];
|
||||
_out[n_vec] = lv_cmake(sat_adds16i(lv_creal(_out[n_vec]), lv_creal(tmp)),
|
||||
sat_adds16i(lv_cimag(_out[n_vec]), lv_cimag(tmp)));
|
||||
}
|
||||
}
|
||||
for (int n_vec = 0; n_vec < num_a_vectors; n_vec++)
|
||||
{
|
||||
for(unsigned int n = sse_iters * 4; n < num_points; n++)
|
||||
{
|
||||
tmp16 = *in_common++;
|
||||
tmp32 = lv_cmake((float)lv_creal(tmp16), (float)lv_cimag(tmp16)) * (*phase);
|
||||
tmp16 = lv_cmake((int16_t)rintf(lv_creal(tmp32)), (int16_t)rintf(lv_cimag(tmp32)));
|
||||
(*phase) *= phase_inc;
|
||||
lv_16sc_t tmp = tmp16 * in_a[n_vec][n];
|
||||
_out[n_vec] = lv_cmake(sat_adds16i(lv_creal(_out[n_vec]), lv_creal(tmp)),
|
||||
sat_adds16i(lv_cimag(_out[n_vec]), lv_cimag(tmp)));
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
#endif /* LV_HAVE_SSE3 */
|
||||
|
|
@ -248,151 +247,312 @@ static inline void volk_gnsssdr_16ic_x2_rotator_dot_prod_16ic_xn_a_sse3(lv_16sc_
|
|||
*/
|
||||
static inline void volk_gnsssdr_16ic_x2_rotator_dot_prod_16ic_xn_u_sse3(lv_16sc_t* out, const lv_16sc_t* in_common, const lv_32fc_t phase_inc, lv_32fc_t* phase, const lv_16sc_t** in_a, int num_a_vectors, unsigned int num_points)
|
||||
{
|
||||
lv_16sc_t dotProduct = lv_cmake(0,0);
|
||||
lv_16sc_t dotProduct = lv_cmake(0,0);
|
||||
|
||||
const unsigned int sse_iters = num_points / 4;
|
||||
const unsigned int sse_iters = num_points / 4;
|
||||
|
||||
const lv_16sc_t** _in_a = in_a;
|
||||
const lv_16sc_t* _in_common = in_common;
|
||||
lv_16sc_t* _out = out;
|
||||
const lv_16sc_t** _in_a = in_a;
|
||||
const lv_16sc_t* _in_common = in_common;
|
||||
lv_16sc_t* _out = out;
|
||||
|
||||
__VOLK_ATTR_ALIGNED(16) lv_16sc_t dotProductVector[4];
|
||||
__VOLK_ATTR_ALIGNED(16) lv_16sc_t dotProductVector[4];
|
||||
|
||||
//todo dyn mem reg
|
||||
//todo dyn mem reg
|
||||
|
||||
__m128i* realcacc;
|
||||
__m128i* imagcacc;
|
||||
__m128i* realcacc;
|
||||
__m128i* imagcacc;
|
||||
|
||||
realcacc = (__m128i*)calloc(num_a_vectors, sizeof(__m128i)); //calloc also sets memory to 0
|
||||
imagcacc = (__m128i*)calloc(num_a_vectors, sizeof(__m128i)); //calloc also sets memory to 0
|
||||
realcacc = (__m128i*)calloc(num_a_vectors, sizeof(__m128i)); //calloc also sets memory to 0
|
||||
imagcacc = (__m128i*)calloc(num_a_vectors, sizeof(__m128i)); //calloc also sets memory to 0
|
||||
|
||||
__m128i a,b,c, c_sr, mask_imag, mask_real, real, imag, imag1,imag2, b_sl, a_sl, result;
|
||||
__m128i a,b,c, c_sr, mask_imag, mask_real, real, imag, imag1,imag2, b_sl, a_sl, result;
|
||||
|
||||
mask_imag = _mm_set_epi8(255, 255, 0, 0, 255, 255, 0, 0, 255, 255, 0, 0, 255, 255, 0, 0);
|
||||
mask_real = _mm_set_epi8(0, 0, 255, 255, 0, 0, 255, 255, 0, 0, 255, 255, 0, 0, 255, 255);
|
||||
mask_imag = _mm_set_epi8(255, 255, 0, 0, 255, 255, 0, 0, 255, 255, 0, 0, 255, 255, 0, 0);
|
||||
mask_real = _mm_set_epi8(0, 0, 255, 255, 0, 0, 255, 255, 0, 0, 255, 255, 0, 0, 255, 255);
|
||||
|
||||
// phase rotation registers
|
||||
__m128 pa, pb, two_phase_acc_reg, two_phase_inc_reg;
|
||||
__m128i pc1, pc2;
|
||||
__attribute__((aligned(16))) lv_32fc_t two_phase_inc[2];
|
||||
two_phase_inc[0] = phase_inc * phase_inc;
|
||||
two_phase_inc[1] = phase_inc * phase_inc;
|
||||
two_phase_inc_reg = _mm_load_ps((float*) two_phase_inc);
|
||||
__attribute__((aligned(16))) lv_32fc_t two_phase_acc[2];
|
||||
two_phase_acc[0] = (*phase);
|
||||
two_phase_acc[1] = (*phase) * phase_inc;
|
||||
two_phase_acc_reg = _mm_load_ps((float*)two_phase_acc);
|
||||
__m128 yl, yh, tmp1, tmp2, tmp3;
|
||||
lv_16sc_t tmp16;
|
||||
lv_32fc_t tmp32;
|
||||
// phase rotation registers
|
||||
__m128 pa, pb, two_phase_acc_reg, two_phase_inc_reg;
|
||||
__m128i pc1, pc2;
|
||||
__attribute__((aligned(16))) lv_32fc_t two_phase_inc[2];
|
||||
two_phase_inc[0] = phase_inc * phase_inc;
|
||||
two_phase_inc[1] = phase_inc * phase_inc;
|
||||
two_phase_inc_reg = _mm_load_ps((float*) two_phase_inc);
|
||||
__attribute__((aligned(16))) lv_32fc_t two_phase_acc[2];
|
||||
two_phase_acc[0] = (*phase);
|
||||
two_phase_acc[1] = (*phase) * phase_inc;
|
||||
two_phase_acc_reg = _mm_load_ps((float*)two_phase_acc);
|
||||
__m128 yl, yh, tmp1, tmp2, tmp3;
|
||||
lv_16sc_t tmp16;
|
||||
lv_32fc_t tmp32;
|
||||
|
||||
for(unsigned int number = 0; number < sse_iters; number++)
|
||||
{
|
||||
// Phase rotation on operand in_common starts here:
|
||||
for(unsigned int number = 0; number < sse_iters; number++)
|
||||
{
|
||||
// Phase rotation on operand in_common starts here:
|
||||
|
||||
pa = _mm_set_ps((float)(lv_cimag(_in_common[1])), (float)(lv_creal(_in_common[1])), (float)(lv_cimag(_in_common[0])), (float)(lv_creal(_in_common[0]))); // //load (2 byte imag, 2 byte real) x 2 into 128 bits reg
|
||||
//complex 32fc multiplication b=a*two_phase_acc_reg
|
||||
yl = _mm_moveldup_ps(two_phase_acc_reg); // Load yl with cr,cr,dr,dr
|
||||
yh = _mm_movehdup_ps(two_phase_acc_reg); // Load yh with ci,ci,di,di
|
||||
tmp1 = _mm_mul_ps(pa, yl); // tmp1 = ar*cr,ai*cr,br*dr,bi*dr
|
||||
pa = _mm_shuffle_ps(pa, pa, 0xB1); // Re-arrange x to be ai,ar,bi,br
|
||||
tmp2 = _mm_mul_ps(pa, yh); // tmp2 = ai*ci,ar*ci,bi*di,br*di
|
||||
pb = _mm_addsub_ps(tmp1, tmp2); // ar*cr-ai*ci, ai*cr+ar*ci, br*dr-bi*di, bi*dr+br*di
|
||||
pc1 = _mm_cvtps_epi32(pb); // convert from 32fc to 32ic
|
||||
pa = _mm_set_ps((float)(lv_cimag(_in_common[1])), (float)(lv_creal(_in_common[1])), (float)(lv_cimag(_in_common[0])), (float)(lv_creal(_in_common[0]))); // //load (2 byte imag, 2 byte real) x 2 into 128 bits reg
|
||||
//complex 32fc multiplication b=a*two_phase_acc_reg
|
||||
yl = _mm_moveldup_ps(two_phase_acc_reg); // Load yl with cr,cr,dr,dr
|
||||
yh = _mm_movehdup_ps(two_phase_acc_reg); // Load yh with ci,ci,di,di
|
||||
tmp1 = _mm_mul_ps(pa, yl); // tmp1 = ar*cr,ai*cr,br*dr,bi*dr
|
||||
pa = _mm_shuffle_ps(pa, pa, 0xB1); // Re-arrange x to be ai,ar,bi,br
|
||||
tmp2 = _mm_mul_ps(pa, yh); // tmp2 = ai*ci,ar*ci,bi*di,br*di
|
||||
pb = _mm_addsub_ps(tmp1, tmp2); // ar*cr-ai*ci, ai*cr+ar*ci, br*dr-bi*di, bi*dr+br*di
|
||||
pc1 = _mm_cvtps_epi32(pb); // convert from 32fc to 32ic
|
||||
|
||||
//complex 32fc multiplication two_phase_acc_reg=two_phase_acc_reg*two_phase_inc_reg
|
||||
yl = _mm_moveldup_ps(two_phase_acc_reg); // Load yl with cr,cr,dr,dr
|
||||
yh = _mm_movehdup_ps(two_phase_acc_reg); // Load yh with ci,ci,di,di
|
||||
tmp1 = _mm_mul_ps(two_phase_inc_reg, yl); // tmp1 = ar*cr,ai*cr,br*dr,bi*dr
|
||||
tmp3 = _mm_shuffle_ps(two_phase_inc_reg, two_phase_inc_reg, 0xB1); // Re-arrange x to be ai,ar,bi,br
|
||||
tmp2 = _mm_mul_ps(tmp3, yh); // tmp2 = ai*ci,ar*ci,bi*di,br*di
|
||||
two_phase_acc_reg = _mm_addsub_ps(tmp1, tmp2); // ar*cr-ai*ci, ai*cr+ar*ci, br*dr-bi*di, bi*dr+br*di
|
||||
//complex 32fc multiplication two_phase_acc_reg=two_phase_acc_reg*two_phase_inc_reg
|
||||
yl = _mm_moveldup_ps(two_phase_acc_reg); // Load yl with cr,cr,dr,dr
|
||||
yh = _mm_movehdup_ps(two_phase_acc_reg); // Load yh with ci,ci,di,di
|
||||
tmp1 = _mm_mul_ps(two_phase_inc_reg, yl); // tmp1 = ar*cr,ai*cr,br*dr,bi*dr
|
||||
tmp3 = _mm_shuffle_ps(two_phase_inc_reg, two_phase_inc_reg, 0xB1); // Re-arrange x to be ai,ar,bi,br
|
||||
tmp2 = _mm_mul_ps(tmp3, yh); // tmp2 = ai*ci,ar*ci,bi*di,br*di
|
||||
two_phase_acc_reg = _mm_addsub_ps(tmp1, tmp2); // ar*cr-ai*ci, ai*cr+ar*ci, br*dr-bi*di, bi*dr+br*di
|
||||
|
||||
//next two samples
|
||||
_in_common += 2;
|
||||
pa = _mm_set_ps((float)(lv_cimag(_in_common[1])), (float)(lv_creal(_in_common[1])), (float)(lv_cimag(_in_common[0])), (float)(lv_creal(_in_common[0]))); // //load (2 byte imag, 2 byte real) x 2 into 128 bits reg
|
||||
//complex 32fc multiplication b=a*two_phase_acc_reg
|
||||
yl = _mm_moveldup_ps(two_phase_acc_reg); // Load yl with cr,cr,dr,dr
|
||||
yh = _mm_movehdup_ps(two_phase_acc_reg); // Load yh with ci,ci,di,di
|
||||
tmp1 = _mm_mul_ps(pa, yl); // tmp1 = ar*cr,ai*cr,br*dr,bi*dr
|
||||
pa = _mm_shuffle_ps(pa, pa, 0xB1); // Re-arrange x to be ai,ar,bi,br
|
||||
tmp2 = _mm_mul_ps(pa, yh); // tmp2 = ai*ci,ar*ci,bi*di,br*di
|
||||
pb = _mm_addsub_ps(tmp1, tmp2); // ar*cr-ai*ci, ai*cr+ar*ci, br*dr-bi*di, bi*dr+br*di
|
||||
pc2 = _mm_cvtps_epi32(pb); // convert from 32fc to 32ic
|
||||
//next two samples
|
||||
_in_common += 2;
|
||||
pa = _mm_set_ps((float)(lv_cimag(_in_common[1])), (float)(lv_creal(_in_common[1])), (float)(lv_cimag(_in_common[0])), (float)(lv_creal(_in_common[0]))); // //load (2 byte imag, 2 byte real) x 2 into 128 bits reg
|
||||
//complex 32fc multiplication b=a*two_phase_acc_reg
|
||||
yl = _mm_moveldup_ps(two_phase_acc_reg); // Load yl with cr,cr,dr,dr
|
||||
yh = _mm_movehdup_ps(two_phase_acc_reg); // Load yh with ci,ci,di,di
|
||||
tmp1 = _mm_mul_ps(pa, yl); // tmp1 = ar*cr,ai*cr,br*dr,bi*dr
|
||||
pa = _mm_shuffle_ps(pa, pa, 0xB1); // Re-arrange x to be ai,ar,bi,br
|
||||
tmp2 = _mm_mul_ps(pa, yh); // tmp2 = ai*ci,ar*ci,bi*di,br*di
|
||||
pb = _mm_addsub_ps(tmp1, tmp2); // ar*cr-ai*ci, ai*cr+ar*ci, br*dr-bi*di, bi*dr+br*di
|
||||
pc2 = _mm_cvtps_epi32(pb); // convert from 32fc to 32ic
|
||||
|
||||
//complex 32fc multiplication two_phase_acc_reg=two_phase_acc_reg*two_phase_inc_reg
|
||||
yl = _mm_moveldup_ps(two_phase_acc_reg); // Load yl with cr,cr,dr,dr
|
||||
yh = _mm_movehdup_ps(two_phase_acc_reg); // Load yh with ci,ci,di,di
|
||||
tmp1 = _mm_mul_ps(two_phase_inc_reg, yl); // tmp1 = ar*cr,ai*cr,br*dr,bi*dr
|
||||
tmp3 = _mm_shuffle_ps(two_phase_inc_reg, two_phase_inc_reg, 0xB1); // Re-arrange x to be ai,ar,bi,br
|
||||
tmp2 = _mm_mul_ps(tmp3, yh); // tmp2 = ai*ci,ar*ci,bi*di,br*di
|
||||
two_phase_acc_reg = _mm_addsub_ps(tmp1, tmp2); // ar*cr-ai*ci, ai*cr+ar*ci, br*dr-bi*di, bi*dr+br*di
|
||||
//complex 32fc multiplication two_phase_acc_reg=two_phase_acc_reg*two_phase_inc_reg
|
||||
yl = _mm_moveldup_ps(two_phase_acc_reg); // Load yl with cr,cr,dr,dr
|
||||
yh = _mm_movehdup_ps(two_phase_acc_reg); // Load yh with ci,ci,di,di
|
||||
tmp1 = _mm_mul_ps(two_phase_inc_reg, yl); // tmp1 = ar*cr,ai*cr,br*dr,bi*dr
|
||||
tmp3 = _mm_shuffle_ps(two_phase_inc_reg, two_phase_inc_reg, 0xB1); // Re-arrange x to be ai,ar,bi,br
|
||||
tmp2 = _mm_mul_ps(tmp3, yh); // tmp2 = ai*ci,ar*ci,bi*di,br*di
|
||||
two_phase_acc_reg = _mm_addsub_ps(tmp1, tmp2); // ar*cr-ai*ci, ai*cr+ar*ci, br*dr-bi*di, bi*dr+br*di
|
||||
|
||||
// store four rotated in_common samples in the register b
|
||||
b = _mm_packs_epi32(pc1, pc2);// convert from 32ic to 16ic
|
||||
// store four rotated in_common samples in the register b
|
||||
b = _mm_packs_epi32(pc1, pc2);// convert from 32ic to 16ic
|
||||
|
||||
//next two samples
|
||||
_in_common += 2;
|
||||
//next two samples
|
||||
_in_common += 2;
|
||||
|
||||
for (int n_vec = 0; n_vec < num_a_vectors; n_vec++)
|
||||
{
|
||||
a = _mm_loadu_si128((__m128i*)&(_in_a[n_vec][number*4])); //load (2 byte imag, 2 byte real) x 4 into 128 bits reg
|
||||
for (int n_vec = 0; n_vec < num_a_vectors; n_vec++)
|
||||
{
|
||||
a = _mm_loadu_si128((__m128i*)&(_in_a[n_vec][number*4])); //load (2 byte imag, 2 byte real) x 4 into 128 bits reg
|
||||
|
||||
c = _mm_mullo_epi16 (a, b); // a3.i*b3.i, a3.r*b3.r, ....
|
||||
c = _mm_mullo_epi16 (a, b); // a3.i*b3.i, a3.r*b3.r, ....
|
||||
|
||||
c_sr = _mm_srli_si128 (c, 2); // Shift a right by imm8 bytes while shifting in zeros, and store the results in dst.
|
||||
real = _mm_subs_epi16 (c, c_sr);
|
||||
c_sr = _mm_srli_si128 (c, 2); // Shift a right by imm8 bytes while shifting in zeros, and store the results in dst.
|
||||
real = _mm_subs_epi16 (c, c_sr);
|
||||
|
||||
b_sl = _mm_slli_si128(b, 2); // b3.r, b2.i ....
|
||||
a_sl = _mm_slli_si128(a, 2); // a3.r, a2.i ....
|
||||
b_sl = _mm_slli_si128(b, 2); // b3.r, b2.i ....
|
||||
a_sl = _mm_slli_si128(a, 2); // a3.r, a2.i ....
|
||||
|
||||
imag1 = _mm_mullo_epi16(a, b_sl); // a3.i*b3.r, ....
|
||||
imag2 = _mm_mullo_epi16(b, a_sl); // b3.i*a3.r, ....
|
||||
imag1 = _mm_mullo_epi16(a, b_sl); // a3.i*b3.r, ....
|
||||
imag2 = _mm_mullo_epi16(b, a_sl); // b3.i*a3.r, ....
|
||||
|
||||
imag = _mm_adds_epi16(imag1, imag2);
|
||||
imag = _mm_adds_epi16(imag1, imag2);
|
||||
|
||||
realcacc[n_vec] = _mm_adds_epi16 (realcacc[n_vec], real);
|
||||
imagcacc[n_vec] = _mm_adds_epi16 (imagcacc[n_vec], imag);
|
||||
realcacc[n_vec] = _mm_adds_epi16(realcacc[n_vec], real);
|
||||
imagcacc[n_vec] = _mm_adds_epi16(imagcacc[n_vec], imag);
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
for (int n_vec=0;n_vec<num_a_vectors;n_vec++)
|
||||
{
|
||||
realcacc[n_vec] = _mm_and_si128 (realcacc[n_vec], mask_real);
|
||||
imagcacc[n_vec] = _mm_and_si128 (imagcacc[n_vec], mask_imag);
|
||||
for (int n_vec = 0; n_vec < num_a_vectors; n_vec++)
|
||||
{
|
||||
realcacc[n_vec] = _mm_and_si128 (realcacc[n_vec], mask_real);
|
||||
imagcacc[n_vec] = _mm_and_si128 (imagcacc[n_vec], mask_imag);
|
||||
|
||||
result = _mm_or_si128 (realcacc[n_vec], imagcacc[n_vec]);
|
||||
result = _mm_or_si128(realcacc[n_vec], imagcacc[n_vec]);
|
||||
|
||||
_mm_storeu_si128((__m128i*)dotProductVector, result); // Store the results back into the dot product vector
|
||||
dotProduct = lv_cmake(0,0);
|
||||
for (int i = 0; i<4; ++i)
|
||||
{
|
||||
dotProduct = lv_cmake(sat_adds16i(lv_creal(dotProduct), lv_creal(dotProductVector[i])),
|
||||
sat_adds16i(lv_cimag(dotProduct), lv_cimag(dotProductVector[i])));
|
||||
}
|
||||
_out[n_vec] = dotProduct;
|
||||
}
|
||||
free(realcacc);
|
||||
free(imagcacc);
|
||||
_mm_storeu_si128((__m128i*)dotProductVector, result); // Store the results back into the dot product vector
|
||||
dotProduct = lv_cmake(0,0);
|
||||
for (int i = 0; i<4; ++i)
|
||||
{
|
||||
dotProduct = lv_cmake(sat_adds16i(lv_creal(dotProduct), lv_creal(dotProductVector[i])),
|
||||
sat_adds16i(lv_cimag(dotProduct), lv_cimag(dotProductVector[i])));
|
||||
}
|
||||
_out[n_vec] = dotProduct;
|
||||
}
|
||||
free(realcacc);
|
||||
free(imagcacc);
|
||||
|
||||
_mm_store_ps((float*)two_phase_acc, two_phase_acc_reg);
|
||||
(*phase) = lv_cmake(two_phase_acc[0], two_phase_acc[0]);
|
||||
|
||||
for (int n_vec = 0; n_vec < num_a_vectors; n_vec++)
|
||||
{
|
||||
for(unsigned int n = sse_iters * 4; n < num_points; n++)
|
||||
{
|
||||
tmp16 = *in_common++;
|
||||
tmp32 = lv_cmake((float)lv_creal(tmp16), (float)lv_cimag(tmp16)) * (*phase);
|
||||
tmp16 = lv_cmake((int16_t)rintf(lv_creal(tmp32)), (int16_t)rintf(lv_cimag(tmp32)));
|
||||
(*phase) *= phase_inc;
|
||||
lv_16sc_t tmp = tmp16 * in_a[n_vec][n];
|
||||
_out[n_vec] = lv_cmake(sat_adds16i(lv_creal(_out[n_vec]), lv_creal(tmp)),
|
||||
sat_adds16i(lv_cimag(_out[n_vec]), lv_cimag(tmp)));
|
||||
}
|
||||
}
|
||||
_mm_store_ps((float*)two_phase_acc, two_phase_acc_reg);
|
||||
(*phase) = lv_cmake(two_phase_acc[0], two_phase_acc[0]);
|
||||
|
||||
for (int n_vec = 0; n_vec < num_a_vectors; n_vec++)
|
||||
{
|
||||
for(unsigned int n = sse_iters * 4; n < num_points; n++)
|
||||
{
|
||||
tmp16 = *in_common++;
|
||||
tmp32 = lv_cmake((float)lv_creal(tmp16), (float)lv_cimag(tmp16)) * (*phase);
|
||||
tmp16 = lv_cmake((int16_t)rintf(lv_creal(tmp32)), (int16_t)rintf(lv_cimag(tmp32)));
|
||||
(*phase) *= phase_inc;
|
||||
lv_16sc_t tmp = tmp16 * in_a[n_vec][n];
|
||||
_out[n_vec] = lv_cmake(sat_adds16i(lv_creal(_out[n_vec]), lv_creal(tmp)),
|
||||
sat_adds16i(lv_cimag(_out[n_vec]), lv_cimag(tmp)));
|
||||
}
|
||||
}
|
||||
_out[2] =
|
||||
}
|
||||
#endif /* LV_HAVE_SSE3 */
|
||||
|
||||
|
||||
#ifdef LV_HAVE_NEON
|
||||
#include <arm_neon.h>
|
||||
|
||||
static inline void volk_gnsssdr_16ic_x2_rotator_dot_prod_16ic_xn_neon(lv_16sc_t* out, const lv_16sc_t* in_common, const lv_32fc_t phase_inc, lv_32fc_t* phase, const lv_16sc_t** in_a, int num_a_vectors, unsigned int num_points)
|
||||
{
|
||||
// for (int n_vec = 0; n_vec < num_a_vectors; n_vec++)
|
||||
// {
|
||||
// result[n_vec] = lv_cmake(0,0);
|
||||
// }
|
||||
lv_16sc_t dotProduct = lv_cmake(0,0);
|
||||
|
||||
const unsigned int neon_iters = num_points / 4;
|
||||
|
||||
const lv_16sc_t** _in_a = in_a;
|
||||
const lv_16sc_t* _in_common = in_common;
|
||||
lv_16sc_t* _out = out;
|
||||
lv_16sc_t tmp16_;
|
||||
lv_32fc_t tmp32_;
|
||||
|
||||
lv_32fc_t ___phase4 = phase_inc * phase_inc * phase_inc * phase_inc;
|
||||
__VOLK_ATTR_ALIGNED(16) float32_t __phase4_real[4] = { lv_creal(___phase4), lv_creal(___phase4), lv_creal(___phase4), lv_creal(___phase4) };
|
||||
__VOLK_ATTR_ALIGNED(16) float32_t __phase4_imag[4] = { lv_cimag(___phase4), lv_cimag(___phase4), lv_cimag(___phase4), lv_cimag(___phase4) };
|
||||
|
||||
float32x4_t _phase4_real = vld1q_f32(__phase4_real);
|
||||
float32x4_t _phase4_imag = vld1q_f32(__phase4_imag);
|
||||
|
||||
lv_32fc_t phase2 = (lv_32fc_t)(*phase) * phase_inc;
|
||||
lv_32fc_t phase3 = phase2 * phase_inc;
|
||||
lv_32fc_t phase4 = phase3 * phase_inc;
|
||||
|
||||
__VOLK_ATTR_ALIGNED(16) float32_t __phase_real[4] = { lv_creal((*phase)), lv_creal(phase2), lv_creal(phase3), lv_creal(phase4) };
|
||||
__VOLK_ATTR_ALIGNED(16) float32_t __phase_imag[4] = { lv_cimag((*phase)), lv_cimag(phase2), lv_cimag(phase3), lv_cimag(phase4) };
|
||||
|
||||
float32x4_t _phase_real = vld1q_f32(__phase_real);
|
||||
float32x4_t _phase_imag = vld1q_f32(__phase_imag);
|
||||
|
||||
float32x4_t half = vdupq_n_f32(0.5f);
|
||||
int16x4x2_t tmp16;
|
||||
int32x4x2_t tmp32i;
|
||||
float32x4x2_t tmp32f, tmp_real, tmp_imag;
|
||||
float32x4_t sign, PlusHalf, Round;
|
||||
|
||||
int16x4x2_t* accumulator;
|
||||
accumulator = (int16x4x2_t*)calloc(num_a_vectors, sizeof(int16x4x2_t));
|
||||
|
||||
int16x4x2_t tmp_real, tmp_imag;
|
||||
|
||||
for(int n_vec = 0; n_vec < num_a_vectors; n_vec++)
|
||||
{
|
||||
accumulator[n_vec].val[0] = vdup_n_s16(0);
|
||||
accumulator[n_vec].val[1] = vdup_n_s16(0);
|
||||
}
|
||||
|
||||
if (neon_iters > 0)
|
||||
{
|
||||
int16x4x2_t a_val, b_val, c_val;
|
||||
|
||||
|
||||
for(unsigned int number = 0; number < neon_iters; number++)
|
||||
{
|
||||
/* load 4 complex numbers (int 16 bits each component) */
|
||||
tmp16 = vld2_s16((int16_t*)_in_common);
|
||||
__builtin_prefetch(_in_common + 8);
|
||||
_in_common += 4;
|
||||
|
||||
/* promote them to int 32 bits */
|
||||
tmp32i.val[0] = vmovl_s16(tmp16.val[0]);
|
||||
tmp32i.val[1] = vmovl_s16(tmp16.val[1]);
|
||||
|
||||
/* promote them to float 32 bits */
|
||||
tmp32f.val[0] = vcvtq_f32_s32(tmp32i.val[0]);
|
||||
tmp32f.val[1] = vcvtq_f32_s32(tmp32i.val[1]);
|
||||
|
||||
/* complex multiplication of four complex samples (float 32 bits each component) */
|
||||
tmp_real.val[0] = vmulq_f32(tmp32f.val[0], _phase_real);
|
||||
tmp_real.val[1] = vmulq_f32(tmp32f.val[1], _phase_imag);
|
||||
tmp_imag.val[0] = vmulq_f32(tmp32f.val[0], _phase_imag);
|
||||
tmp_imag.val[1] = vmulq_f32(tmp32f.val[1], _phase_real);
|
||||
|
||||
tmp32f.val[0] = vsubq_f32(tmp_real.val[0], tmp_real.val[1]);
|
||||
tmp32f.val[1] = vaddq_f32(tmp_imag.val[0], tmp_imag.val[1]);
|
||||
|
||||
/* downcast results to int32 */
|
||||
/* in __aarch64__ we can do that with vcvtaq_s32_f32(ret1); vcvtaq_s32_f32(ret2); */
|
||||
sign = vcvtq_f32_u32((vshrq_n_u32(vreinterpretq_u32_f32(tmp32f.val[0]), 31)));
|
||||
PlusHalf = vaddq_f32(tmp32f.val[0], half);
|
||||
Round = vsubq_f32(PlusHalf, sign);
|
||||
tmp32i.val[0] = vcvtq_s32_f32(Round);
|
||||
|
||||
sign = vcvtq_f32_u32((vshrq_n_u32(vreinterpretq_u32_f32(tmp32f.val[1]), 31)));
|
||||
PlusHalf = vaddq_f32(tmp32f.val[1], half);
|
||||
Round = vsubq_f32(PlusHalf, sign);
|
||||
tmp32i.val[1] = vcvtq_s32_f32(Round);
|
||||
|
||||
/* downcast results to int16 */
|
||||
tmp16.val[0] = vqmovn_s32(tmp32i.val[0]);
|
||||
tmp16.val[1] = vqmovn_s32(tmp32i.val[1]);
|
||||
|
||||
/* compute next four phases */
|
||||
tmp_real.val[0] = vmulq_f32(_phase_real, _phase4_real);
|
||||
tmp_real.val[1] = vmulq_f32(_phase_imag, _phase4_imag);
|
||||
tmp_imag.val[0] = vmulq_f32(_phase_real, _phase4_imag);
|
||||
tmp_imag.val[1] = vmulq_f32(_phase_imag, _phase4_real);
|
||||
|
||||
_phase_real = vsubq_f32(tmp_real.val[0], tmp_real.val[1]);
|
||||
_phase_imag = vaddq_f32(tmp_imag.val[0], tmp_imag.val[1]);
|
||||
|
||||
|
||||
for (int n_vec = 0; n_vec < num_a_vectors; n_vec++)
|
||||
{
|
||||
a_val = vld2_s16((int16_t*)&(_in_a[n_vec][number*4])); //load (2 byte imag, 2 byte real) x 4 into 128 bits reg
|
||||
//__builtin_prefetch(_in_a[n_vec] + 8);
|
||||
|
||||
// multiply the real*real and imag*imag to get real result
|
||||
// a0r*b0r|a1r*b1r|a2r*b2r|a3r*b3r
|
||||
tmp_real.val[0] = vmul_s16(a_val.val[0], b_val.val[0]);
|
||||
// a0i*b0i|a1i*b1i|a2i*b2i|a3i*b3i
|
||||
tmp_real.val[1] = vmul_s16(a_val.val[1], b_val.val[1]);
|
||||
|
||||
// Multiply cross terms to get the imaginary result
|
||||
// a0r*b0i|a1r*b1i|a2r*b2i|a3r*b3i
|
||||
tmp_imag.val[0] = vmul_s16(a_val.val[0], b_val.val[1]);
|
||||
// a0i*b0r|a1i*b1r|a2i*b2r|a3i*b3r
|
||||
tmp_imag.val[1] = vmul_s16(a_val.val[1], b_val.val[0]);
|
||||
|
||||
c_val.val[0] = vsub_s16(tmp_real.val[0], tmp_real.val[1]);
|
||||
c_val.val[1] = vadd_s16(tmp_imag.val[0], tmp_imag.val[1]);
|
||||
|
||||
accumulator[n_vec].val[0] = vadd_s16(accumulator[n_vec].val[0], c_val.val[0]);
|
||||
accumulator[n_vec].val[1] = vadd_s16(accumulator[n_vec].val[1], c_val.val[1]);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
for (int n_vec = 0; n_vec < num_a_vectors; n_vec++)
|
||||
{
|
||||
for(unsigned int n = sse_iters * 4; n < num_points; n++)
|
||||
{
|
||||
tmp16_ = *in_common++;
|
||||
tmp32_ = lv_cmake((float)lv_creal(tmp16_), (float)lv_cimag(tmp16_)) * (*phase);
|
||||
tmp16_ = lv_cmake((int16_t)rintf(lv_creal(tmp32_)), (int16_t)rintf(lv_cimag(tmp32_)));
|
||||
(*phase) *= phase_inc;
|
||||
lv_16sc_t tmp = tmp16_ * in_a[n_vec][n];
|
||||
_out[n_vec] = lv_cmake(sat_adds16i(lv_creal(_out[n_vec]), lv_creal(tmp)),
|
||||
sat_adds16i(lv_cimag(_out[n_vec]), lv_cimag(tmp)));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#endif /* LV_HAVE_NEON */
|
||||
|
||||
#endif /*INCLUDED_volk_gnsssdr_16ic_xn_dot_prod_16ic_xn_H*/
|
||||
|
|
|
|||
|
|
@ -132,6 +132,37 @@ static inline void volk_gnsssdr_16ic_x2_rotator_dotprodxnpuppet_16ic_u_sse3(lv_1
|
|||
|
||||
#endif // SSE3
|
||||
|
||||
#ifdef LV_HAVE_NEON
|
||||
|
||||
static inline void volk_gnsssdr_16ic_x2_rotator_dotprodxnpuppet_16ic_neon(lv_16sc_t* result, const lv_16sc_t* local_code, const lv_16sc_t* in, unsigned int num_points)
|
||||
{
|
||||
// phases must be normalized. Phase rotator expects a complex exponential input!
|
||||
float rem_carrier_phase_in_rad = 0.345;
|
||||
float phase_step_rad = 0.123;
|
||||
lv_32fc_t phase[1];
|
||||
phase[0] = lv_cmake(cos(rem_carrier_phase_in_rad), -sin(rem_carrier_phase_in_rad));
|
||||
lv_32fc_t phase_inc[1];
|
||||
phase_inc[0] = lv_cmake(cos(phase_step_rad), -sin(phase_step_rad));
|
||||
|
||||
int num_a_vectors = 3;
|
||||
lv_16sc_t** in_a = (lv_16sc_t**)volk_gnsssdr_malloc(sizeof(lv_16sc_t*) * num_a_vectors, volk_gnsssdr_get_alignment());
|
||||
for(unsigned int n = 0; n < num_a_vectors; n++)
|
||||
{
|
||||
in_a[n] = (lv_16sc_t*)volk_gnsssdr_malloc(sizeof(lv_16sc_t)*num_points, volk_gnsssdr_get_alignment());
|
||||
memcpy(in_a[n], in, sizeof(lv_16sc_t)*num_points);
|
||||
}
|
||||
result = (lv_16sc_t*)calloc(num_points, sizeof(lv_16sc_t));
|
||||
volk_gnsssdr_16ic_x2_rotator_dot_prod_16ic_xn_u_sse3(result, local_code, phase_inc[0], phase, (const lv_16sc_t**) in_a, num_a_vectors, num_points);
|
||||
|
||||
for(unsigned int n = 0; n < num_a_vectors; n++)
|
||||
{
|
||||
volk_gnsssdr_free(in_a[n]);
|
||||
}
|
||||
volk_gnsssdr_free(in_a);
|
||||
}
|
||||
|
||||
#endif // NEON
|
||||
|
||||
#endif // INCLUDED_volk_gnsssdr_16ic_x2_rotator_dotprodxnpuppet_16ic_H
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user