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https://github.com/gnss-sdr/gnss-sdr
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Merge branch 'mmajoral-update_tracking_FPGA' into next
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commit
decade163d
@ -132,8 +132,8 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
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d_trk_parameters.y_intercept = 1.0;
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// symbol integration: 20 trk symbols (20 ms) = 1 tlm bit
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// set the bit transition pattern in secondary code to obtain bit synchronization
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d_secondary_code_length = static_cast<uint32_t>(GPS_CA_BIT_TRANSITION_SYMBOLS_LENGTH_SYMBOLS);
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d_secondary_code_string = GPS_CA_BIT_TRANSITION_SYMBOLS_STR;
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d_secondary_code_length = static_cast<uint32_t>(GPS_CA_PREAMBLE_LENGTH_SYMBOLS);
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d_secondary_code_string = GPS_CA_PREAMBLE_SYMBOLS_STR;
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d_symbols_per_bit = GPS_CA_TELEMETRY_SYMBOLS_PER_BIT;
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}
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else if (d_signal_type == "2S")
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@ -466,6 +466,7 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
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d_stop_tracking = false;
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d_acc_carrier_phase_initialized = false;
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d_Flag_PLL_180_deg_phase_locked = false;
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}
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@ -585,6 +586,14 @@ bool dll_pll_veml_tracking_fpga::acquire_secondary()
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if (abs(corr_value) == static_cast<int32_t>(d_secondary_code_length))
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{
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if (corr_value < 0)
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{
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d_Flag_PLL_180_deg_phase_locked = true;
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}
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else
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{
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d_Flag_PLL_180_deg_phase_locked = false;
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}
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return true;
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}
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@ -1493,6 +1502,7 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
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auto **out = reinterpret_cast<Gnss_Synchro **>(&output_items[0]);
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Gnss_Synchro current_synchro_data = Gnss_Synchro();
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current_synchro_data.Flag_valid_symbol_output = false;
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bool loss_of_lock = false;
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while ((!current_synchro_data.Flag_valid_symbol_output) && (!d_stop_tracking))
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{
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@ -1616,10 +1626,9 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
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if (!cn0_and_tracking_lock_status(d_code_period))
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{
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clear_tracking_vars();
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d_state = 1; // loss-of-lock detected
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// send something to let the scheduler know that it has to keep on calling general work and to finish the loop
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// current_synchro_data.Flag_valid_symbol_output=1;
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d_state = 1; // loss-of-lock detected
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loss_of_lock = true; // Set the flag so that the negative indication can be generated
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current_synchro_data = *d_acquisition_gnss_synchro; // Fill in the Gnss_Synchro object with basic info
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}
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else
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{
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@ -1818,10 +1827,9 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
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if (!cn0_and_tracking_lock_status(d_code_period * static_cast<double>(d_trk_parameters.extend_correlation_symbols)))
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{
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clear_tracking_vars();
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d_state = 1; // loss-of-lock detected
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// send something to let the scheduler know that it has to keep on calling general work and to finish the loop
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// current_synchro_data.Flag_valid_symbol_output=1;
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d_state = 1; // loss-of-lock detected
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loss_of_lock = true; // Set the flag so that the negative indication can be generated
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current_synchro_data = *d_acquisition_gnss_synchro; // Fill in the Gnss_Synchro object with basic info
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}
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else
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{
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@ -1941,10 +1949,9 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
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if (!cn0_and_tracking_lock_status(d_code_period * static_cast<double>(d_trk_parameters.extend_correlation_symbols)))
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{
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clear_tracking_vars();
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d_state = 1; // loss-of-lock detected
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// send something to let the scheduler know that it has to keep on calling general work and to finish the loop
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// current_synchro_data.Flag_valid_symbol_output=1;
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d_state = 1; // loss-of-lock detected
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loss_of_lock = true; // Set the flag so that the negative indication can be generated
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current_synchro_data = *d_acquisition_gnss_synchro; // Fill in the Gnss_Synchro object with basic info
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}
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else
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{
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@ -1999,10 +2006,12 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
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}
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}
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if (current_synchro_data.Flag_valid_symbol_output)
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if (current_synchro_data.Flag_valid_symbol_output || loss_of_lock)
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{
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current_synchro_data.fs = static_cast<int64_t>(d_trk_parameters.fs_in);
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current_synchro_data.Tracking_sample_counter = d_sample_counter_next; // d_sample_counter;
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current_synchro_data.Flag_valid_symbol_output = !loss_of_lock;
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current_synchro_data.Flag_PLL_180_deg_phase_locked = d_Flag_PLL_180_deg_phase_locked;
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*out[0] = current_synchro_data;
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return 1;
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}
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@ -240,6 +240,7 @@ private:
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bool d_current_extended_correlation_in_fpga;
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bool d_stop_tracking;
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bool d_sc_demodulate_enabled;
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bool d_Flag_PLL_180_deg_phase_locked;
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};
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