mirrors/gnss-sdr
1
0
Fork 0
mirror of https://github.com/gnss-sdr/gnss-sdr synced 2026-09-17 06:31:22 +00:00
Code Issues Releases Wiki Activity

Expose bit synchronizer parameters to user configuration

Browse Source
This commit is contained in:
Carles Fernandez
2026-02-03 14:18:54 +01:00
parent b7f4f3b754
commit d3bd3717f1
6 changed files with 32 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/algorithms/tracking/gnuradio_blocks/dll_pll_veml_tracking.cc
+5 -2
View File
@@ -1302,8 +1302,11 @@ void dll_pll_veml_tracking::configure_bit_synchronizer()
HistogramBitSynchronizer::Config cfg;
cfg.bit_period_ms = d_symbols_per_bit * d_correlation_length_ms;
cfg.epoch_ms = d_correlation_length_ms;
cfg.min_events_for_lock = 5;
cfg.stable_best_required = 3;
cfg.min_events_for_lock = d_trk_parameters.bs_min_events_for_lock;
cfg.stable_best_required = d_trk_parameters.bs_stable_best_required;
cfg.dominance_ratio = d_trk_parameters.bs_dominance_ratio;
cfg.min_prompt_mag = d_trk_parameters.bs_min_prompt_mag;
cfg.use_phase_dot_detector = d_trk_parameters.bs_use_phase_dot_detector;
d_bit_sync = HistogramBitSynchronizer(cfg);
}
src/algorithms/tracking/gnuradio_blocks/dll_pll_veml_tracking_fpga.cc
+5
View File
@@ -830,6 +830,11 @@ void dll_pll_veml_tracking_fpga::configure_bit_synchronizer()
HistogramBitSynchronizer::Config cfg;
cfg.bit_period_ms = d_symbols_per_bit * d_correlation_length_ms;
cfg.epoch_ms = d_correlation_length_ms;
cfg.min_events_for_lock = d_trk_parameters.bs_min_events_for_lock;
cfg.stable_best_required = d_trk_parameters.bs_stable_best_required;
cfg.dominance_ratio = d_trk_parameters.bs_dominance_ratio;
cfg.min_prompt_mag = d_trk_parameters.bs_min_prompt_mag;
cfg.use_phase_dot_detector = d_trk_parameters.bs_use_phase_dot_detector;
d_bit_sync = HistogramBitSynchronizer(cfg);
}
src/algorithms/tracking/libs/dll_pll_conf.cc
+6
View File
@@ -149,4 +149,10 @@ void Dll_Pll_Conf::SetFromConfiguration(const ConfigurationInterface *configurat
carrier_lock_test_smoother_samples = configuration->property(role + ".carrier_lock_test_smoother_samples", carrier_lock_test_smoother_samples);
carrier_lock_test_smoother_alpha = configuration->property(role + ".carrier_lock_test_smoother_alpha", carrier_lock_test_smoother_alpha);
tow_to_trk = configuration->property("GNSS-SDR.tow_to_trk", false);
bs_dominance_ratio = configuration->property(role + ".bs_dominance_ratio", bs_dominance_ratio);
bs_min_prompt_mag = configuration->property(role + ".bs_min_prompt_mag", bs_min_prompt_mag);
bs_stable_best_required = configuration->property(role + ".bs_stable_best_required", bs_stable_best_required);
bs_min_events_for_lock = configuration->property(role + ".bs_min_events_for_lock", bs_min_events_for_lock);
bs_use_phase_dot_detector = configuration->property(role + ".bs_use_phase_dot_detector", bs_use_phase_dot_detector);
}
src/algorithms/tracking/libs/dll_pll_conf.h
+5
View File
@@ -40,6 +40,7 @@ public:
std::string dump_filename{"./dll_pll_dump.dat"};
double fs_in{2000000.0};
double carrier_lock_th{0.0};
double bs_dominance_ratio{0.6};
float pll_pull_in_bw_hz{50.0};
float dll_pull_in_bw_hz{3.0};
float fll_bw_hz{35.0};
@@ -56,6 +57,7 @@ public:
float y_intercept{1.0};
float cn0_smoother_alpha{0.002};
float carrier_lock_test_smoother_alpha{0.002};
float bs_min_prompt_mag{0.0};
uint32_t pull_in_time_s{10U};
uint32_t bit_synchronization_time_limit_s{20U};
uint32_t vector_length{0U};
@@ -70,6 +72,8 @@ public:
int32_t cn0_min{0};
int32_t max_code_lock_fail{0};
int32_t max_carrier_lock_fail{0};
int32_t bs_stable_best_required{3};
int32_t bs_min_events_for_lock{5};
char signal[3]{};
char system{'G'};
bool enable_fll_pull_in{false};
@@ -81,6 +85,7 @@ public:
bool dump{false};
bool dump_mat{true};
bool tow_to_trk{false};
bool bs_use_phase_dot_detector{true};
};
src/algorithms/tracking/libs/dll_pll_conf_fpga.cc
+6
View File
@@ -146,4 +146,10 @@ void Dll_Pll_Conf_Fpga::SetFromConfiguration(const ConfigurationInterface *confi
// max_lock_fail = 50;
device_name = configuration->property(role + ".devicename", device_name);
bs_dominance_ratio = configuration->property(role + ".bs_dominance_ratio", bs_dominance_ratio);
bs_min_prompt_mag = configuration->property(role + ".bs_min_prompt_mag", bs_min_prompt_mag);
bs_stable_best_required = configuration->property(role + ".bs_stable_best_required", bs_stable_best_required);
bs_min_events_for_lock = configuration->property(role + ".bs_min_events_for_lock", bs_min_events_for_lock);
bs_use_phase_dot_detector = configuration->property(role + ".bs_use_phase_dot_detector", bs_use_phase_dot_detector);
}
src/algorithms/tracking/libs/dll_pll_conf_fpga.h
+5
View File
@@ -43,6 +43,7 @@ public:
double fs_in{12500000.0};
double carrier_lock_th{0.0};
double bs_dominance_ratio{0.6};
float pll_pull_in_bw_hz{50.0};
float dll_pull_in_bw_hz{3.0};
@@ -60,6 +61,7 @@ public:
float y_intercept{1.0};
float cn0_smoother_alpha{0.002};
float carrier_lock_test_smoother_alpha{0.002};
float bs_min_prompt_mag{0.0};
uint32_t pull_in_time_s{10U}; // signed integer, when pull in time is not yet reached it has to be compared against a negative number
uint32_t bit_synchronization_time_limit_s{70U};
@@ -81,6 +83,8 @@ public:
int32_t cn0_smoother_samples{200};
int32_t carrier_lock_test_smoother_samples{25};
// int32_t max_lock_fail;
int32_t bs_stable_best_required{3};
int32_t bs_min_events_for_lock{5};
int32_t* ca_codes{nullptr};
int32_t* data_codes{nullptr};
@@ -97,6 +101,7 @@ public:
bool high_dyn{false};
bool dump{false};
bool dump_mat{true};
bool bs_use_phase_dot_detector{true};
};