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https://github.com/gnss-sdr/gnss-sdr
synced 2025-01-18 21:23:02 +00:00
use std::array
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@ -602,7 +602,7 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0_, cons
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// rx signal vectors
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std::vector<int8_t> input_samples(sample_block_size * 2); // complex samples
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// pointer to DMA buffer
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int8_t *dma_buffer;
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std::array<int8_t, BUFFER_SIZE> *dma_buffer;
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int nread_elements = 0; // num bytes read from the file corresponding to frequency band 1
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bool run_DMA = true;
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@ -623,8 +623,8 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0_, cons
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// if only one file is enabled then clear the samples corresponding to the frequency band that is not used.
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for (int index0 = 0; index0 < (nread_elements); index0 += 2)
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{
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dma_buffer[dma_index + (2 - dma_buff_offset_pos)] = 0;
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dma_buffer[dma_index + 1 + (2 - dma_buff_offset_pos)] = 0;
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(*dma_buffer)[dma_index + (2 - dma_buff_offset_pos)] = 0;
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(*dma_buffer)[dma_index + 1 + (2 - dma_buff_offset_pos)] = 0;
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dma_index += 4;
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}
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}
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@ -665,8 +665,8 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0_, cons
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for (int index0 = 0; index0 < (nread_elements); index0 += 2)
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{
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// dma_buff_offset_pos is 1 for the L1 band and 0 for the other bands
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dma_buffer[dma_index + dma_buff_offset_pos] = input_samples[index0];
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dma_buffer[dma_index + 1 + dma_buff_offset_pos] = input_samples[index0 + 1];
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(*dma_buffer)[dma_index + dma_buff_offset_pos] = input_samples[index0];
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(*dma_buffer)[dma_index + 1 + dma_buff_offset_pos] = input_samples[index0 + 1];
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dma_index += 4;
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}
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@ -696,8 +696,8 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0_, cons
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for (int index0 = 0; index0 < (nread_elements); index0 += 2)
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{
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// filename2 is never the L1 band
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dma_buffer[dma_index] = input_samples[index0];
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dma_buffer[dma_index + 1] = input_samples[index0 + 1];
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(*dma_buffer)[dma_index] = input_samples[index0];
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(*dma_buffer)[dma_index + 1] = input_samples[index0 + 1];
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dma_index += 4;
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}
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}
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@ -1,6 +1,7 @@
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/*!
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* \file fpga_dma.cc
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* \brief FPGA DMA control.
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* \brief FPGA DMA control. This code is based in the Xilinx DMA proxy test application:
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* https://github.com/Xilinx-Wiki-Projects/software-prototypes/tree/master/linux-user-space-dma/Software
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* \author Marc Majoral, mmajoral(at)cttc.es
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*
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* -----------------------------------------------------------------------------
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@ -67,12 +68,12 @@ int Fpga_DMA::DMA_open()
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}
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int8_t *Fpga_DMA::get_buffer_address(void)
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std::array<int8_t, BUFFER_SIZE> *Fpga_DMA::get_buffer_address(void)
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{
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#if INTPTR_MAX == INT64_MAX // 64-bit processor architecture
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return tx_channel.buf_ptr[0].buffer;
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return &tx_channel.buf_ptr[0].buffer;
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#else // 32-bit processor architecture
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return buffer;
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return &buffer;
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#endif
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}
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@ -1,6 +1,7 @@
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/*!
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* \file fpga_dma.h
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* \brief FPGA DMA control.
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* \brief FPGA DMA control. This code is based in the Xilinx DMA proxy test application:
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* https://github.com/Xilinx-Wiki-Projects/software-prototypes/tree/master/linux-user-space-dma/Software
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* \author Marc Majoral, mmajoral(at)cttc.es
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*
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* -----------------------------------------------------------------------------
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@ -18,7 +19,8 @@
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#ifndef GNSS_SDR_FPGA_DMA_H
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#define GNSS_SDR_FPGA_DMA_H
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#include <cstdint> // for int8_t
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#include <array> // for std::array
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#include <cstdint> // for std::int8_t
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#define BUFFER_SIZE (128 * 1024) /* must match driver exactly */
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@ -32,7 +34,7 @@
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// channel buffer structure
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struct channel_buffer
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{
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int8_t buffer[BUFFER_SIZE];
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std::array<int8_t, BUFFER_SIZE> buffer;
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enum proxy_status
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{
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PROXY_NO_ERROR = 0,
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@ -76,7 +78,7 @@ public:
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/*!
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* \brief Obtain DMA buffer address.
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*/
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int8_t *get_buffer_address(void);
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std::array<int8_t, BUFFER_SIZE> *get_buffer_address(void);
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/*!
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* \brief Transfer DMA data
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*/
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@ -90,8 +92,8 @@ public:
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private:
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#if INTPTR_MAX == INT64_MAX // 64-bit processor architecture
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channel tx_channel;
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int8_t buffer[BUFFER_SIZE];
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#else // 32-bit processor architecture
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std::array<int8_t, BUFFER_SIZE> buffer[BUFFER_SIZE];
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int tx_fd;
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#endif
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};
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