diff --git a/src/algorithms/signal_source/adapters/ad9361_fpga_signal_source.cc b/src/algorithms/signal_source/adapters/ad9361_fpga_signal_source.cc
index dece5581c..35ac26dac 100644
--- a/src/algorithms/signal_source/adapters/ad9361_fpga_signal_source.cc
+++ b/src/algorithms/signal_source/adapters/ad9361_fpga_signal_source.cc
@@ -602,7 +602,7 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0_, cons
     // rx signal vectors
     std::vector<int8_t> input_samples(sample_block_size * 2);  // complex samples
     // pointer to DMA buffer
-    int8_t *dma_buffer;
+    std::array<int8_t, BUFFER_SIZE> *dma_buffer;
     int nread_elements = 0;  // num bytes read from the file corresponding to frequency band 1
     bool run_DMA = true;
 
@@ -623,8 +623,8 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0_, cons
             // if only one file is enabled then clear the samples corresponding to the frequency band that is not used.
             for (int index0 = 0; index0 < (nread_elements); index0 += 2)
                 {
-                    dma_buffer[dma_index + (2 - dma_buff_offset_pos)] = 0;
-                    dma_buffer[dma_index + 1 + (2 - dma_buff_offset_pos)] = 0;
+                    (*dma_buffer)[dma_index + (2 - dma_buff_offset_pos)] = 0;
+                    (*dma_buffer)[dma_index + 1 + (2 - dma_buff_offset_pos)] = 0;
                     dma_index += 4;
                 }
         }
@@ -665,8 +665,8 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0_, cons
             for (int index0 = 0; index0 < (nread_elements); index0 += 2)
                 {
                     // dma_buff_offset_pos is 1 for the L1 band and 0 for the other bands
-                    dma_buffer[dma_index + dma_buff_offset_pos] = input_samples[index0];
-                    dma_buffer[dma_index + 1 + dma_buff_offset_pos] = input_samples[index0 + 1];
+                    (*dma_buffer)[dma_index + dma_buff_offset_pos] = input_samples[index0];
+                    (*dma_buffer)[dma_index + 1 + dma_buff_offset_pos] = input_samples[index0 + 1];
                     dma_index += 4;
                 }
 
@@ -696,8 +696,8 @@ void Ad9361FpgaSignalSource::run_DMA_process(const std::string &filename0_, cons
                     for (int index0 = 0; index0 < (nread_elements); index0 += 2)
                         {
                             // filename2 is never the L1 band
-                            dma_buffer[dma_index] = input_samples[index0];
-                            dma_buffer[dma_index + 1] = input_samples[index0 + 1];
+                            (*dma_buffer)[dma_index] = input_samples[index0];
+                            (*dma_buffer)[dma_index + 1] = input_samples[index0 + 1];
                             dma_index += 4;
                         }
                 }
diff --git a/src/algorithms/signal_source/libs/fpga_dma.cc b/src/algorithms/signal_source/libs/fpga_dma.cc
index e976e7686..3a7bc3eb5 100644
--- a/src/algorithms/signal_source/libs/fpga_dma.cc
+++ b/src/algorithms/signal_source/libs/fpga_dma.cc
@@ -1,6 +1,7 @@
 /*!
  * \file fpga_dma.cc
- * \brief FPGA DMA control.
+ * \brief FPGA DMA control. This code is based in the Xilinx DMA proxy test application:
+ * https://github.com/Xilinx-Wiki-Projects/software-prototypes/tree/master/linux-user-space-dma/Software
  * \author Marc Majoral, mmajoral(at)cttc.es
  *
  * -----------------------------------------------------------------------------
@@ -67,12 +68,12 @@ int Fpga_DMA::DMA_open()
 }
 
 
-int8_t *Fpga_DMA::get_buffer_address(void)
+std::array<int8_t, BUFFER_SIZE> *Fpga_DMA::get_buffer_address(void)
 {
 #if INTPTR_MAX == INT64_MAX  // 64-bit processor architecture
-    return tx_channel.buf_ptr[0].buffer;
+    return &tx_channel.buf_ptr[0].buffer;
 #else  // 32-bit processor architecture
-    return buffer;
+    return &buffer;
 #endif
 }
 
diff --git a/src/algorithms/signal_source/libs/fpga_dma.h b/src/algorithms/signal_source/libs/fpga_dma.h
index 0657be320..0fd8041ec 100644
--- a/src/algorithms/signal_source/libs/fpga_dma.h
+++ b/src/algorithms/signal_source/libs/fpga_dma.h
@@ -1,6 +1,7 @@
 /*!
  * \file fpga_dma.h
- * \brief FPGA DMA control.
+ * \brief FPGA DMA control. This code is based in the Xilinx DMA proxy test application:
+ * https://github.com/Xilinx-Wiki-Projects/software-prototypes/tree/master/linux-user-space-dma/Software
  * \author Marc Majoral, mmajoral(at)cttc.es
  *
  * -----------------------------------------------------------------------------
@@ -18,7 +19,8 @@
 #ifndef GNSS_SDR_FPGA_DMA_H
 #define GNSS_SDR_FPGA_DMA_H
 
-#include <cstdint>  // for int8_t
+#include <array>    // for std::array
+#include <cstdint>  // for std::int8_t
 
 #define BUFFER_SIZE (128 * 1024) /* must match driver exactly */
 
@@ -32,7 +34,7 @@
 // channel buffer structure
 struct channel_buffer
 {
-    int8_t buffer[BUFFER_SIZE];
+    std::array<int8_t, BUFFER_SIZE> buffer;
     enum proxy_status
     {
         PROXY_NO_ERROR = 0,
@@ -76,7 +78,7 @@ public:
     /*!
      * \brief Obtain DMA buffer address.
      */
-    int8_t *get_buffer_address(void);
+    std::array<int8_t, BUFFER_SIZE> *get_buffer_address(void);
     /*!
      * \brief Transfer DMA data
      */
@@ -90,8 +92,8 @@ public:
 private:
 #if INTPTR_MAX == INT64_MAX  // 64-bit processor architecture
     channel tx_channel;
-    int8_t buffer[BUFFER_SIZE];
 #else  // 32-bit processor architecture
+    std::array<int8_t, BUFFER_SIZE> buffer[BUFFER_SIZE];
     int tx_fd;
 #endif
 };