mirror of
				https://github.com/gnss-sdr/gnss-sdr
				synced 2025-10-30 23:03:05 +00:00 
			
		
		
		
	Add Comet Lake support
This commit is contained in:
		| @@ -132,6 +132,7 @@ typedef enum | |||||||
|     INTEL_KBL,           // KABY LAKE |     INTEL_KBL,           // KABY LAKE | ||||||
|     INTEL_CFL,           // COFFEE LAKE |     INTEL_CFL,           // COFFEE LAKE | ||||||
|     INTEL_WHL,           // WHISKEY LAKE |     INTEL_WHL,           // WHISKEY LAKE | ||||||
|  |     INTEL_CML,           // COMET LAKE | ||||||
|     INTEL_CNL,           // CANNON LAKE |     INTEL_CNL,           // CANNON LAKE | ||||||
|     INTEL_ICL,           // ICE LAKE |     INTEL_ICL,           // ICE LAKE | ||||||
|     INTEL_TGL,           // TIGER LAKE |     INTEL_TGL,           // TIGER LAKE | ||||||
|   | |||||||
| @@ -561,6 +561,8 @@ X86Microarchitecture GetX86Microarchitecture(const X86Info* info) | |||||||
|                             return INTEL_CFL;  // https://en.wikipedia.org/wiki/Coffee_Lake |                             return INTEL_CFL;  // https://en.wikipedia.org/wiki/Coffee_Lake | ||||||
|                         case 11: |                         case 11: | ||||||
|                             return INTEL_WHL;  // https://en.wikipedia.org/wiki/Whiskey_Lake_(microarchitecture) |                             return INTEL_WHL;  // https://en.wikipedia.org/wiki/Whiskey_Lake_(microarchitecture) | ||||||
|  |                         case 12: | ||||||
|  |                             return INTEL_CML;  // https://en.wikichip.org/wiki/intel/microarchitectures/comet_lake | ||||||
|                         default: |                         default: | ||||||
|                             return X86_UNKNOWN; |                             return X86_UNKNOWN; | ||||||
|                         } |                         } | ||||||
| @@ -579,6 +581,9 @@ X86Microarchitecture GetX86Microarchitecture(const X86Info* info) | |||||||
|                 case CPUID(0x06, 0x9A): |                 case CPUID(0x06, 0x9A): | ||||||
|                     // https://en.wikichip.org/wiki/intel/microarchitectures/alder_lake |                     // https://en.wikichip.org/wiki/intel/microarchitectures/alder_lake | ||||||
|                     return INTEL_ADL; |                     return INTEL_ADL; | ||||||
|  |                 case CPUID(0x06, 0xA5): | ||||||
|  |                     // https://en.wikichip.org/wiki/intel/microarchitectures/comet_lake | ||||||
|  |                     return INTEL_CML; | ||||||
|                 case CPUID(0x06, 0xA7): |                 case CPUID(0x06, 0xA7): | ||||||
|                     // https://en.wikichip.org/wiki/intel/microarchitectures/rocket_lake |                     // https://en.wikichip.org/wiki/intel/microarchitectures/rocket_lake | ||||||
|                     return INTEL_RCL; |                     return INTEL_RCL; | ||||||
| @@ -1830,6 +1835,7 @@ CacheInfo GetX86CacheInfo(void) | |||||||
|     LINE(INTEL_KBL)                 \ |     LINE(INTEL_KBL)                 \ | ||||||
|     LINE(INTEL_CFL)                 \ |     LINE(INTEL_CFL)                 \ | ||||||
|     LINE(INTEL_WHL)                 \ |     LINE(INTEL_WHL)                 \ | ||||||
|  |     LINE(INTEL_CML)                 \ | ||||||
|     LINE(INTEL_CNL)                 \ |     LINE(INTEL_CNL)                 \ | ||||||
|     LINE(INTEL_ICL)                 \ |     LINE(INTEL_ICL)                 \ | ||||||
|     LINE(INTEL_TGL)                 \ |     LINE(INTEL_TGL)                 \ | ||||||
|   | |||||||
		Reference in New Issue
	
	Block a user
	 Carles Fernandez
					Carles Fernandez