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Code Issues Releases Wiki Activity

coding style + removed some unnecessary memory arrays in the FPGA E5A tracking adapter class.

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This commit is contained in:
Marc Majoral
2019-02-27 17:27:31 +01:00
parent 484b0f4b02
commit c32e0b427a
25 changed files with 1388 additions and 1535 deletions
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31
src/algorithms/tracking/adapters/galileo_e5a_dll_pll_tracking_fpga.cc
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@@ -55,7 +55,6 @@ GalileoE5aDllPllTrackingFpga::GalileoE5aDllPllTrackingFpga(
ConfigurationInterface *configuration, const std::string &role,
unsigned int in_streams, unsigned int out_streams) : role_(role), in_streams_(in_streams), out_streams_(out_streams)
{
Dll_Pll_Conf_Fpga trk_param_fpga = Dll_Pll_Conf_Fpga();
DLOG(INFO) << "role " << role;
//################# CONFIGURATION PARAMETERS ########################
@@ -138,15 +137,6 @@ GalileoE5aDllPllTrackingFpga::GalileoE5aDllPllTrackingFpga(
auto *aux_code = static_cast<gr_complex *>(volk_gnsssdr_malloc(sizeof(gr_complex) * code_length_chips * code_samples_per_chip, volk_gnsssdr_get_alignment()));
float *tracking_code;
float *data_code;
if (trk_param_fpga.track_pilot)
{
data_code = static_cast<float *>(volk_gnsssdr_malloc(code_samples_per_chip * code_length_chips * sizeof(float), volk_gnsssdr_get_alignment()));
}
tracking_code = static_cast<float *>(volk_gnsssdr_malloc(code_samples_per_chip * code_length_chips * sizeof(float), volk_gnsssdr_get_alignment()));
d_ca_codes = static_cast<int32_t *>(volk_gnsssdr_malloc(static_cast<int32_t>(code_length_chips) * code_samples_per_chip * GALILEO_E5A_NUMBER_OF_CODES * sizeof(int32_t), volk_gnsssdr_get_alignment()));
if (trk_param_fpga.track_pilot)
@@ -160,37 +150,22 @@ GalileoE5aDllPllTrackingFpga::GalileoE5aDllPllTrackingFpga(
galileo_e5_a_code_gen_complex_primary(aux_code, PRN, const_cast<char *>(sig_));
if (trk_param_fpga.track_pilot)
{
for (uint32_t i = 0; i < code_length_chips; i++)
{
tracking_code[i] = aux_code[i].imag();
data_code[i] = aux_code[i].real();
}
for (uint32_t s = 0; s < code_length_chips; s++)
{
d_ca_codes[static_cast<int32_t>(code_length_chips) * (PRN - 1) + s] = static_cast<int32_t>(tracking_code[s]);
d_data_codes[static_cast<int32_t>(code_length_chips) * (PRN - 1) + s] = static_cast<int32_t>(data_code[s]);
d_ca_codes[static_cast<int32_t>(code_length_chips) * (PRN - 1) + s] = static_cast<int32_t>(aux_code[s].imag());
d_data_codes[static_cast<int32_t>(code_length_chips) * (PRN - 1) + s] = static_cast<int32_t>(aux_code[s].real());
}
}
else
{
for (uint32_t i = 0; i < code_length_chips; i++)
{
tracking_code[i] = aux_code[i].real();
}
for (uint32_t s = 0; s < code_length_chips; s++)
{
d_ca_codes[static_cast<int32_t>(code_length_chips) * (PRN - 1) + s] = static_cast<int32_t>(tracking_code[s]);
d_ca_codes[static_cast<int32_t>(code_length_chips) * (PRN - 1) + s] = static_cast<int32_t>(aux_code[s].real());
}
}
}
volk_gnsssdr_free(aux_code);
volk_gnsssdr_free(tracking_code);
if (trk_param_fpga.track_pilot)
{
volk_gnsssdr_free(data_code);
}
trk_param_fpga.ca_codes = d_ca_codes;
trk_param_fpga.data_codes = d_data_codes;
trk_param_fpga.code_length_chips = code_length_chips;

2
src/algorithms/tracking/adapters/gps_l5_dll_pll_tracking_fpga.cc
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@@ -153,7 +153,7 @@ GpsL5DllPllTrackingFpga::GpsL5DllPllTrackingFpga(
for (uint32_t PRN = 1; PRN <= NUM_PRNs; PRN++)
{
if (track_pilot)
if (trk_param_fpga.track_pilot)
{
gps_l5q_code_gen_float(tracking_code, PRN);
gps_l5i_code_gen_float(data_code, PRN);

117
src/algorithms/tracking/gnuradio_blocks/dll_pll_veml_tracking_fpga.cc
View File

@@ -36,21 +36,21 @@
*/
#include "dll_pll_veml_tracking_fpga.h"
#include "tracking_discriminators.h"
#include "lock_detectors.h"
#include "control_message_factory.h"
#include "MATH_CONSTANTS.h"
#include "Galileo_E1.h"
#include "galileo_e1_signal_processing.h"
#include "Galileo_E5a.h"
#include "galileo_e5_signal_processing.h"
#include "GPS_L1_CA.h"
#include "gps_sdr_signal_processing.h"
#include "GPS_L2C.h"
#include "gps_l2c_signal.h"
#include "GPS_L5.h"
#include "gps_l5_signal.h"
#include "Galileo_E1.h"
#include "Galileo_E5a.h"
#include "MATH_CONSTANTS.h"
#include "control_message_factory.h"
#include "galileo_e1_signal_processing.h"
#include "galileo_e5_signal_processing.h"
#include "gnss_sdr_create_directory.h"
#include "gps_l2c_signal.h"
#include "gps_l5_signal.h"
#include "gps_sdr_signal_processing.h"
#include "lock_detectors.h"
#include "tracking_discriminators.h"
#include <boost/filesystem/path.hpp>
#include <glog/logging.h>
#include <gnuradio/io_signature.h>
@@ -60,8 +60,8 @@
#include <cmath>
#include <exception>
#include <iostream>
#include <sstream>
#include <numeric>
#include <sstream>
using google::LogMessage;
@@ -72,7 +72,7 @@ dll_pll_veml_tracking_fpga_sptr dll_pll_veml_make_tracking_fpga(const Dll_Pll_Co
dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &conf_) : gr::block("dll_pll_veml_tracking_fpga", gr::io_signature::make(0, 0, sizeof(lv_16sc_t)),
gr::io_signature::make(1, 1, sizeof(Gnss_Synchro)))
gr::io_signature::make(1, 1, sizeof(Gnss_Synchro)))
{
trk_parameters = conf_;
// Telemetry bit synchronization message port input
@@ -326,7 +326,7 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
trk_parameters.extend_correlation_symbols = 1;
}
// --- Initializations ---
// --- Initializations ---
// Initial code frequency basis of NCO
d_code_freq_chips = d_code_chip_rate;
// Residual code phase (in chips)
@@ -423,14 +423,11 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
uint32_t multicorr_type = trk_parameters.multicorr_type;
multicorrelator_fpga = std::make_shared<fpga_multicorrelator_8sc>(d_n_correlator_taps, device_name, device_base, ca_codes, data_codes, d_code_length_chips, trk_parameters.track_pilot, multicorr_type, d_code_samples_per_chip);
multicorrelator_fpga->set_output_vectors(d_correlator_outs, d_Prompt_Data);
}
void dll_pll_veml_tracking_fpga::start_tracking()
{
// correct the code phase according to the delay between acq and trk
d_acq_code_phase_samples = d_acquisition_gnss_synchro->Acq_delay_samples;
d_acq_carrier_doppler_hz = d_acquisition_gnss_synchro->Acq_doppler_hz;
@@ -508,7 +505,6 @@ void dll_pll_veml_tracking_fpga::start_tracking()
d_cloop = true;
d_Prompt_buffer_deque.clear();
d_last_prompt = gr_complex(0.0, 0.0);
}
@@ -553,13 +549,11 @@ dll_pll_veml_tracking_fpga::~dll_pll_veml_tracking_fpga()
{
LOG(WARNING) << "Exception in destructor " << ex.what();
}
}
bool dll_pll_veml_tracking_fpga::acquire_secondary()
{
// ******* preamble correlation ********
int32_t corr_value = 0;
for (uint32_t i = 0; i < d_secondary_code_length; i++)
@@ -596,13 +590,11 @@ bool dll_pll_veml_tracking_fpga::acquire_secondary()
{
return false;
}
}
bool dll_pll_veml_tracking_fpga::cn0_and_tracking_lock_status(double coh_integration_time_s)
{
// ####### CN0 ESTIMATION AND LOCK DETECTORS ######
if (d_cn0_estimation_counter < trk_parameters.cn0_samples)
@@ -642,7 +634,6 @@ bool dll_pll_veml_tracking_fpga::cn0_and_tracking_lock_status(double coh_integra
return true;
}
}
}
@@ -654,25 +645,20 @@ bool dll_pll_veml_tracking_fpga::cn0_and_tracking_lock_status(double coh_integra
//void dll_pll_veml_tracking_fpga::do_correlation_step(const gr_complex *input_samples)
void dll_pll_veml_tracking_fpga::do_correlation_step(void)
{
// // ################# CARRIER WIPEOFF AND CORRELATORS ##############################
// // ################# CARRIER WIPEOFF AND CORRELATORS ##############################
multicorrelator_fpga->Carrier_wipeoff_multicorrelator_resampler(
multicorrelator_fpga->Carrier_wipeoff_multicorrelator_resampler(
d_rem_carr_phase_rad,
d_carrier_phase_step_rad, d_carrier_phase_rate_step_rad,
static_cast<float>(d_rem_code_phase_chips) * static_cast<float>(d_code_samples_per_chip),
static_cast<float>(d_code_phase_step_chips) * static_cast<float>(d_code_samples_per_chip),
static_cast<float>(d_code_phase_rate_step_chips) * static_cast<float>(d_code_samples_per_chip),
d_carrier_phase_step_rad, d_carrier_phase_rate_step_rad,
static_cast<float>(d_rem_code_phase_chips) * static_cast<float>(d_code_samples_per_chip),
static_cast<float>(d_code_phase_step_chips) * static_cast<float>(d_code_samples_per_chip),
static_cast<float>(d_code_phase_rate_step_chips) * static_cast<float>(d_code_samples_per_chip),
d_current_prn_length_samples);
}
void dll_pll_veml_tracking_fpga::run_dll_pll()
{
// ################## PLL ##########################################################
// PLL discriminator
if (d_cloop)
@@ -707,13 +693,11 @@ void dll_pll_veml_tracking_fpga::run_dll_pll()
// New code Doppler frequency estimation
d_code_freq_chips = (1.0 + (d_carrier_doppler_hz / d_signal_carrier_freq)) * d_code_chip_rate - d_code_error_filt_chips;
}
void dll_pll_veml_tracking_fpga::clear_tracking_vars()
{
std::fill_n(d_correlator_outs, d_n_correlator_taps, gr_complex(0.0, 0.0));
if (trk_parameters.track_pilot) d_Prompt_Data[0] = gr_complex(0.0, 0.0);
d_carr_error_hz = 0.0;
@@ -727,13 +711,11 @@ void dll_pll_veml_tracking_fpga::clear_tracking_vars()
d_code_phase_rate_step_chips = 0.0;
d_carr_ph_history.clear();
d_code_ph_history.clear();
}
void dll_pll_veml_tracking_fpga::update_tracking_vars()
{
T_chip_seconds = 1.0 / d_code_freq_chips;
T_prn_seconds = T_chip_seconds * static_cast<double>(d_code_length_chips);
@@ -800,13 +782,11 @@ void dll_pll_veml_tracking_fpga::update_tracking_vars()
// remnant code phase [chips]
d_rem_code_phase_samples = K_blk_samples - static_cast<double>(d_current_prn_length_samples); // rounding error < 1 sample
d_rem_code_phase_chips = d_code_freq_chips * d_rem_code_phase_samples / trk_parameters.fs_in;
}
void dll_pll_veml_tracking_fpga::save_correlation_results()
{
if (d_secondary)
{
if (d_secondary_code_string->at(d_current_symbol) == '0')
@@ -853,13 +833,11 @@ void dll_pll_veml_tracking_fpga::save_correlation_results()
d_cloop = false;
else
d_cloop = true;
}
void dll_pll_veml_tracking_fpga::log_data(bool integrating)
{
if (d_dump)
{
// Dump results to file
@@ -980,13 +958,11 @@ void dll_pll_veml_tracking_fpga::log_data(bool integrating)
LOG(WARNING) << "Exception writing trk dump file " << e.what();
}
}
}
int32_t dll_pll_veml_tracking_fpga::save_matfile()
{
// READ DUMP FILE
std::ifstream::pos_type size;
int32_t number_of_double_vars = 1;
@@ -1228,13 +1204,11 @@ int32_t dll_pll_veml_tracking_fpga::save_matfile()
delete[] aux2;
delete[] PRN;
return 0;
}
void dll_pll_veml_tracking_fpga::set_channel(uint32_t channel)
{
d_channel = channel;
multicorrelator_fpga->set_channel(d_channel);
LOG(INFO) << "Tracking Channel set to " << d_channel;
@@ -1261,7 +1235,6 @@ void dll_pll_veml_tracking_fpga::set_channel(uint32_t channel)
}
}
}
}
@@ -1279,8 +1252,6 @@ void dll_pll_veml_tracking_fpga::stop_tracking()
int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((unused)), gr_vector_int &ninput_items,
gr_vector_const_void_star &input_items, gr_vector_void_star &output_items)
{
Gnss_Synchro **out = reinterpret_cast<Gnss_Synchro **>(&output_items[0]);
Gnss_Synchro current_synchro_data = Gnss_Synchro();
@@ -1296,33 +1267,33 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
}
case 1: // Pull-in
{
int64_t acq_trk_diff_samples;
double acq_trk_diff_seconds;
double delta_trk_to_acq_prn_start_samples;
int64_t acq_trk_diff_samples;
double acq_trk_diff_seconds;
double delta_trk_to_acq_prn_start_samples;
multicorrelator_fpga->lock_channel();
uint64_t counter_value = multicorrelator_fpga->read_sample_counter();
uint64_t absolute_samples_offset;
if (counter_value > (d_acq_sample_stamp + d_acq_code_phase_samples))
{
// Signal alignment (skip samples until the incoming signal is aligned with local replica)
acq_trk_diff_samples = static_cast<int64_t>(counter_value) - static_cast<int64_t>(d_acq_sample_stamp);
acq_trk_diff_seconds = static_cast<double>(acq_trk_diff_samples) / trk_parameters.fs_in;
delta_trk_to_acq_prn_start_samples = static_cast<double>(acq_trk_diff_samples) - d_acq_code_phase_samples;
{
// Signal alignment (skip samples until the incoming signal is aligned with local replica)
acq_trk_diff_samples = static_cast<int64_t>(counter_value) - static_cast<int64_t>(d_acq_sample_stamp);
acq_trk_diff_seconds = static_cast<double>(acq_trk_diff_samples) / trk_parameters.fs_in;
delta_trk_to_acq_prn_start_samples = static_cast<double>(acq_trk_diff_samples) - d_acq_code_phase_samples;
uint32_t num_frames = ceil((delta_trk_to_acq_prn_start_samples) / d_correlation_length_samples);
absolute_samples_offset = static_cast<uint64_t>(d_acq_code_phase_samples + d_acq_sample_stamp + num_frames * d_correlation_length_samples);
}
uint32_t num_frames = ceil((delta_trk_to_acq_prn_start_samples) / d_correlation_length_samples);
absolute_samples_offset = static_cast<uint64_t>(d_acq_code_phase_samples + d_acq_sample_stamp + num_frames * d_correlation_length_samples);
}
else
{
// test mode
{
// test mode
acq_trk_diff_samples = - static_cast<int64_t>(counter_value) + static_cast<int64_t>(d_acq_sample_stamp);
acq_trk_diff_seconds = static_cast<double>(acq_trk_diff_samples) / trk_parameters.fs_in;
delta_trk_to_acq_prn_start_samples = static_cast<double>(acq_trk_diff_samples) + d_acq_code_phase_samples;
acq_trk_diff_samples = -static_cast<int64_t>(counter_value) + static_cast<int64_t>(d_acq_sample_stamp);
acq_trk_diff_seconds = static_cast<double>(acq_trk_diff_samples) / trk_parameters.fs_in;
delta_trk_to_acq_prn_start_samples = static_cast<double>(acq_trk_diff_samples) + d_acq_code_phase_samples;
absolute_samples_offset = static_cast<uint64_t>(delta_trk_to_acq_prn_start_samples);
}
absolute_samples_offset = static_cast<uint64_t>(delta_trk_to_acq_prn_start_samples);
}
multicorrelator_fpga->set_initial_sample(absolute_samples_offset);
d_absolute_samples_offset = absolute_samples_offset;
d_sample_counter = absolute_samples_offset;
@@ -1357,13 +1328,12 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
// don't leave the HW module blocking the signal path before the first sample arrives
// start the first tracking process
run_state_2(current_synchro_data);
run_state_2(current_synchro_data);
break;
}
case 2: // Wide tracking and symbol synchronization
{
run_state_2(current_synchro_data);
run_state_2(current_synchro_data);
break;
}
case 3: // coherent integration (correlation time extension)
@@ -1497,9 +1467,9 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
if (current_synchro_data.Flag_valid_symbol_output)
{
current_synchro_data.fs = static_cast<int64_t>(trk_parameters.fs_in);
// two choices for the reporting of the sample counter:
// either the sample counter position that should be (d_sample_counter_next)
//or the sample counter corresponding to the number of samples that the FPGA actually consumed.
// two choices for the reporting of the sample counter:
// either the sample counter position that should be (d_sample_counter_next)
//or the sample counter corresponding to the number of samples that the FPGA actually consumed.
current_synchro_data.Tracking_sample_counter = d_sample_counter_next;
*out[0] = current_synchro_data;
return 1;
@@ -1678,7 +1648,6 @@ void dll_pll_veml_tracking_fpga::run_state_2(Gnss_Synchro &current_synchro_data)
}
}
}
}

1
src/algorithms/tracking/gnuradio_blocks/dll_pll_veml_tracking_fpga.h
View File

@@ -44,7 +44,6 @@
#include <map>
#include <queue>
#include <utility>
#include <boost/circular_buffer.hpp>
//#include <string>
class dll_pll_veml_tracking_fpga;

4
src/algorithms/tracking/libs/dll_pll_conf_fpga.cc
View File

@@ -37,8 +37,8 @@
Dll_Pll_Conf_Fpga::Dll_Pll_Conf_Fpga()
{
/* DLL/PLL tracking configuration */
high_dyn = false;
smoother_length = 10;
high_dyn = false;
smoother_length = 10;
fs_in = 0.0;
vector_length = 0U;
dump = false;

69
src/algorithms/tracking/libs/fpga_multicorrelator.cc
View File

@@ -35,40 +35,36 @@
*/
#include "fpga_multicorrelator.h"
#include <cmath>
#include <new>
#include <cerrno>
#include <cstdio>
#include <fcntl.h>
#include <unistd.h>
#include <glog/logging.h>
#include <cassert>
#include <cerrno>
#include <cmath>
#include <csignal>
#include <cstdint>
#include <cstdio>
#include <cstdlib>
#include <fcntl.h>
#include <new>
#include <string>
#include <sys/mman.h>
#include <sys/stat.h>
#include <unistd.h>
#include <csignal>
#include <cstdlib>
#include <sys/mman.h>
#include <glog/logging.h>
#include <string>
#include <utility>
// FPGA register access constants
#define PAGE_SIZE 0x10000
#define MAX_LENGTH_DEVICEIO_NAME 50
#define CODE_RESAMPLER_NUM_BITS_PRECISION 20
#define CODE_PHASE_STEP_CHIPS_NUM_NBITS CODE_RESAMPLER_NUM_BITS_PRECISION
#define pwrtwo(x) (1 << (x))
#define MAX_CODE_RESAMPLER_COUNTER pwrtwo(CODE_PHASE_STEP_CHIPS_NUM_NBITS) // 2^CODE_PHASE_STEP_CHIPS_NUM_NBITS
#define PHASE_CARR_NBITS 32
#define PHASE_CARR_NBITS_INT 1
#define PHASE_CARR_NBITS_FRAC PHASE_CARR_NBITS - PHASE_CARR_NBITS_INT
#define LOCAL_CODE_FPGA_CORRELATOR_SELECT_COUNT 0x20000000
#define LOCAL_CODE_FPGA_CLEAR_ADDRESS_COUNTER 0x10000000
#define LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY 0x0C000000
#define TEST_REGISTER_TRACK_WRITEVAL 0x55AA
#define PAGE_SIZE 0x10000
#define MAX_LENGTH_DEVICEIO_NAME 50
#define CODE_RESAMPLER_NUM_BITS_PRECISION 20
#define CODE_PHASE_STEP_CHIPS_NUM_NBITS CODE_RESAMPLER_NUM_BITS_PRECISION
#define pwrtwo(x) (1 << (x))
#define MAX_CODE_RESAMPLER_COUNTER pwrtwo(CODE_PHASE_STEP_CHIPS_NUM_NBITS) // 2^CODE_PHASE_STEP_CHIPS_NUM_NBITS
#define PHASE_CARR_NBITS 32
#define PHASE_CARR_NBITS_INT 1
#define PHASE_CARR_NBITS_FRAC PHASE_CARR_NBITS - PHASE_CARR_NBITS_INT
#define LOCAL_CODE_FPGA_CORRELATOR_SELECT_COUNT 0x20000000
#define LOCAL_CODE_FPGA_CLEAR_ADDRESS_COUNTER 0x10000000
#define LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY 0x0C000000
#define TEST_REGISTER_TRACK_WRITEVAL 0x55AA
uint64_t fpga_multicorrelator_8sc::read_sample_counter()
@@ -111,9 +107,9 @@ void fpga_multicorrelator_8sc::update_local_code(float rem_code_phase_chips)
void fpga_multicorrelator_8sc::Carrier_wipeoff_multicorrelator_resampler(
float rem_carrier_phase_in_rad, float phase_step_rad,
float carrier_phase_rate_step_rad,
float carrier_phase_rate_step_rad,
float rem_code_phase_chips, float code_phase_step_chips,
float code_phase_rate_step_chips,
float code_phase_rate_step_chips,
int32_t signal_length_samples)
{
update_local_code(rem_code_phase_chips);
@@ -130,7 +126,7 @@ void fpga_multicorrelator_8sc::Carrier_wipeoff_multicorrelator_resampler(
if (nb != sizeof(irq_count))
{
std::cout << "Tracking_module Read failed to retrieve 4 bytes!" << std::endl;
std::cout << "Tracking_module Interrupt number " << irq_count << std::endl;
std::cout << "Tracking_module Interrupt number " << irq_count << std::endl;
}
fpga_multicorrelator_8sc::read_tracking_gps_results();
}
@@ -294,7 +290,6 @@ void fpga_multicorrelator_8sc::fpga_configure_tracking_gps_local_code(int32_t PR
}
if (d_track_pilot)
{
d_map_base[PROG_MEMS_ADDR] = LOCAL_CODE_FPGA_CLEAR_ADDRESS_COUNTER;
for (k = 0; k < d_code_length_chips * d_code_samples_per_chip; k++)
{
@@ -410,7 +405,6 @@ void fpga_multicorrelator_8sc::fpga_compute_signal_parameters_in_fpga(void)
{
d_phase_step_rad_int = -d_phase_step_rad_int;
}
}
@@ -451,9 +445,9 @@ void fpga_multicorrelator_8sc::read_tracking_gps_results(void)
}
if (d_track_pilot)
{
readval_real = d_map_base[RESULT_REG_REAL_BASE_ADDR + d_n_correlators];
readval_imag = d_map_base[RESULT_REG_IMAG_BASE_ADDR + d_n_correlators];
d_Prompt_Data[0] = gr_complex(readval_real, readval_imag);
readval_real = d_map_base[RESULT_REG_REAL_BASE_ADDR + d_n_correlators];
readval_imag = d_map_base[RESULT_REG_IMAG_BASE_ADDR + d_n_correlators];
d_Prompt_Data[0] = gr_complex(readval_real, readval_imag);
}
}
@@ -461,8 +455,8 @@ void fpga_multicorrelator_8sc::read_tracking_gps_results(void)
void fpga_multicorrelator_8sc::unlock_channel(void)
{
// unlock the channel to let the next samples go through
d_map_base[DROP_SAMPLES_REG_ADDR] = 1; // unlock the channel
d_map_base[STOP_TRACKING_REG_ADDR] = 1; // set the tracking module back to idle
d_map_base[DROP_SAMPLES_REG_ADDR] = 1; // unlock the channel
d_map_base[STOP_TRACKING_REG_ADDR] = 1; // set the tracking module back to idle
}
void fpga_multicorrelator_8sc::close_device()
@@ -481,4 +475,3 @@ void fpga_multicorrelator_8sc::lock_channel(void)
// lock the channel for processing
d_map_base[DROP_SAMPLES_REG_ADDR] = 0; // lock the channel
}

52
src/algorithms/tracking/libs/fpga_multicorrelator.h
View File

@@ -44,27 +44,26 @@
// FPGA register addresses
// write addresses
#define CODE_PHASE_STEP_CHIPS_NUM_REG_ADDR 0
#define INITIAL_INDEX_REG_BASE_ADDR 1
#define INITIAL_INTERP_COUNTER_REG_BASE_ADDR 7
#define NSAMPLES_MINUS_1_REG_ADDR 13
#define CODE_LENGTH_MINUS_1_REG_ADDR 14
#define REM_CARR_PHASE_RAD_REG_ADDR 15
#define PHASE_STEP_RAD_REG_ADDR 16
#define PROG_MEMS_ADDR 17
#define DROP_SAMPLES_REG_ADDR 18
#define INITIAL_COUNTER_VALUE_REG_ADDR_LSW 19
#define INITIAL_COUNTER_VALUE_REG_ADDR_MSW 20
#define STOP_TRACKING_REG_ADDR 23
#define START_FLAG_ADDR 30
#define CODE_PHASE_STEP_CHIPS_NUM_REG_ADDR 0
#define INITIAL_INDEX_REG_BASE_ADDR 1
#define INITIAL_INTERP_COUNTER_REG_BASE_ADDR 7
#define NSAMPLES_MINUS_1_REG_ADDR 13
#define CODE_LENGTH_MINUS_1_REG_ADDR 14
#define REM_CARR_PHASE_RAD_REG_ADDR 15
#define PHASE_STEP_RAD_REG_ADDR 16
#define PROG_MEMS_ADDR 17
#define DROP_SAMPLES_REG_ADDR 18
#define INITIAL_COUNTER_VALUE_REG_ADDR_LSW 19
#define INITIAL_COUNTER_VALUE_REG_ADDR_MSW 20
#define STOP_TRACKING_REG_ADDR 23
#define START_FLAG_ADDR 30
// read-write addresses
#define TEST_REG_ADDR 31
#define TEST_REG_ADDR 31
// read addresses
#define RESULT_REG_REAL_BASE_ADDR 1
#define RESULT_REG_IMAG_BASE_ADDR 7
#define SAMPLE_COUNTER_REG_ADDR_LSW 13
#define SAMPLE_COUNTER_REG_ADDR_MSW 14
#define RESULT_REG_REAL_BASE_ADDR 1
#define RESULT_REG_IMAG_BASE_ADDR 7
#define SAMPLE_COUNTER_REG_ADDR_LSW 13
#define SAMPLE_COUNTER_REG_ADDR_MSW 14
/*!
@@ -74,18 +73,18 @@ class fpga_multicorrelator_8sc
{
public:
fpga_multicorrelator_8sc(int32_t n_correlators, std::string device_name,
uint32_t device_base, int32_t *ca_codes, int32_t *data_codes, uint32_t code_length_chips, bool track_pilot, uint32_t multicorr_type, uint32_t code_samples_per_chip);
uint32_t device_base, int32_t *ca_codes, int32_t *data_codes, uint32_t code_length_chips, bool track_pilot, uint32_t multicorr_type, uint32_t code_samples_per_chip);
~fpga_multicorrelator_8sc();
void set_output_vectors(gr_complex *corr_out, gr_complex *Prompt_Data);
void set_local_code_and_taps(
float *shifts_chips, float *prompt_data_shift, int32_t PRN);
float *shifts_chips, float *prompt_data_shift, int32_t PRN);
void update_local_code(float rem_code_phase_chips);
void Carrier_wipeoff_multicorrelator_resampler(
float rem_carrier_phase_in_rad, float phase_step_rad,
float carrier_phase_rate_step_rad,
float rem_code_phase_chips, float code_phase_step_chips,
float code_phase_rate_step_chips,
int32_t signal_length_samples);
float rem_carrier_phase_in_rad, float phase_step_rad,
float carrier_phase_rate_step_rad,
float rem_code_phase_chips, float code_phase_step_chips,
float code_phase_rate_step_chips,
int32_t signal_length_samples);
bool free();
void set_channel(uint32_t channel);
void set_initial_sample(uint64_t samples_offset);
@@ -144,7 +143,6 @@ private:
void fpga_launch_multicorrelator_fpga(void);
void read_tracking_gps_results(void);
void close_device(void);
};
#endif /* GNSS_SDR_FPGA_MULTICORRELATOR_H_ */