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Add some MIPS features
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@ -11,11 +11,20 @@ CPU_FEATURES_START_CPP_NAMESPACE
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typedef struct
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{
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int msa : 1; // MIPS SIMD Architecture
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// https://www.mips.com/products/architectures/ase/simd/
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int eva : 1; // Enhanced Virtual Addressing
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// https://www.mips.com/products/architectures/mips64/
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int r6 : 1; // True if is release 6 of the processor.
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int msa : 1; // MIPS SIMD Architecture
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// https://www.mips.com/products/architectures/ase/simd/
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int eva : 1; // Enhanced Virtual Addressing
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// https://www.mips.com/products/architectures/mips64/
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int r6 : 1; // True if is release 6 of the processor.
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int mips16 : 1; // Compressed instructions
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int mdmx : 1; // MIPS Digital Media Extension
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int mips3d : 1; // 3D graphics acceleration
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// MIPS(r) Architecture for Programmers, Volume IV-c
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int smart : 1; // Smart-card cryptography
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// MIPS(r) Architecture for Programmers, Volume IV-d
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int dsp : 1; // Digital Signal Processing
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// MIPS(r) Architecture for Programmers, Volume IV-e
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// https://www.mips.com/products/architectures/ase/dsp/
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// Make sure to update MipsFeaturesEnum below if you add a field here.
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} MipsFeatures;
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@ -35,6 +44,11 @@ typedef enum
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MIPS_MSA,
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MIPS_EVA,
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MIPS_R6,
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MIPS_MIPS16,
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MIPS_MDMX,
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MIPS_MIPS3D,
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MIPS_SMART,
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MIPS_DSP,
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MIPS_LAST_,
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} MipsFeaturesEnum;
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@ -105,6 +105,13 @@ CPU_FEATURES_START_CPP_NAMESPACE
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#define MIPS_HWCAP_R6 (1UL << 0)
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#define MIPS_HWCAP_MSA (1UL << 1)
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#define MIPS_HWCAP_CRC32 (1UL << 2)
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#define MIPS_HWCAP_MIPS16 (1UL << 3)
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#define MIPS_HWCAP_MDMX (1UL << 4)
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#define MIPS_HWCAP_MIPS3D (1UL << 5)
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#define MIPS_HWCAP_SMARTMIPS (1UL << 6)
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#define MIPS_HWCAP_DSP (1UL << 7)
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#define MIPS_HWCAP_DSP2 (1UL << 8)
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#define MIPS_HWCAP_DSP3 (1UL << 9)
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// http://elixir.free-electrons.com/linux/latest/source/arch/powerpc/include/uapi/asm/cputable.h
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#ifndef _UAPI__ASM_POWERPC_CPUTABLE_H
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@ -11,10 +11,15 @@
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////////////////////////////////////////////////////////////////////////////////
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// Definitions for introspection.
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////////////////////////////////////////////////////////////////////////////////
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#define INTROSPECTION_TABLE \
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LINE(MIPS_MSA, msa, "msa", MIPS_HWCAP_MSA, 0) \
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LINE(MIPS_EVA, eva, "eva", 0, 0) \
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LINE(MIPS_R6, r6, "r6", MIPS_HWCAP_R6, 0)
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#define INTROSPECTION_TABLE \
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LINE(MIPS_MSA, msa, "msa", MIPS_HWCAP_MSA, 0) \
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LINE(MIPS_EVA, eva, "eva", 0, 0) \
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LINE(MIPS_R6, r6, "r6", MIPS_HWCAP_R6, 0) \
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LINE(MIPS_MIPS16, mips16, "mips16", MIPS_HWCAP_MIPS16, 0) \
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LINE(MIPS_MDMX, mdmx, "mdmx", MIPS_HWCAP_MDMX, 0) \
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LINE(MIPS_MIPS3D, mips3d, "mips3d", MIPS_HWCAP_MIPS3D, 0) \
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LINE(MIPS_SMART, smart, "smartmips", MIPS_HWCAP_SMARTMIPS, 0) \
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LINE(MIPS_DSP, dsp, "dsp", MIPS_HWCAP_DSP, 0)
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#define INTROSPECTION_PREFIX Mips
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#define INTROSPECTION_ENUM_PREFIX MIPS
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#include "define_introspection_and_hwcaps.inl"
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@ -60,6 +60,12 @@ VPE : 0
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const auto info = GetMipsInfo();
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EXPECT_FALSE(info.features.msa);
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EXPECT_TRUE(info.features.eva);
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EXPECT_FALSE(info.features.r6);
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EXPECT_TRUE(info.features.mips16);
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EXPECT_FALSE(info.features.mdmx);
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EXPECT_FALSE(info.features.mips3d);
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EXPECT_FALSE(info.features.smart);
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EXPECT_TRUE(info.features.dsp);
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}
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TEST(CpuinfoMipsTest, AR7161)
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@ -87,6 +93,7 @@ VCEI exceptions : not available
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const auto info = GetMipsInfo();
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EXPECT_FALSE(info.features.msa);
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EXPECT_FALSE(info.features.eva);
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EXPECT_TRUE(info.features.mips16);
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}
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TEST(CpuinfoMipsTest, Goldfish)
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@ -115,5 +122,37 @@ VCEI exceptions : not available
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EXPECT_FALSE(info.features.eva);
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}
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TEST(CpuinfoMipsTest, BCM1250)
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{
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ResetHwcaps();
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auto& fs = GetEmptyFilesystem();
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fs.CreateFile("/proc/cpuinfo", R"(system type : SiByte BCM91250A (SWARM)
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processor : 0
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cpu model : SiByte SB1 V0.2 FPU V0.2
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BogoMIPS : 532.48
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wait instruction : no
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microsecond timers : yes
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tlb_entries : 64
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extra interrupt vector : yes
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hardware watchpoint : yes, count: 1, address/irw mask: [0x0ff8]
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isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2
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ASEs implemented : mdmx mips3d
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shadow register sets : 1
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kscratch registers : 0
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package : 0
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core : 0
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VCED exceptions : not available
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VCEI exceptions : not available
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)");
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const auto info = GetMipsInfo();
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EXPECT_FALSE(info.features.msa);
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EXPECT_FALSE(info.features.eva);
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EXPECT_FALSE(info.features.mips16);
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EXPECT_TRUE(info.features.mdmx);
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EXPECT_TRUE(info.features.mips3d);
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EXPECT_FALSE(info.features.smart);
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EXPECT_FALSE(info.features.dsp);
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}
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} // namespace
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} // namespace cpu_features
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