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https://github.com/gnss-sdr/gnss-sdr
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Added optional support for Sparkfun SiGe GN3S USB GPS RF sampler:
- Added a pre-compiled custom GN3S firmware. - Added a fully-compliant GNU Radio source block for GN3S USB dongle. It can be used also from GNU Radio companion and from Python applications. - Added a new GN3S_Signal_Source block. It is possible to disable the GN3S signal source compilation. See README. git-svn-id: https://svn.code.sf.net/p/gnss-sdr/code/trunk@217 64b25241-fba3-4117-9849-534c7e92360d
This commit is contained in:
Javier Arribas
179
firmware/GN3S_v2/lib/delay.lst
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179
firmware/GN3S_v2/lib/delay.lst
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1 ;--------------------------------------------------------
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2 ; File Created by SDCC : free open source ANSI-C Compiler
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3 ; Version 2.9.0 #5416 (Feb 3 2010) (UNIX)
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4 ; This file was generated Mon Jul 30 11:40:52 2012
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5 ;--------------------------------------------------------
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6 .module delay
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7 .optsdcc -mmcs51 --model-small
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8
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9 ;--------------------------------------------------------
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10 ; Public variables in this module
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11 ;--------------------------------------------------------
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12 .globl _mdelay
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13 .globl _udelay
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14 ;--------------------------------------------------------
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15 ; special function registers
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16 ;--------------------------------------------------------
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17 .area RSEG (DATA)
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18 ;--------------------------------------------------------
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19 ; special function bits
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20 ;--------------------------------------------------------
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21 .area RSEG (DATA)
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22 ;--------------------------------------------------------
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23 ; overlayable register banks
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24 ;--------------------------------------------------------
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25 .area REG_BANK_0 (REL,OVR,DATA)
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0000 26 .ds 8
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27 ;--------------------------------------------------------
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28 ; internal ram data
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29 ;--------------------------------------------------------
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30 .area DSEG (DATA)
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31 ;--------------------------------------------------------
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32 ; overlayable items in internal ram
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33 ;--------------------------------------------------------
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34 .area OSEG (OVR,DATA)
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35 ;--------------------------------------------------------
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36 ; indirectly addressable internal ram data
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37 ;--------------------------------------------------------
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38 .area ISEG (DATA)
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39 ;--------------------------------------------------------
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40 ; absolute internal ram data
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41 ;--------------------------------------------------------
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42 .area IABS (ABS,DATA)
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43 .area IABS (ABS,DATA)
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44 ;--------------------------------------------------------
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45 ; bit data
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46 ;--------------------------------------------------------
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47 .area BSEG (BIT)
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48 ;--------------------------------------------------------
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49 ; paged external ram data
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50 ;--------------------------------------------------------
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51 .area PSEG (PAG,XDATA)
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52 ;--------------------------------------------------------
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53 ; external ram data
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54 ;--------------------------------------------------------
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55 .area XSEG (XDATA)
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56 ;--------------------------------------------------------
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57 ; absolute external ram data
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58 ;--------------------------------------------------------
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59 .area XABS (ABS,XDATA)
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60 ;--------------------------------------------------------
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61 ; external initialized ram data
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62 ;--------------------------------------------------------
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63 .area HOME (CODE)
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64 .area GSINIT0 (CODE)
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65 .area GSINIT1 (CODE)
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66 .area GSINIT2 (CODE)
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67 .area GSINIT3 (CODE)
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68 .area GSINIT4 (CODE)
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69 .area GSINIT5 (CODE)
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70 .area GSINIT (CODE)
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71 .area GSFINAL (CODE)
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72 .area CSEG (CODE)
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73 ;--------------------------------------------------------
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74 ; global & static initialisations
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75 ;--------------------------------------------------------
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76 .area HOME (CODE)
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77 .area GSINIT (CODE)
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78 .area GSFINAL (CODE)
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79 .area GSINIT (CODE)
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80 ;--------------------------------------------------------
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81 ; Home
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82 ;--------------------------------------------------------
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83 .area HOME (CODE)
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84 .area HOME (CODE)
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85 ;--------------------------------------------------------
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86 ; code
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87 ;--------------------------------------------------------
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88 .area CSEG (CODE)
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89 ;------------------------------------------------------------
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90 ;Allocation info for local variables in function 'udelay1'
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91 ;------------------------------------------------------------
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92 ;------------------------------------------------------------
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93 ; delay.c:27: udelay1 (void) _naked
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94 ; -----------------------------------------
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95 ; function udelay1
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96 ; -----------------------------------------
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0000 97 _udelay1:
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98 ; naked function: no prologue.
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99 ; delay.c:31: _endasm;
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100 ; lcall that got us here took 4 bus cycles
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0000 22 101 ret ; 4 bus cycles
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102
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103 ; naked function: no epilogue.
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104 ;------------------------------------------------------------
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105 ;Allocation info for local variables in function 'udelay'
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106 ;------------------------------------------------------------
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107 ;usecs Allocated to registers r2
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108 ;------------------------------------------------------------
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109 ; delay.c:38: udelay (unsigned char usecs)
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110 ; -----------------------------------------
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111 ; function udelay
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112 ; -----------------------------------------
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0001 113 _udelay:
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0002 114 ar2 = 0x02
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0003 115 ar3 = 0x03
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0004 116 ar4 = 0x04
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0005 117 ar5 = 0x05
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0006 118 ar6 = 0x06
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0007 119 ar7 = 0x07
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0000 120 ar0 = 0x00
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0001 121 ar1 = 0x01
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0001 AA 82 122 mov r2,dpl
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123 ; delay.c:40: do {
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0003 124 00101$:
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125 ; delay.c:41: udelay1 ();
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0003 12s00r00 126 lcall _udelay1
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127 ; delay.c:42: } while (--usecs != 0);
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0006 DA FB 128 djnz r2,00101$
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0008 22 129 ret
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130 ;------------------------------------------------------------
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131 ;Allocation info for local variables in function 'mdelay1'
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132 ;------------------------------------------------------------
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133 ;------------------------------------------------------------
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134 ; delay.c:54: mdelay1 (void) _naked
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135 ; -----------------------------------------
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136 ; function mdelay1
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137 ; -----------------------------------------
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0009 138 _mdelay1:
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139 ; naked function: no prologue.
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140 ; delay.c:65: _endasm;
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141
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0009 90 FB 50 142 mov dptr,#(-1200 & 0xffff)
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000C 143 002$:
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000C A3 144 inc dptr ; 3 bus cycles
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000D E5 82 145 mov a, dpl ; 2 bus cycles
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000F 45 83 146 orl a, dph ; 2 bus cycles
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0011 70 F9 147 jnz 002$ ; 3 bus cycles
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148
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0013 22 149 ret
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150
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151 ; naked function: no epilogue.
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152 ;------------------------------------------------------------
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153 ;Allocation info for local variables in function 'mdelay'
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154 ;------------------------------------------------------------
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155 ;msecs Allocated to registers r2 r3
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156 ;------------------------------------------------------------
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157 ; delay.c:69: mdelay (unsigned int msecs)
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158 ; -----------------------------------------
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159 ; function mdelay
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160 ; -----------------------------------------
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0014 161 _mdelay:
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0014 AA 82 162 mov r2,dpl
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0016 AB 83 163 mov r3,dph
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164 ; delay.c:71: do {
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0018 165 00101$:
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166 ; delay.c:72: mdelay1 ();
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0018 12s00r09 167 lcall _mdelay1
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168 ; delay.c:73: } while (--msecs != 0);
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001B 1A 169 dec r2
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001C BA FF 01 170 cjne r2,#0xff,00108$
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001F 1B 171 dec r3
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0020 172 00108$:
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0020 EA 173 mov a,r2
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0021 4B 174 orl a,r3
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0022 70 F4 175 jnz 00101$
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0024 22 176 ret
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177 .area CSEG (CODE)
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178 .area CONST (CODE)
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179 .area CABS (ABS,CODE)
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