mirror of
https://github.com/gnss-sdr/gnss-sdr
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Added optional support for Sparkfun SiGe GN3S USB GPS RF sampler:
- Added a pre-compiled custom GN3S firmware. - Added a fully-compliant GNU Radio source block for GN3S USB dongle. It can be used also from GNU Radio companion and from Python applications. - Added a new GN3S_Signal_Source block. It is possible to disable the GN3S signal source compilation. See README. git-svn-id: https://svn.code.sf.net/p/gnss-sdr/code/trunk@217 64b25241-fba3-4117-9849-534c7e92360d
This commit is contained in:
Javier Arribas
340
firmware/GN3S_v2/COPYING_GPL.txt
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340
firmware/GN3S_v2/COPYING_GPL.txt
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@@ -0,0 +1,340 @@
|
||||
GNU GENERAL PUBLIC LICENSE
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Version 2, June 1991
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Copyright (C) 1989, 1991 Free Software Foundation, Inc.
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59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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Everyone is permitted to copy and distribute verbatim copies
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Preamble
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The licenses for most software are designed to take away your
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21
firmware/GN3S_v2/README
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firmware/GN3S_v2/README
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|
||||
GN3S v2 CUSTOM FIRMWARE FOR GNSS-SDR
|
||||
------------------------------------
|
||||
Source maintainer:
|
||||
Javier Arribas
|
||||
jarribas@cttc.es
|
||||
|
||||
Here can be found a modified version of the Sparkfun SiGe v2 firmware.
|
||||
|
||||
The target is the 8051 MCU used in the Cypress FX2 USB 2.0 microcontroller.
|
||||
|
||||
Basically, the main modifications are:
|
||||
- Disabled the capture filesize limit
|
||||
- USB VID and PID changed
|
||||
;; Original one
|
||||
;;VID_FREE = 0x1781 ; GN3S Project
|
||||
;;PID_USRP = 0x0B39 ; CU AAU SE4120L-EK3
|
||||
;; New one
|
||||
VID_FREE = 0x16C0 ; GN3S Modified driver Project
|
||||
PID_USRP = 0x072F ; CU AAU SE4120L-EK3
|
||||
|
||||
Basically, you should follow the original Sparkfun SiGe GN3S driver build instructions, using SDCC and make
|
||||
544
firmware/GN3S_v2/bin/gn3s_firmware.ihx
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544
firmware/GN3S_v2/bin/gn3s_firmware.ihx
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:06000000020FE002006B9C
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:03000B0002006B85
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:0300130002006B7D
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:01006B003262
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:0700B100006B0002006B0070
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:0901000002006B0002006B00021A
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:030FF800021000E4
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:070FE000E4F50AF50BE4F54E
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:040FE7000CF50D7583
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:020FEB000E00F6
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:03101300020FFBCE
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||||
:030AC2001E287576
|
||||
:060AC5001F0A75821012E9
|
||||
:040ACB000E6C751E1A
|
||||
:030ACF006D751F23
|
||||
:0C0AD2000A758214120E6C90E65C743100
|
||||
:020ADE00F02204
|
||||
:0D0AE000E582547FFA24F75004758200224D
|
||||
:070AED00BA01047582012229
|
||||
:080AF400530201E4BA00010401
|
||||
:030AFC00F582225E
|
||||
:0E0AFF00AA82BA010C90E6A1E0FB7C008B827B
|
||||
:030B0D008C8322B4
|
||||
:0E0B1000BA810C90E6A2E0FB7C008B828C8305
|
||||
:010B1E0022B4
|
||||
:0E0B1F0053027FEA700C90E6A0E0FB7C008B96
|
||||
:040B2D00828C832211
|
||||
:0E0B310090E6A3E0FB7C00EAC313FA7D00EA25
|
||||
:090B3F002BFBED3C8B82F58322B7
|
||||
:0C0B4800C20090E6B8E0FA530260BA0068
|
||||
:030B5400028028F4
|
||||
:050B5700BA2002800D30
|
||||
:050B5C00BA4002800E0A
|
||||
:050B6100BA60028003F0
|
||||
:030B6600020E017B
|
||||
:060B690012099F020E01BB
|
||||
:0A0B6F001201AFE5826003020E01DF
|
||||
:060B790012099F020E01AB
|
||||
:0D0B7F0090E6B8E0FA530280BA80028003CD
|
||||
:030B8C00020D0255
|
||||
:0B0B8F0090E6B9E0FABA0003020C8007
|
||||
:050B9A00BA06028035DF
|
||||
:050B9F00BA0802800805
|
||||
:050BA400BA0A028017EF
|
||||
:030BA900020CFC3F
|
||||
:0C0BAC0090E740E522F090E68AE4F0902B
|
||||
:080BB800E68B7401F0020E014E
|
||||
:0C0BC00090E740E523F090E68AE4F09016
|
||||
:080BCC00E68B7401F0020E013A
|
||||
:0A0BD40090E6BBE0FABA01028017B8
|
||||
:050BDE00BA020280389C
|
||||
:050BE300BA0302805975
|
||||
:050BE800BA0602801BAB
|
||||
:050BED00BA0702803C84
|
||||
:030BF200020C7A78
|
||||
:0A0BF500AA24AB2590E6B3EBF07BD9
|
||||
:090BFF000090E6B4EAF0020E01D8
|
||||
:0A0C0800AA26AB2790E6B3EBF07BC1
|
||||
:090C12000090E6B4EAF0020E01C4
|
||||
:0A0C1B00AA28AB2990E6B3EBF07BAA
|
||||
:090C25000090E6B4EAF0020E01B1
|
||||
:0A0C2E00AA2AAB2B90E6B3EBF07B93
|
||||
:090C38000090E6B4EAF0020E019E
|
||||
:0E0C410090E6BAE0FA90E07CE0FBC3EA9B404C
|
||||
:070C4F000612099F020E01CD
|
||||
:0C0C560090E6BAE075F002A4247DF5825F
|
||||
:0B0C620074E035F0F583E0FAA3E090A9
|
||||
:0D0C6D00E6B3F07B0090E6B4EAF0020E0161
|
||||
:060C7A0012099F020E01A9
|
||||
:0D0C800090E6B8E0FA53021FBA0002800AA5
|
||||
:050C8D00BA0102801C09
|
||||
:050C9200BA0264802C91
|
||||
:0E0C970090E7407401F090E741E4F090E68AA7
|
||||
:090CA500F090E68B7402F0804E21
|
||||
:0E0CAE0090E740E4F090E741F090E68AF09085
|
||||
:070CBC00E68B7402F08039A1
|
||||
:0E0CC30090E6BCE0F582120AE0E58260249023
|
||||
:0E0CD100E6BCE0F582120AFFE0FA5302019041
|
||||
:0E0CDF00E740EAF090E741E4F090E68AF090FA
|
||||
:070CED00E68B7402F08008A1
|
||||
:050CF40012099F8003BE
|
||||
:030CF90012099F3E
|
||||
:060CFC0012099F020E0127
|
||||
:0C0D020090E6B9E0FA24F45003020DFE64
|
||||
:070D0E00EA2A2A900D15737B
|
||||
:070D1500020DFE020D4B026E
|
||||
:060D1C000DC6020DA70246
|
||||
:060D22000DFE020DFE02B1
|
||||
:060D28000DFE020DFE02AB
|
||||
:060D2E000DFE020D39026A
|
||||
:050D34000DFE020D425E
|
||||
:090D390090E6BAE0F522020E0179
|
||||
:090D420090E6BAE0F523020E016F
|
||||
:0D0D4B0090E6B8E0FA53021FBA00028005DE
|
||||
:050D5800BA0247800A09
|
||||
:0A0D5D0090E6BAE012099F020E01B1
|
||||
:0D0D670090E6BAE0703090E6BCE0F5821234
|
||||
:0D0D74000AE0E582602390E6BCE0F5821203
|
||||
:0E0D81000AFFAA82AB83E0FC5304FE8A828B39
|
||||
:0E0D8F0083ECF090E6BCE0F5821209A78064C8
|
||||
:050D9D0012099F805FB8
|
||||
:050DA20012099F805AB8
|
||||
:0E0DA70090E6B8E0FA53021FBA004F90E6BA89
|
||||
:070DB500E0FABA010280051B
|
||||
:050DBC00BA02028040B4
|
||||
:050DC10012099F803BB8
|
||||
:0E0DC60090E6BAE0FA702C90E6BCE0F58212DE
|
||||
:0D0DD4000AE0E582601A90E6BCE0F58212AC
|
||||
:0E0DE1000AFFAA82AB83E0FC4304018A828BE6
|
||||
:050DEF0083ECF0800D13
|
||||
:050DF40012099F8008B8
|
||||
:050DF90012099F8003B8
|
||||
:030DFE0012099F38
|
||||
:080E010090E6A0E04480F0221D
|
||||
:050E0900AA82BA0300FB
|
||||
:070E0E004005EA249C50019D
|
||||
:010E150022BA
|
||||
:090E1600740F5AFBBB03028007B4
|
||||
:070E1F00740F5AFBBB0B45E9
|
||||
:0A0E2600A2AF9202C2AFEA2400F569
|
||||
:0C0E300082E43400F5837402F07B00744F
|
||||
:0C0E3C00012AFCE43BFDEC2400F582EDF3
|
||||
:0A0E48003400F583E51FFCF074028E
|
||||
:0C0E52002AFAE43BFBEA2400F582EB34B2
|
||||
:0A0E5E0000F583AA1E7B00EAF0A253
|
||||
:030E68000292AF44
|
||||
:010E6B002264
|
||||
:080E6C00E582FA248350012203
|
||||
:060E7400EA5403600122B4
|
||||
:0A0E7A00A2AF9203C2AFEA2400F514
|
||||
:0C0E840082E43401F5837402F07B0074FA
|
||||
:0C0E9000012AFCE43BFDEC2400F582ED9F
|
||||
:0A0E9C003401F583E51FF074022A0B
|
||||
:0B0EA600FAE43BFBEA2400F582EB3489
|
||||
:080EB10001F583AA1EEAF0A27C
|
||||
:040EB9000392AF22CF
|
||||
:050EBD00AA82BA8000CA
|
||||
:070EC2004005EA244B50013A
|
||||
:010EC9002206
|
||||
:060ECA00EA54036001225E
|
||||
:0A0ED000A2AF9204C2AFEA2480F53D
|
||||
:0C0EDA0082E43400F5837402F07B0074A5
|
||||
:0C0EE600012AFCE43BFDEC2480F582EDC9
|
||||
:0A0EF2003400F583E51FF074022AB6
|
||||
:0B0EFC00FAE43BFBEA2480F582EB34B3
|
||||
:080F070000F583AA1EEAF0A226
|
||||
:040F0F000492AF2277
|
||||
:080F1300C2E8C2EA751E007578
|
||||
:060F1B001F017582431264
|
||||
:040F21000E09751E22
|
||||
:030F250080751FB5
|
||||
:0C0F280000758253120E090090E650E4A0
|
||||
:0E0F3400F00090E652E4F00090E654E4F00085
|
||||
:0E0F420090E656E4F00090E65174FFF0009047
|
||||
:0E0F5000E65374FFF00090E65574FFF0009039
|
||||
:0E0F5E00E65774FFF00090E658E4F090E65974
|
||||
:0E0F6C0074FFF090E65AE4F090E65B74FFF03C
|
||||
:0E0F7A0090E65CE4F090E65D74FFF090E65EB9
|
||||
:0E0F8800E4F090E65F74FFF00090E660E4F0A5
|
||||
:0D0F96000090E66174FFF090E662E4F090D8
|
||||
:0E0FA300E66374FFF090E665E4F090E6687493
|
||||
:0A0FB1000BF05391AFD2E8D2EA2210
|
||||
:010FBB002213
|
||||
:020FBC00AA8207
|
||||
:060FBE00120FBBDAFB225A
|
||||
:030FC40090FB504F
|
||||
:080FC700A3E582458370F922C5
|
||||
:040FCF00AA82AB83C4
|
||||
:080FD300120FC41ABAFF011B42
|
||||
:050FDB00EA4B70F42256
|
||||
:0310000075812BCC
|
||||
:0A10030012097DE5826003020FFB75
|
||||
:00000001FF
|
||||
38
firmware/GN3S_v2/include/delay.h
Normal file
38
firmware/GN3S_v2/include/delay.h
Normal file
@@ -0,0 +1,38 @@
|
||||
/* -*- c++ -*- */
|
||||
/*
|
||||
* Copyright 2003 Free Software Foundation, Inc.
|
||||
*
|
||||
* This file is part of GNU Radio
|
||||
*
|
||||
* GNU Radio is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* GNU Radio is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with GNU Radio; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
|
||||
* Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef _DELAY_H_
|
||||
#define _DELAY_H_
|
||||
|
||||
/*
|
||||
* delay for approximately usecs microseconds
|
||||
* Note limit of 255 usecs.
|
||||
*/
|
||||
void udelay (unsigned char usecs);
|
||||
|
||||
/*
|
||||
* delay for approximately msecs milliseconds
|
||||
*/
|
||||
void mdelay (unsigned short msecs);
|
||||
|
||||
|
||||
#endif /* _DELAY_H_ */
|
||||
40
firmware/GN3S_v2/include/eeprom.h
Normal file
40
firmware/GN3S_v2/include/eeprom.h
Normal file
@@ -0,0 +1,40 @@
|
||||
#define EEPROM_ADDR 0x51
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Macros
|
||||
//-----------------------------------------------------------------------------
|
||||
// the 3684 DVK board uses port pin PA7 as an EEPROM write-protect enable/disable.
|
||||
// If your design uses a different pin, modify the following macros accordingly.
|
||||
#define EEPROM_ENABLE_WRITE_PROTECT() OEA &= ~0x80 // float PA7
|
||||
#define EEPROM_DISABLE_WRITE_PROTECT() PA7 = 0; OEA |= 0x80 // drive PA7 low
|
||||
#define MSB(word) (BYTE)(((WORD)(word) >> 8) & 0xff)
|
||||
#define LSB(word) (BYTE)((WORD)(word) & 0xff)
|
||||
|
||||
#define SWAP_ENDIAN(word) ((BYTE*)&word)[0] ^= ((BYTE*)&word)[1];\
|
||||
((BYTE*)&word)[1] ^= ((BYTE*)&word)[0];\
|
||||
((BYTE*)&word)[0] ^= ((BYTE*)&word)[1]
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Function Prototypes
|
||||
//-----------------------------------------------------------------------------
|
||||
void EEWaitForStop();
|
||||
BYTE EEWaitForAck();
|
||||
static void EEStartAndAddr();
|
||||
extern void WaitForEEPROMWrite();
|
||||
BYTE EEPROMWritePage(WORD addr, BYTE xdata * ptr, BYTE len);
|
||||
BYTE EEPROMRead(WORD addr, BYTE length, BYTE xdata *buf);
|
||||
void WaitForEEPROMWrite2();
|
||||
BYTE EEWaitForDone();
|
||||
BYTE EEPROMGetPageSize();
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Global Variables
|
||||
//-----------------------------------------------------------------------------
|
||||
extern BYTE DB_Addr; // Dual Byte Address stat
|
||||
extern BYTE I2C_Addr; // I2C address
|
||||
extern BYTE EE_Page_Size; // EEPROM page size
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Global Constants
|
||||
//-----------------------------------------------------------------------------
|
||||
#define SERIAL_ADDR 0x50
|
||||
738
firmware/GN3S_v2/include/fx2regs.h
Normal file
738
firmware/GN3S_v2/include/fx2regs.h
Normal file
@@ -0,0 +1,738 @@
|
||||
/* -*- c++ -*- */
|
||||
/*
|
||||
* Copyright 2003 Free Software Foundation, Inc.
|
||||
*
|
||||
* This file is part of GNU Radio
|
||||
*
|
||||
* GNU Radio is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* GNU Radio is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with GNU Radio; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
|
||||
* Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
/*
|
||||
//-----------------------------------------------------------------------------
|
||||
// File: FX2regs.h
|
||||
// Contents: EZ-USB FX2 register declarations and bit mask definitions.
|
||||
//
|
||||
// $Archive: /USB/Target/Inc/fx2regs.h $
|
||||
// $Date: 2003/12/08 03:26:57 $
|
||||
// $Revision: 1.4 $
|
||||
//
|
||||
//
|
||||
// Copyright (c) 2000 Cypress Semiconductor, All rights reserved
|
||||
//-----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
#ifndef FX2REGS_H /* Header Sentry */
|
||||
#define FX2REGS_H
|
||||
|
||||
#define ALLOCATE_EXTERN // required for "right thing to happen" with fx2regs.h
|
||||
|
||||
/*
|
||||
//-----------------------------------------------------------------------------
|
||||
// FX2 Related Register Assignments
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
// The Ez-USB FX2 registers are defined here. We use FX2regs.h for register
|
||||
// address allocation by using "#define ALLOCATE_EXTERN".
|
||||
// When using "#define ALLOCATE_EXTERN", you get (for instance):
|
||||
// xdata volatile BYTE OUT7BUF[64] _at_ 0x7B40;
|
||||
// Such lines are created from FX2.h by using the preprocessor.
|
||||
// Incidently, these lines will not generate any space in the resulting hex
|
||||
// file; they just bind the symbols to the addresses for compilation.
|
||||
// You just need to put "#define ALLOCATE_EXTERN" in your main program file;
|
||||
// i.e. fw.c or a stand-alone C source file.
|
||||
// Without "#define ALLOCATE_EXTERN", you just get the external reference:
|
||||
// extern xdata volatile BYTE OUT7BUF[64] ;// 0x7B40;
|
||||
// This uses the concatenation operator "##" to insert a comment "//"
|
||||
// to cut off the end of the line, "_at_ 0x7B40;", which is not wanted.
|
||||
*/
|
||||
|
||||
|
||||
#ifdef ALLOCATE_EXTERN
|
||||
#define EXTERN
|
||||
#define _AT_(a) at a
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#define _AT_ ;/ ## /
|
||||
#endif
|
||||
|
||||
typedef unsigned char BYTE;
|
||||
typedef unsigned short WORD;
|
||||
|
||||
EXTERN xdata _AT_(0xE400) volatile BYTE GPIF_WAVE_DATA[128];
|
||||
EXTERN xdata _AT_(0xE480) volatile BYTE RES_WAVEDATA_END ;
|
||||
|
||||
// General Configuration
|
||||
|
||||
EXTERN xdata _AT_(0xE600) volatile BYTE CPUCS ; // Control & Status
|
||||
EXTERN xdata _AT_(0xE601) volatile BYTE IFCONFIG ; // Interface Configuration
|
||||
EXTERN xdata _AT_(0xE602) volatile BYTE PINFLAGSAB ; // FIFO FLAGA and FLAGB Assignments
|
||||
EXTERN xdata _AT_(0xE603) volatile BYTE PINFLAGSCD ; // FIFO FLAGC and FLAGD Assignments
|
||||
EXTERN xdata _AT_(0xE604) volatile BYTE FIFORESET ; // Restore FIFOS to default state
|
||||
EXTERN xdata _AT_(0xE605) volatile BYTE BREAKPT ; // Breakpoint
|
||||
EXTERN xdata _AT_(0xE606) volatile BYTE BPADDRH ; // Breakpoint Address H
|
||||
EXTERN xdata _AT_(0xE607) volatile BYTE BPADDRL ; // Breakpoint Address L
|
||||
EXTERN xdata _AT_(0xE608) volatile BYTE UART230 ; // 230 Kbaud clock for T0,T1,T2
|
||||
EXTERN xdata _AT_(0xE609) volatile BYTE FIFOPINPOLAR ; // FIFO polarities
|
||||
EXTERN xdata _AT_(0xE60A) volatile BYTE REVID ; // Chip Revision
|
||||
EXTERN xdata _AT_(0xE60B) volatile BYTE REVCTL ; // Chip Revision Control
|
||||
|
||||
// Endpoint Configuration
|
||||
|
||||
EXTERN xdata _AT_(0xE610) volatile BYTE EP1OUTCFG ; // Endpoint 1-OUT Configuration
|
||||
EXTERN xdata _AT_(0xE611) volatile BYTE EP1INCFG ; // Endpoint 1-IN Configuration
|
||||
EXTERN xdata _AT_(0xE612) volatile BYTE EP2CFG ; // Endpoint 2 Configuration
|
||||
EXTERN xdata _AT_(0xE613) volatile BYTE EP4CFG ; // Endpoint 4 Configuration
|
||||
EXTERN xdata _AT_(0xE614) volatile BYTE EP6CFG ; // Endpoint 6 Configuration
|
||||
EXTERN xdata _AT_(0xE615) volatile BYTE EP8CFG ; // Endpoint 8 Configuration
|
||||
EXTERN xdata _AT_(0xE618) volatile BYTE EP2FIFOCFG ; // Endpoint 2 FIFO configuration
|
||||
EXTERN xdata _AT_(0xE619) volatile BYTE EP4FIFOCFG ; // Endpoint 4 FIFO configuration
|
||||
EXTERN xdata _AT_(0xE61A) volatile BYTE EP6FIFOCFG ; // Endpoint 6 FIFO configuration
|
||||
EXTERN xdata _AT_(0xE61B) volatile BYTE EP8FIFOCFG ; // Endpoint 8 FIFO configuration
|
||||
EXTERN xdata _AT_(0xE620) volatile BYTE EP2AUTOINLENH ; // Endpoint 2 Packet Length H (IN only)
|
||||
EXTERN xdata _AT_(0xE621) volatile BYTE EP2AUTOINLENL ; // Endpoint 2 Packet Length L (IN only)
|
||||
EXTERN xdata _AT_(0xE622) volatile BYTE EP4AUTOINLENH ; // Endpoint 4 Packet Length H (IN only)
|
||||
EXTERN xdata _AT_(0xE623) volatile BYTE EP4AUTOINLENL ; // Endpoint 4 Packet Length L (IN only)
|
||||
EXTERN xdata _AT_(0xE624) volatile BYTE EP6AUTOINLENH ; // Endpoint 6 Packet Length H (IN only)
|
||||
EXTERN xdata _AT_(0xE625) volatile BYTE EP6AUTOINLENL ; // Endpoint 6 Packet Length L (IN only)
|
||||
EXTERN xdata _AT_(0xE626) volatile BYTE EP8AUTOINLENH ; // Endpoint 8 Packet Length H (IN only)
|
||||
EXTERN xdata _AT_(0xE627) volatile BYTE EP8AUTOINLENL ; // Endpoint 8 Packet Length L (IN only)
|
||||
EXTERN xdata _AT_(0xE630) volatile BYTE EP2FIFOPFH ; // EP2 Programmable Flag trigger H
|
||||
EXTERN xdata _AT_(0xE631) volatile BYTE EP2FIFOPFL ; // EP2 Programmable Flag trigger L
|
||||
EXTERN xdata _AT_(0xE632) volatile BYTE EP4FIFOPFH ; // EP4 Programmable Flag trigger H
|
||||
EXTERN xdata _AT_(0xE633) volatile BYTE EP4FIFOPFL ; // EP4 Programmable Flag trigger L
|
||||
EXTERN xdata _AT_(0xE634) volatile BYTE EP6FIFOPFH ; // EP6 Programmable Flag trigger H
|
||||
EXTERN xdata _AT_(0xE635) volatile BYTE EP6FIFOPFL ; // EP6 Programmable Flag trigger L
|
||||
EXTERN xdata _AT_(0xE636) volatile BYTE EP8FIFOPFH ; // EP8 Programmable Flag trigger H
|
||||
EXTERN xdata _AT_(0xE637) volatile BYTE EP8FIFOPFL ; // EP8 Programmable Flag trigger L
|
||||
EXTERN xdata _AT_(0xE640) volatile BYTE EP2ISOINPKTS ; // EP2 (if ISO) IN Packets per frame (1-3)
|
||||
EXTERN xdata _AT_(0xE641) volatile BYTE EP4ISOINPKTS ; // EP4 (if ISO) IN Packets per frame (1-3)
|
||||
EXTERN xdata _AT_(0xE642) volatile BYTE EP6ISOINPKTS ; // EP6 (if ISO) IN Packets per frame (1-3)
|
||||
EXTERN xdata _AT_(0xE643) volatile BYTE EP8ISOINPKTS ; // EP8 (if ISO) IN Packets per frame (1-3)
|
||||
EXTERN xdata _AT_(0xE648) volatile BYTE INPKTEND ; // Force IN Packet End
|
||||
EXTERN xdata _AT_(0xE649) volatile BYTE OUTPKTEND ; // Force OUT Packet End
|
||||
|
||||
// Interrupts
|
||||
|
||||
EXTERN xdata _AT_(0xE650) volatile BYTE EP2FIFOIE ; // Endpoint 2 Flag Interrupt Enable
|
||||
EXTERN xdata _AT_(0xE651) volatile BYTE EP2FIFOIRQ ; // Endpoint 2 Flag Interrupt Request
|
||||
EXTERN xdata _AT_(0xE652) volatile BYTE EP4FIFOIE ; // Endpoint 4 Flag Interrupt Enable
|
||||
EXTERN xdata _AT_(0xE653) volatile BYTE EP4FIFOIRQ ; // Endpoint 4 Flag Interrupt Request
|
||||
EXTERN xdata _AT_(0xE654) volatile BYTE EP6FIFOIE ; // Endpoint 6 Flag Interrupt Enable
|
||||
EXTERN xdata _AT_(0xE655) volatile BYTE EP6FIFOIRQ ; // Endpoint 6 Flag Interrupt Request
|
||||
EXTERN xdata _AT_(0xE656) volatile BYTE EP8FIFOIE ; // Endpoint 8 Flag Interrupt Enable
|
||||
EXTERN xdata _AT_(0xE657) volatile BYTE EP8FIFOIRQ ; // Endpoint 8 Flag Interrupt Request
|
||||
EXTERN xdata _AT_(0xE658) volatile BYTE IBNIE ; // IN-BULK-NAK Interrupt Enable
|
||||
EXTERN xdata _AT_(0xE659) volatile BYTE IBNIRQ ; // IN-BULK-NAK interrupt Request
|
||||
EXTERN xdata _AT_(0xE65A) volatile BYTE NAKIE ; // Endpoint Ping NAK interrupt Enable
|
||||
EXTERN xdata _AT_(0xE65B) volatile BYTE NAKIRQ ; // Endpoint Ping NAK interrupt Request
|
||||
EXTERN xdata _AT_(0xE65C) volatile BYTE USBIE ; // USB Int Enables
|
||||
EXTERN xdata _AT_(0xE65D) volatile BYTE USBIRQ ; // USB Interrupt Requests
|
||||
EXTERN xdata _AT_(0xE65E) volatile BYTE EPIE ; // Endpoint Interrupt Enables
|
||||
EXTERN xdata _AT_(0xE65F) volatile BYTE EPIRQ ; // Endpoint Interrupt Requests
|
||||
EXTERN xdata _AT_(0xE660) volatile BYTE GPIFIE ; // GPIF Interrupt Enable
|
||||
EXTERN xdata _AT_(0xE661) volatile BYTE GPIFIRQ ; // GPIF Interrupt Request
|
||||
EXTERN xdata _AT_(0xE662) volatile BYTE USBERRIE ; // USB Error Interrupt Enables
|
||||
EXTERN xdata _AT_(0xE663) volatile BYTE USBERRIRQ ; // USB Error Interrupt Requests
|
||||
EXTERN xdata _AT_(0xE664) volatile BYTE ERRCNTLIM ; // USB Error counter and limit
|
||||
EXTERN xdata _AT_(0xE665) volatile BYTE CLRERRCNT ; // Clear Error Counter EC[3..0]
|
||||
EXTERN xdata _AT_(0xE666) volatile BYTE INT2IVEC ; // Interupt 2 (USB) Autovector
|
||||
EXTERN xdata _AT_(0xE667) volatile BYTE INT4IVEC ; // Interupt 4 (FIFOS & GPIF) Autovector
|
||||
EXTERN xdata _AT_(0xE668) volatile BYTE INTSETUP ; // Interrupt 2&4 Setup
|
||||
|
||||
// Input/Output
|
||||
|
||||
EXTERN xdata _AT_(0xE670) volatile BYTE PORTACFG ; // I/O PORTA Alternate Configuration
|
||||
EXTERN xdata _AT_(0xE671) volatile BYTE PORTCCFG ; // I/O PORTC Alternate Configuration
|
||||
EXTERN xdata _AT_(0xE672) volatile BYTE PORTECFG ; // I/O PORTE Alternate Configuration
|
||||
EXTERN xdata _AT_(0xE678) volatile BYTE I2CS ; // Control & Status
|
||||
EXTERN xdata _AT_(0xE679) volatile BYTE I2DAT ; // Data
|
||||
EXTERN xdata _AT_(0xE67A) volatile BYTE I2CTL ; // I2C Control
|
||||
EXTERN xdata _AT_(0xE67B) volatile BYTE XAUTODAT1 ; // Autoptr1 MOVX access
|
||||
EXTERN xdata _AT_(0xE67C) volatile BYTE XAUTODAT2 ; // Autoptr2 MOVX access
|
||||
|
||||
#define EXTAUTODAT1 XAUTODAT1
|
||||
#define EXTAUTODAT2 XAUTODAT2
|
||||
|
||||
// USB Control
|
||||
|
||||
EXTERN xdata _AT_(0xE680) volatile BYTE USBCS ; // USB Control & Status
|
||||
EXTERN xdata _AT_(0xE681) volatile BYTE SUSPEND ; // Put chip into suspend
|
||||
EXTERN xdata _AT_(0xE682) volatile BYTE WAKEUPCS ; // Wakeup source and polarity
|
||||
EXTERN xdata _AT_(0xE683) volatile BYTE TOGCTL ; // Toggle Control
|
||||
EXTERN xdata _AT_(0xE684) volatile BYTE USBFRAMEH ; // USB Frame count H
|
||||
EXTERN xdata _AT_(0xE685) volatile BYTE USBFRAMEL ; // USB Frame count L
|
||||
EXTERN xdata _AT_(0xE686) volatile BYTE MICROFRAME ; // Microframe count, 0-7
|
||||
EXTERN xdata _AT_(0xE687) volatile BYTE FNADDR ; // USB Function address
|
||||
|
||||
// Endpoints
|
||||
|
||||
EXTERN xdata _AT_(0xE68A) volatile BYTE EP0BCH ; // Endpoint 0 Byte Count H
|
||||
EXTERN xdata _AT_(0xE68B) volatile BYTE EP0BCL ; // Endpoint 0 Byte Count L
|
||||
EXTERN xdata _AT_(0xE68D) volatile BYTE EP1OUTBC ; // Endpoint 1 OUT Byte Count
|
||||
EXTERN xdata _AT_(0xE68F) volatile BYTE EP1INBC ; // Endpoint 1 IN Byte Count
|
||||
EXTERN xdata _AT_(0xE690) volatile BYTE EP2BCH ; // Endpoint 2 Byte Count H
|
||||
EXTERN xdata _AT_(0xE691) volatile BYTE EP2BCL ; // Endpoint 2 Byte Count L
|
||||
EXTERN xdata _AT_(0xE694) volatile BYTE EP4BCH ; // Endpoint 4 Byte Count H
|
||||
EXTERN xdata _AT_(0xE695) volatile BYTE EP4BCL ; // Endpoint 4 Byte Count L
|
||||
EXTERN xdata _AT_(0xE698) volatile BYTE EP6BCH ; // Endpoint 6 Byte Count H
|
||||
EXTERN xdata _AT_(0xE699) volatile BYTE EP6BCL ; // Endpoint 6 Byte Count L
|
||||
EXTERN xdata _AT_(0xE69C) volatile BYTE EP8BCH ; // Endpoint 8 Byte Count H
|
||||
EXTERN xdata _AT_(0xE69D) volatile BYTE EP8BCL ; // Endpoint 8 Byte Count L
|
||||
EXTERN xdata _AT_(0xE6A0) volatile BYTE EP0CS ; // Endpoint Control and Status
|
||||
EXTERN xdata _AT_(0xE6A1) volatile BYTE EP1OUTCS ; // Endpoint 1 OUT Control and Status
|
||||
EXTERN xdata _AT_(0xE6A2) volatile BYTE EP1INCS ; // Endpoint 1 IN Control and Status
|
||||
EXTERN xdata _AT_(0xE6A3) volatile BYTE EP2CS ; // Endpoint 2 Control and Status
|
||||
EXTERN xdata _AT_(0xE6A4) volatile BYTE EP4CS ; // Endpoint 4 Control and Status
|
||||
EXTERN xdata _AT_(0xE6A5) volatile BYTE EP6CS ; // Endpoint 6 Control and Status
|
||||
EXTERN xdata _AT_(0xE6A6) volatile BYTE EP8CS ; // Endpoint 8 Control and Status
|
||||
EXTERN xdata _AT_(0xE6A7) volatile BYTE EP2FIFOFLGS ; // Endpoint 2 Flags
|
||||
EXTERN xdata _AT_(0xE6A8) volatile BYTE EP4FIFOFLGS ; // Endpoint 4 Flags
|
||||
EXTERN xdata _AT_(0xE6A9) volatile BYTE EP6FIFOFLGS ; // Endpoint 6 Flags
|
||||
EXTERN xdata _AT_(0xE6AA) volatile BYTE EP8FIFOFLGS ; // Endpoint 8 Flags
|
||||
EXTERN xdata _AT_(0xE6AB) volatile BYTE EP2FIFOBCH ; // EP2 FIFO total byte count H
|
||||
EXTERN xdata _AT_(0xE6AC) volatile BYTE EP2FIFOBCL ; // EP2 FIFO total byte count L
|
||||
EXTERN xdata _AT_(0xE6AD) volatile BYTE EP4FIFOBCH ; // EP4 FIFO total byte count H
|
||||
EXTERN xdata _AT_(0xE6AE) volatile BYTE EP4FIFOBCL ; // EP4 FIFO total byte count L
|
||||
EXTERN xdata _AT_(0xE6AF) volatile BYTE EP6FIFOBCH ; // EP6 FIFO total byte count H
|
||||
EXTERN xdata _AT_(0xE6B0) volatile BYTE EP6FIFOBCL ; // EP6 FIFO total byte count L
|
||||
EXTERN xdata _AT_(0xE6B1) volatile BYTE EP8FIFOBCH ; // EP8 FIFO total byte count H
|
||||
EXTERN xdata _AT_(0xE6B2) volatile BYTE EP8FIFOBCL ; // EP8 FIFO total byte count L
|
||||
EXTERN xdata _AT_(0xE6B3) volatile BYTE SUDPTRH ; // Setup Data Pointer high address byte
|
||||
EXTERN xdata _AT_(0xE6B4) volatile BYTE SUDPTRL ; // Setup Data Pointer low address byte
|
||||
EXTERN xdata _AT_(0xE6B5) volatile BYTE SUDPTRCTL ; // Setup Data Pointer Auto Mode
|
||||
EXTERN xdata _AT_(0xE6B8) volatile BYTE SETUPDAT[8] ; // 8 bytes of SETUP data
|
||||
|
||||
// GPIF
|
||||
|
||||
EXTERN xdata _AT_(0xE6C0) volatile BYTE GPIFWFSELECT ; // Waveform Selector
|
||||
EXTERN xdata _AT_(0xE6C1) volatile BYTE GPIFIDLECS ; // GPIF Done, GPIF IDLE drive mode
|
||||
EXTERN xdata _AT_(0xE6C2) volatile BYTE GPIFIDLECTL ; // Inactive Bus, CTL states
|
||||
EXTERN xdata _AT_(0xE6C3) volatile BYTE GPIFCTLCFG ; // CTL OUT pin drive
|
||||
EXTERN xdata _AT_(0xE6C4) volatile BYTE GPIFADRH ; // GPIF Address H
|
||||
EXTERN xdata _AT_(0xE6C5) volatile BYTE GPIFADRL ; // GPIF Address L
|
||||
|
||||
EXTERN xdata _AT_(0xE6CE) volatile BYTE GPIFTCB3 ; // GPIF Transaction Count Byte 3
|
||||
EXTERN xdata _AT_(0xE6CF) volatile BYTE GPIFTCB2 ; // GPIF Transaction Count Byte 2
|
||||
EXTERN xdata _AT_(0xE6D0) volatile BYTE GPIFTCB1 ; // GPIF Transaction Count Byte 1
|
||||
EXTERN xdata _AT_(0xE6D1) volatile BYTE GPIFTCB0 ; // GPIF Transaction Count Byte 0
|
||||
|
||||
#define EP2GPIFTCH GPIFTCB1 // these are here for backwards compatibility
|
||||
#define EP2GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
|
||||
#define EP4GPIFTCH GPIFTCB1 // these are here for backwards compatibility
|
||||
#define EP4GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
|
||||
#define EP6GPIFTCH GPIFTCB1 // these are here for backwards compatibility
|
||||
#define EP6GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
|
||||
#define EP8GPIFTCH GPIFTCB1 // these are here for backwards compatibility
|
||||
#define EP8GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
|
||||
|
||||
// EXTERN xdata volatile BYTE EP2GPIFTCH _AT_ 0xE6D0; // EP2 GPIF Transaction Count High
|
||||
// EXTERN xdata volatile BYTE EP2GPIFTCL _AT_ 0xE6D1; // EP2 GPIF Transaction Count Low
|
||||
EXTERN xdata _AT_(0xE6D2) volatile BYTE EP2GPIFFLGSEL ; // EP2 GPIF Flag select
|
||||
EXTERN xdata _AT_(0xE6D3) volatile BYTE EP2GPIFPFSTOP ; // Stop GPIF EP2 transaction on prog. flag
|
||||
EXTERN xdata _AT_(0xE6D4) volatile BYTE EP2GPIFTRIG ; // EP2 FIFO Trigger
|
||||
// EXTERN xdata volatile BYTE EP4GPIFTCH _AT_ 0xE6D8; // EP4 GPIF Transaction Count High
|
||||
// EXTERN xdata volatile BYTE EP4GPIFTCL _AT_ 0xE6D9; // EP4 GPIF Transactionr Count Low
|
||||
EXTERN xdata _AT_(0xE6DA) volatile BYTE EP4GPIFFLGSEL ; // EP4 GPIF Flag select
|
||||
EXTERN xdata _AT_(0xE6DB) volatile BYTE EP4GPIFPFSTOP ; // Stop GPIF EP4 transaction on prog. flag
|
||||
EXTERN xdata _AT_(0xE6DC) volatile BYTE EP4GPIFTRIG ; // EP4 FIFO Trigger
|
||||
// EXTERN xdata volatile BYTE EP6GPIFTCH _AT_ 0xE6E0; // EP6 GPIF Transaction Count High
|
||||
// EXTERN xdata volatile BYTE EP6GPIFTCL _AT_ 0xE6E1; // EP6 GPIF Transaction Count Low
|
||||
EXTERN xdata _AT_(0xE6E2) volatile BYTE EP6GPIFFLGSEL ; // EP6 GPIF Flag select
|
||||
EXTERN xdata _AT_(0xE6E3) volatile BYTE EP6GPIFPFSTOP ; // Stop GPIF EP6 transaction on prog. flag
|
||||
EXTERN xdata _AT_(0xE6E4) volatile BYTE EP6GPIFTRIG ; // EP6 FIFO Trigger
|
||||
// EXTERN xdata volatile BYTE EP8GPIFTCH _AT_ 0xE6E8; // EP8 GPIF Transaction Count High
|
||||
// EXTERN xdata volatile BYTE EP8GPIFTCL _AT_ 0xE6E9; // EP8GPIF Transaction Count Low
|
||||
EXTERN xdata _AT_(0xE6EA) volatile BYTE EP8GPIFFLGSEL ; // EP8 GPIF Flag select
|
||||
EXTERN xdata _AT_(0xE6EB) volatile BYTE EP8GPIFPFSTOP ; // Stop GPIF EP8 transaction on prog. flag
|
||||
EXTERN xdata _AT_(0xE6EC) volatile BYTE EP8GPIFTRIG ; // EP8 FIFO Trigger
|
||||
EXTERN xdata _AT_(0xE6F0) volatile BYTE XGPIFSGLDATH ; // GPIF Data H (16-bit mode only)
|
||||
EXTERN xdata _AT_(0xE6F1) volatile BYTE XGPIFSGLDATLX ; // Read/Write GPIF Data L & trigger transac
|
||||
EXTERN xdata _AT_(0xE6F2) volatile BYTE XGPIFSGLDATLNOX ; // Read GPIF Data L, no transac trigger
|
||||
EXTERN xdata _AT_(0xE6F3) volatile BYTE GPIFREADYCFG ; // Internal RDY,Sync/Async, RDY5CFG
|
||||
EXTERN xdata _AT_(0xE6F4) volatile BYTE GPIFREADYSTAT ; // RDY pin states
|
||||
EXTERN xdata _AT_(0xE6F5) volatile BYTE GPIFABORT ; // Abort GPIF cycles
|
||||
|
||||
// UDMA
|
||||
|
||||
EXTERN xdata _AT_(0xE6C6) volatile BYTE FLOWSTATE ; //Defines GPIF flow state
|
||||
EXTERN xdata _AT_(0xE6C7) volatile BYTE FLOWLOGIC ; //Defines flow/hold decision criteria
|
||||
EXTERN xdata _AT_(0xE6C8) volatile BYTE FLOWEQ0CTL ; //CTL states during active flow state
|
||||
EXTERN xdata _AT_(0xE6C9) volatile BYTE FLOWEQ1CTL ; //CTL states during hold flow state
|
||||
EXTERN xdata _AT_(0xE6CA) volatile BYTE FLOWHOLDOFF ;
|
||||
EXTERN xdata _AT_(0xE6CB) volatile BYTE FLOWSTB ; //CTL/RDY Signal to use as master data strobe
|
||||
EXTERN xdata _AT_(0xE6CC) volatile BYTE FLOWSTBEDGE ; //Defines active master strobe edge
|
||||
EXTERN xdata _AT_(0xE6CD) volatile BYTE FLOWSTBHPERIOD ; //Half Period of output master strobe
|
||||
EXTERN xdata _AT_(0xE60C) volatile BYTE GPIFHOLDAMOUNT ; //Data delay shift
|
||||
EXTERN xdata _AT_(0xE67D) volatile BYTE UDMACRCH ; //CRC Upper byte
|
||||
EXTERN xdata _AT_(0xE67E) volatile BYTE UDMACRCL ; //CRC Lower byte
|
||||
EXTERN xdata _AT_(0xE67F) volatile BYTE UDMACRCQUAL ; //UDMA In only, host terminated use only
|
||||
|
||||
|
||||
// Debug/Test
|
||||
|
||||
EXTERN xdata _AT_(0xE6F8) volatile BYTE DBUG ; // Debug
|
||||
EXTERN xdata _AT_(0xE6F9) volatile BYTE TESTCFG ; // Test configuration
|
||||
EXTERN xdata _AT_(0xE6FA) volatile BYTE USBTEST ; // USB Test Modes
|
||||
EXTERN xdata _AT_(0xE6FB) volatile BYTE CT1 ; // Chirp Test--Override
|
||||
EXTERN xdata _AT_(0xE6FC) volatile BYTE CT2 ; // Chirp Test--FSM
|
||||
EXTERN xdata _AT_(0xE6FD) volatile BYTE CT3 ; // Chirp Test--Control Signals
|
||||
EXTERN xdata _AT_(0xE6FE) volatile BYTE CT4 ; // Chirp Test--Inputs
|
||||
|
||||
// Endpoint Buffers
|
||||
|
||||
EXTERN xdata _AT_(0xE740) volatile BYTE EP0BUF[64] ; // EP0 IN-OUT buffer
|
||||
EXTERN xdata _AT_(0xE780) volatile BYTE EP1OUTBUF[64] ; // EP1-OUT buffer
|
||||
EXTERN xdata _AT_(0xE7C0) volatile BYTE EP1INBUF[64] ; // EP1-IN buffer
|
||||
EXTERN xdata _AT_(0xF000) volatile BYTE EP2FIFOBUF[1024] ; // 512/1024-byte EP2 buffer (IN or OUT)
|
||||
EXTERN xdata _AT_(0xF400) volatile BYTE EP4FIFOBUF[1024] ; // 512 byte EP4 buffer (IN or OUT)
|
||||
EXTERN xdata _AT_(0xF800) volatile BYTE EP6FIFOBUF[1024] ; // 512/1024-byte EP6 buffer (IN or OUT)
|
||||
EXTERN xdata _AT_(0xFC00) volatile BYTE EP8FIFOBUF[1024] ; // 512 byte EP8 buffer (IN or OUT)
|
||||
|
||||
#undef EXTERN
|
||||
#undef _AT_
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
Special Function Registers (SFRs)
|
||||
The byte registers and bits defined in the following list are based
|
||||
on the Synopsis definition of the 8051 Special Function Registers for EZ-USB.
|
||||
If you modify the register definitions below, please regenerate the file
|
||||
"ezregs.inc" which includes the same basic information for assembly inclusion.
|
||||
-----------------------------------------------------------------------------*/
|
||||
|
||||
// Port A
|
||||
sfr at 0x80 IOA;
|
||||
// Bit addressing on Port A
|
||||
sbit at 0x80+0 A0;
|
||||
sbit at 0x80+1 A1;
|
||||
sbit at 0x80+2 A2;
|
||||
sbit at 0x80+3 A3;
|
||||
sbit at 0x80+4 A4;
|
||||
sbit at 0x80+5 A5;
|
||||
sbit at 0x80+6 A6;
|
||||
sbit at 0x80+7 A7;
|
||||
|
||||
sfr at 0x81 SP;
|
||||
sfr at 0x82 DPL;
|
||||
sfr at 0x83 DPH;
|
||||
sfr at 0x84 DPL1;
|
||||
sfr at 0x85 DPH1;
|
||||
sfr at 0x86 DPS;
|
||||
/* DPS */
|
||||
sbit at 0x86+0 SEL;
|
||||
sfr at 0x87 PCON; /* PCON */
|
||||
//sbit IDLE = 0x87+0;
|
||||
//sbit STOP = 0x87+1;
|
||||
//sbit GF0 = 0x87+2;
|
||||
//sbit GF1 = 0x87+3;
|
||||
//sbit SMOD0 = 0x87+7;
|
||||
sfr at 0x88 TCON;
|
||||
/* TCON */
|
||||
sbit at 0x88+0 IT0;
|
||||
sbit at 0x88+1 IE0;
|
||||
sbit at 0x88+2 IT1;
|
||||
sbit at 0x88+3 IE1;
|
||||
sbit at 0x88+4 TR0;
|
||||
sbit at 0x88+5 TF0;
|
||||
sbit at 0x88+6 TR1;
|
||||
sbit at 0x88+7 TF1;
|
||||
sfr at 0x89 TMOD;
|
||||
/* TMOD */
|
||||
//sbit M00 = 0x89+0;
|
||||
//sbit M10 = 0x89+1;
|
||||
//sbit CT0 = 0x89+2;
|
||||
//sbit GATE0 = 0x89+3;
|
||||
//sbit M01 = 0x89+4;
|
||||
//sbit M11 = 0x89+5;
|
||||
//sbit CT1 = 0x89+6;
|
||||
//sbit GATE1 = 0x89+7;
|
||||
sfr at 0x8A TL0;
|
||||
sfr at 0x8B TL1;
|
||||
sfr at 0x8C TH0;
|
||||
sfr at 0x8D TH1;
|
||||
sfr at 0x8E CKCON;
|
||||
/* CKCON */
|
||||
//sbit MD0 = 0x89+0;
|
||||
//sbit MD1 = 0x89+1;
|
||||
//sbit MD2 = 0x89+2;
|
||||
//sbit T0M = 0x89+3;
|
||||
//sbit T1M = 0x89+4;
|
||||
//sbit T2M = 0x89+5;
|
||||
// sfr at 0x8F SPC_FNC; // Was WRS in Reg320
|
||||
/* CKCON */
|
||||
//sbit WRS = 0x8F+0;
|
||||
sfr at 0x90 IOB;
|
||||
sfr at 0x91 EXIF; // EXIF Bit Values differ from Reg320
|
||||
/* EXIF */
|
||||
//sbit USBINT = 0x91+4;
|
||||
//sbit I2CINT = 0x91+5;
|
||||
//sbit IE4 = 0x91+6;
|
||||
//sbit IE5 = 0x91+7;
|
||||
sfr at 0x92 MPAGE;
|
||||
sfr at 0x98 SCON0;
|
||||
/* SCON0 */
|
||||
sbit at 0x98+0 RI;
|
||||
sbit at 0x98+1 TI;
|
||||
sbit at 0x98+2 RB8;
|
||||
sbit at 0x98+3 TB8;
|
||||
sbit at 0x98+4 REN;
|
||||
sbit at 0x98+5 SM2;
|
||||
sbit at 0x98+6 SM1;
|
||||
sbit at 0x98+7 SM0;
|
||||
sfr at 0x99 SBUF0;
|
||||
|
||||
sfr at 0x9A APTR1H;
|
||||
sfr at 0x9B APTR1L;
|
||||
sfr at 0x9C AUTODAT1;
|
||||
sfr at 0x9D AUTOPTRH2;
|
||||
sfr at 0x9E AUTOPTRL2;
|
||||
sfr at 0x9F AUTODAT2;
|
||||
sfr at 0xA0 IOC;
|
||||
sfr at 0xA1 INT2CLR;
|
||||
sfr at 0xA2 INT4CLR;
|
||||
|
||||
#define AUTOPTRH1 APTR1H
|
||||
#define AUTOPTRL1 APTR1L
|
||||
|
||||
sfr at 0xA8 IE;
|
||||
/* IE */
|
||||
sbit at 0xA8+0 EX0;
|
||||
sbit at 0xA8+1 ET0;
|
||||
sbit at 0xA8+2 EX1;
|
||||
sbit at 0xA8+3 ET1;
|
||||
sbit at 0xA8+4 ES0;
|
||||
sbit at 0xA8+5 ET2;
|
||||
sbit at 0xA8+6 ES1;
|
||||
sbit at 0xA8+7 EA;
|
||||
|
||||
sfr at 0xAA EP2468STAT;
|
||||
/* EP2468STAT */
|
||||
//sbit EP2E = 0xAA+0;
|
||||
//sbit EP2F = 0xAA+1;
|
||||
//sbit EP4E = 0xAA+2;
|
||||
//sbit EP4F = 0xAA+3;
|
||||
//sbit EP6E = 0xAA+4;
|
||||
//sbit EP6F = 0xAA+5;
|
||||
//sbit EP8E = 0xAA+6;
|
||||
//sbit EP8F = 0xAA+7;
|
||||
|
||||
sfr at 0xAB EP24FIFOFLGS;
|
||||
sfr at 0xAC EP68FIFOFLGS;
|
||||
sfr at 0xAF AUTOPTRSETUP;
|
||||
/* AUTOPTRSETUP */
|
||||
// sbit EXTACC = 0xAF+0;
|
||||
// sbit APTR1FZ = 0xAF+1;
|
||||
// sbit APTR2FZ = 0xAF+2;
|
||||
|
||||
// Port D
|
||||
sfr at 0xB0 IOD;
|
||||
// Bit addressing on Port D
|
||||
sbit at 0xB0+0 D0;
|
||||
sbit at 0xB0+1 D1;
|
||||
sbit at 0xB0+2 D2;
|
||||
sbit at 0xB0+3 D3;
|
||||
sbit at 0xB0+4 D4;
|
||||
sbit at 0xB0+5 D5;
|
||||
sbit at 0xB0+6 D6;
|
||||
sbit at 0xB0+7 D7;
|
||||
|
||||
sfr at 0xB1 IOE;
|
||||
sfr at 0xB2 OEA;
|
||||
sfr at 0xB3 OEB;
|
||||
sfr at 0xB4 OEC;
|
||||
sfr at 0xB5 OED;
|
||||
sfr at 0xB6 OEE;
|
||||
|
||||
sfr at 0xB8 IP;
|
||||
/* IP */
|
||||
sbit at 0xB8+0 PX0;
|
||||
sbit at 0xB8+1 PT0;
|
||||
sbit at 0xB8+2 PX1;
|
||||
sbit at 0xB8+3 PT1;
|
||||
sbit at 0xB8+4 PS0;
|
||||
sbit at 0xB8+5 PT2;
|
||||
sbit at 0xB8+6 PS1;
|
||||
|
||||
sfr at 0xBA EP01STAT;
|
||||
sfr at 0xBB GPIFTRIG;
|
||||
|
||||
sfr at 0xBD GPIFSGLDATH;
|
||||
sfr at 0xBE GPIFSGLDATLX;
|
||||
sfr at 0xBF GPIFSGLDATLNOX;
|
||||
|
||||
sfr at 0xC0 SCON1;
|
||||
/* SCON1 */
|
||||
sbit at 0xC0+0 RI1;
|
||||
sbit at 0xC0+1 TI1;
|
||||
sbit at 0xC0+2 RB81;
|
||||
sbit at 0xC0+3 TB81;
|
||||
sbit at 0xC0+4 REN1;
|
||||
sbit at 0xC0+5 SM21;
|
||||
sbit at 0xC0+6 SM11;
|
||||
sbit at 0xC0+7 SM01;
|
||||
sfr at 0xC1 SBUF1;
|
||||
sfr at 0xC8 T2CON;
|
||||
/* T2CON */
|
||||
sbit at 0xC8+0 CP_RL2;
|
||||
sbit at 0xC8+1 C_T2;
|
||||
sbit at 0xC8+2 TR2;
|
||||
sbit at 0xC8+3 EXEN2;
|
||||
sbit at 0xC8+4 TCLK;
|
||||
sbit at 0xC8+5 RCLK;
|
||||
sbit at 0xC8+6 EXF2;
|
||||
sbit at 0xC8+7 TF2;
|
||||
sfr at 0xCA RCAP2L;
|
||||
sfr at 0xCB RCAP2H;
|
||||
sfr at 0xCC TL2;
|
||||
sfr at 0xCD TH2;
|
||||
sfr at 0xD0 PSW;
|
||||
/* PSW */
|
||||
sbit at 0xD0+0 P;
|
||||
sbit at 0xD0+1 FL;
|
||||
sbit at 0xD0+2 OV;
|
||||
sbit at 0xD0+3 RS0;
|
||||
sbit at 0xD0+4 RS1;
|
||||
sbit at 0xD0+5 F0;
|
||||
sbit at 0xD0+6 AC;
|
||||
sbit at 0xD0+7 CY;
|
||||
sfr at 0xD8 EICON; // Was WDCON in DS80C320 EICON; Bit Values differ from Reg320
|
||||
/* EICON */
|
||||
sbit at 0xD8+3 INT6;
|
||||
sbit at 0xD8+4 RESI;
|
||||
sbit at 0xD8+5 ERESI;
|
||||
sbit at 0xD8+7 SMOD1;
|
||||
sfr at 0xE0 ACC;
|
||||
sfr at 0xE8 EIE; // EIE Bit Values differ from Reg320
|
||||
/* EIE */
|
||||
sbit at 0xE8+0 EIUSB;
|
||||
sbit at 0xE8+1 EI2C;
|
||||
sbit at 0xE8+2 EIEX4;
|
||||
sbit at 0xE8+3 EIEX5;
|
||||
sbit at 0xE8+4 EIEX6;
|
||||
sfr at 0xF0 B;
|
||||
sfr at 0xF8 EIP; // EIP Bit Values differ from Reg320
|
||||
/* EIP */
|
||||
sbit at 0xF8+0 PUSB;
|
||||
sbit at 0xF8+1 PI2C;
|
||||
sbit at 0xF8+2 EIPX4;
|
||||
sbit at 0xF8+3 EIPX5;
|
||||
sbit at 0xF8+4 EIPX6;
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
Bit Masks
|
||||
-----------------------------------------------------------------------------*/
|
||||
|
||||
#define bmBIT0 1
|
||||
#define bmBIT1 2
|
||||
#define bmBIT2 4
|
||||
#define bmBIT3 8
|
||||
#define bmBIT4 16
|
||||
#define bmBIT5 32
|
||||
#define bmBIT6 64
|
||||
#define bmBIT7 128
|
||||
|
||||
/* CPU Control & Status Register (CPUCS) */
|
||||
#define bmPRTCSTB bmBIT5
|
||||
#define bmCLKSPD (bmBIT4 | bmBIT3)
|
||||
#define bmCLKSPD1 bmBIT4
|
||||
#define bmCLKSPD0 bmBIT3
|
||||
#define bmCLKINV bmBIT2
|
||||
#define bmCLKOE bmBIT1
|
||||
#define bm8051RES bmBIT0
|
||||
/* Port Alternate Configuration Registers */
|
||||
/* Port A (PORTACFG) */
|
||||
#define bmFLAGD bmBIT7
|
||||
#define bmINT1 bmBIT1
|
||||
#define bmINT0 bmBIT0
|
||||
/* Port C (PORTCCFG) */
|
||||
#define bmGPIFA7 bmBIT7
|
||||
#define bmGPIFA6 bmBIT6
|
||||
#define bmGPIFA5 bmBIT5
|
||||
#define bmGPIFA4 bmBIT4
|
||||
#define bmGPIFA3 bmBIT3
|
||||
#define bmGPIFA2 bmBIT2
|
||||
#define bmGPIFA1 bmBIT1
|
||||
#define bmGPIFA0 bmBIT0
|
||||
/* Port E (PORTECFG) */
|
||||
#define bmGPIFA8 bmBIT7
|
||||
#define bmT2EX bmBIT6
|
||||
#define bmINT6 bmBIT5
|
||||
#define bmRXD1OUT bmBIT4
|
||||
#define bmRXD0OUT bmBIT3
|
||||
#define bmT2OUT bmBIT2
|
||||
#define bmT1OUT bmBIT1
|
||||
#define bmT0OUT bmBIT0
|
||||
|
||||
/* I2C Control & Status Register (I2CS) */
|
||||
#define bmSTART bmBIT7
|
||||
#define bmSTOP bmBIT6
|
||||
#define bmLASTRD bmBIT5
|
||||
#define bmID (bmBIT4 | bmBIT3)
|
||||
#define bmBERR bmBIT2
|
||||
#define bmACK bmBIT1
|
||||
#define bmDONE bmBIT0
|
||||
/* I2C Control Register (I2CTL) */
|
||||
#define bmSTOPIE bmBIT1
|
||||
#define bm400KHZ bmBIT0
|
||||
/* Interrupt 2 (USB) Autovector Register (INT2IVEC) */
|
||||
#define bmIV4 bmBIT6
|
||||
#define bmIV3 bmBIT5
|
||||
#define bmIV2 bmBIT4
|
||||
#define bmIV1 bmBIT3
|
||||
#define bmIV0 bmBIT2
|
||||
/* USB Interrupt Request & Enable Registers (USBIE/USBIRQ) */
|
||||
#define bmEP0ACK bmBIT6
|
||||
#define bmHSGRANT bmBIT5
|
||||
#define bmURES bmBIT4
|
||||
#define bmSUSP bmBIT3
|
||||
#define bmSUTOK bmBIT2
|
||||
#define bmSOF bmBIT1
|
||||
#define bmSUDAV bmBIT0
|
||||
/* Breakpoint register (BREAKPT) */
|
||||
#define bmBREAK bmBIT3
|
||||
#define bmBPPULSE bmBIT2
|
||||
#define bmBPEN bmBIT1
|
||||
/* Interrupt 2 & 4 Setup (INTSETUP) */
|
||||
#define bmAV2EN bmBIT3
|
||||
#define bmINT4IN bmBIT1
|
||||
#define bmAV4EN bmBIT0
|
||||
/* USB Control & Status Register (USBCS) */
|
||||
#define bmHSM bmBIT7
|
||||
#define bmDISCON bmBIT3
|
||||
#define bmNOSYNSOF bmBIT2
|
||||
#define bmRENUM bmBIT1
|
||||
#define bmSIGRESUME bmBIT0
|
||||
/* Wakeup Control and Status Register (WAKEUPCS) */
|
||||
#define bmWU2 bmBIT7
|
||||
#define bmWU bmBIT6
|
||||
#define bmWU2POL bmBIT5
|
||||
#define bmWUPOL bmBIT4
|
||||
#define bmDPEN bmBIT2
|
||||
#define bmWU2EN bmBIT1
|
||||
#define bmWUEN bmBIT0
|
||||
/* End Point 0 Control & Status Register (EP0CS) */
|
||||
#define bmHSNAK bmBIT7
|
||||
/* End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS) */
|
||||
#define bmEPBUSY bmBIT1
|
||||
#define bmEPSTALL bmBIT0
|
||||
/* End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS) */
|
||||
#define bmNPAK (bmBIT6 | bmBIT5 | bmBIT4)
|
||||
#define bmEPFULL bmBIT3
|
||||
#define bmEPEMPTY bmBIT2
|
||||
/* Endpoint Status (EP2468STAT) SFR bits */
|
||||
#define bmEP8FULL bmBIT7
|
||||
#define bmEP8EMPTY bmBIT6
|
||||
#define bmEP6FULL bmBIT5
|
||||
#define bmEP6EMPTY bmBIT4
|
||||
#define bmEP4FULL bmBIT3
|
||||
#define bmEP4EMPTY bmBIT2
|
||||
#define bmEP2FULL bmBIT1
|
||||
#define bmEP2EMPTY bmBIT0
|
||||
/* SETUP Data Pointer Auto Mode (SUDPTRCTL) */
|
||||
#define bmSDPAUTO bmBIT0
|
||||
/* Endpoint Data Toggle Control (TOGCTL) */
|
||||
#define bmQUERYTOGGLE bmBIT7
|
||||
#define bmSETTOGGLE bmBIT6
|
||||
#define bmRESETTOGGLE bmBIT5
|
||||
#define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0
|
||||
/* IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ) */
|
||||
#define bmEP8IBN bmBIT5
|
||||
#define bmEP6IBN bmBIT4
|
||||
#define bmEP4IBN bmBIT3
|
||||
#define bmEP2IBN bmBIT2
|
||||
#define bmEP1IBN bmBIT1
|
||||
#define bmEP0IBN bmBIT0
|
||||
|
||||
/* PING-NAK enable and request bits (NAKIE/NAKIRQ) */
|
||||
#define bmEP8PING bmBIT7
|
||||
#define bmEP6PING bmBIT6
|
||||
#define bmEP4PING bmBIT5
|
||||
#define bmEP2PING bmBIT4
|
||||
#define bmEP1PING bmBIT3
|
||||
#define bmEP0PING bmBIT2
|
||||
#define bmIBN bmBIT0
|
||||
|
||||
/* Interface Configuration bits (IFCONFIG) */
|
||||
#define bmIFCLKSRC bmBIT7 // set == INTERNAL
|
||||
#define bm3048MHZ bmBIT6 // set == 48 MHz
|
||||
#define bmIFCLKOE bmBIT5
|
||||
#define bmIFCLKPOL bmBIT4
|
||||
#define bmASYNC bmBIT3
|
||||
#define bmGSTATE bmBIT2
|
||||
#define bmIFCFG1 bmBIT1
|
||||
#define bmIFCFG0 bmBIT0
|
||||
#define bmIFCFGMASK (bmIFCFG0 | bmIFCFG1)
|
||||
#define bmIFGPIF bmIFCFG1
|
||||
|
||||
/* EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG) */
|
||||
#define bmINFM bmBIT6
|
||||
#define bmOEP bmBIT5
|
||||
#define bmAUTOOUT bmBIT4
|
||||
#define bmAUTOIN bmBIT3
|
||||
#define bmZEROLENIN bmBIT2
|
||||
// must be zero bmBIT1
|
||||
#define bmWORDWIDE bmBIT0
|
||||
|
||||
/*
|
||||
* Chip Revision Control Bits (REVCTL) - used to ebable/disable revision specific features
|
||||
*/
|
||||
#define bmNOAUTOARM bmBIT1 // these don't match the docs
|
||||
#define bmSKIPCOMMIT bmBIT0 // these don't match the docs
|
||||
|
||||
#define bmDYN_OUT bmBIT1 // these do...
|
||||
#define bmENH_PKT bmBIT0
|
||||
|
||||
|
||||
/* Fifo Reset bits (FIFORESET) */
|
||||
#define bmNAKALL bmBIT7
|
||||
|
||||
/* Endpoint Configuration (EPxCFG) */
|
||||
#define bmVALID bmBIT7
|
||||
#define bmIN bmBIT6
|
||||
#define bmTYPE1 bmBIT5
|
||||
#define bmTYPE0 bmBIT4
|
||||
#define bmISOCHRONOUS bmTYPE0
|
||||
#define bmBULK bmTYPE1
|
||||
#define bmINTERRUPT (bmTYPE1 | bmTYPE0)
|
||||
#define bm1KBUF bmBIT3
|
||||
#define bmBUF1 bmBIT1
|
||||
#define bmBUF0 bmBIT0
|
||||
#define bmQUADBUF 0
|
||||
#define bmINVALIDBUF bmBUF0
|
||||
#define bmDOUBLEBUF bmBUF1
|
||||
#define bmTRIPLEBUF (bmBUF1 | bmBUF0)
|
||||
|
||||
/* OUTPKTEND */
|
||||
#define bmSKIP bmBIT7 // low 4 bits specify which end point
|
||||
|
||||
/* GPIFTRIG defs */
|
||||
#define bmGPIF_IDLE bmBIT7 // status bit
|
||||
|
||||
#define bmGPIF_EP2_START 0
|
||||
#define bmGPIF_EP4_START 1
|
||||
#define bmGPIF_EP6_START 2
|
||||
#define bmGPIF_EP8_START 3
|
||||
#define bmGPIF_READ bmBIT2
|
||||
#define bmGPIF_WRITE 0
|
||||
|
||||
/* EXIF bits */
|
||||
#define bmEXIF_USBINT bmBIT4
|
||||
#define bmEXIF_I2CINT bmBIT5
|
||||
#define bmEXIF_IE4 bmBIT6
|
||||
#define bmEXIF_IE5 bmBIT7
|
||||
|
||||
|
||||
#endif /* FX2REGS_H */
|
||||
31
firmware/GN3S_v2/include/fx2utils.h
Normal file
31
firmware/GN3S_v2/include/fx2utils.h
Normal file
@@ -0,0 +1,31 @@
|
||||
/* -*- c -*- */
|
||||
/*
|
||||
* Copyright 2003 Free Software Foundation, Inc.
|
||||
*
|
||||
* This file is part of GNU Radio
|
||||
*
|
||||
* GNU Radio is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* GNU Radio is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with GNU Radio; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
|
||||
* Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
#ifndef _FX2UTILS_H_
|
||||
#define _FX2UTILS_H_
|
||||
|
||||
void fx2_stall_ep0 (void);
|
||||
void fx2_reset_data_toggle (unsigned char ep);
|
||||
void fx2_renumerate (void);
|
||||
|
||||
|
||||
|
||||
#endif /* _FX2UTILS_H_ */
|
||||
97
firmware/GN3S_v2/include/gn3s_main.h
Normal file
97
firmware/GN3S_v2/include/gn3s_main.h
Normal file
@@ -0,0 +1,97 @@
|
||||
/*
|
||||
* Code from: USRP - Universal Software Radio Peripheral (GNU Radio)
|
||||
*
|
||||
* Initial modifications by:
|
||||
*
|
||||
* Stephan Esterhuizen, Aerospace Engineering Sciences
|
||||
* University of Colorado at Boulder
|
||||
* Boulder CO, USA
|
||||
*
|
||||
* Further modifications for use with the SiGe USB module to accompany
|
||||
* the textbook: "A Software-Defined GPS and Galileo Receiver: A
|
||||
* Single-Frequency Approach" by Kai Borre, Dennis Akos, et.al. by:
|
||||
*
|
||||
* Marcus Junered, GNSS Research Group
|
||||
* Lulea University of Technology
|
||||
* Lulea, Sweden
|
||||
*
|
||||
* http://ccar.colorado.edu/gnss
|
||||
*
|
||||
* ---------------------------------------------------------------------
|
||||
*
|
||||
* GN3S - GNSS IF Streamer for Windows
|
||||
* Copyright (C) 2006 Marcus Junered
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _GN3S_MAIN_
|
||||
#define _GN3S_MAIN_
|
||||
|
||||
#include "usrp_common.h"
|
||||
#include "fx2regs.h"
|
||||
#include "gn3s_regs.h"
|
||||
#include "gpif_inline.h"
|
||||
#include "timer.h"
|
||||
#include "isr.h"
|
||||
#include "usb_common.h"
|
||||
#include "fx2utils.h"
|
||||
#include "gn3s_se4110.h"
|
||||
#include "eeprom.h"
|
||||
#include <string.h>
|
||||
|
||||
|
||||
// ----------------------------------------------------------------
|
||||
// Vendor bmRequestType's
|
||||
// ----------------------------------------------------------------
|
||||
#define VRT_VENDOR_IN 0xC0
|
||||
#define VRT_VENDOR_OUT 0x40
|
||||
|
||||
// IN commands
|
||||
#define VRQ_GET_STATUS 0x80
|
||||
#define GS_TX_UNDERRUN 0 // wIndexL // returns 1 byte
|
||||
#define GS_RX_OVERRUN 1 // wIndexL // returns 1 byte
|
||||
|
||||
// OUT commands
|
||||
#define VRQ_XFER 0x01
|
||||
#define VRQ_XFER_TX 0x02
|
||||
|
||||
#define bRequestType SETUPDAT[0]
|
||||
#define bRequest SETUPDAT[1]
|
||||
#define wValueL SETUPDAT[2]
|
||||
#define wValueH SETUPDAT[3]
|
||||
#define wIndexL SETUPDAT[4]
|
||||
#define wIndexH SETUPDAT[5]
|
||||
#define wLengthL SETUPDAT[6]
|
||||
#define wLengthH SETUPDAT[7]
|
||||
#define GUARD 4073
|
||||
#undef wordwide
|
||||
|
||||
// A9 specific
|
||||
#define VRQ_EEPROM 0xa2 // loads (uploads) EEPROM
|
||||
#define VRQ_RAM 0xa3 // loads (uploads) external ram
|
||||
#define VRQ_DB_FX 0xa9 // Force use of double byte address EEPROM
|
||||
#define EP0BUFF_SIZE 0x40
|
||||
|
||||
|
||||
// Prototypes
|
||||
static void get_ep0_data(void);
|
||||
unsigned char app_vendor_cmd(void);
|
||||
void guardC(void) interrupt;
|
||||
static void main_loop(void);
|
||||
void TD_Init();
|
||||
|
||||
#endif
|
||||
63
firmware/GN3S_v2/include/gn3s_regs.h
Normal file
63
firmware/GN3S_v2/include/gn3s_regs.h
Normal file
@@ -0,0 +1,63 @@
|
||||
/*
|
||||
* Code from: USRP - Universal Software Radio Peripheral (GNU Radio)
|
||||
*
|
||||
* Initial modifications by:
|
||||
*
|
||||
* Stephan Esterhuizen, Aerospace Engineering Sciences
|
||||
* University of Colorado at Boulder
|
||||
* Boulder CO, USA
|
||||
*
|
||||
* Further modifications for use with the SiGe USB module to accompany
|
||||
* the textbook: "A Software-Defined GPS and Galileo Receiver: A
|
||||
* Single-Frequency Approach" by Kai Borre, Dennis Akos, et.al. by:
|
||||
*
|
||||
* Marcus Junered, GNSS Research Group
|
||||
* Lulea University of Technology
|
||||
* Lulea, Sweden
|
||||
*
|
||||
* http://ccar.colorado.edu/gnss
|
||||
*
|
||||
* ---------------------------------------------------------------------
|
||||
*
|
||||
* GN3S - GNSS IF Streamer for Windows
|
||||
* Copyright (C) 2006 Marcus Junered
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _GN3S_REGS_H_
|
||||
#define _GN3S_REGS_H_
|
||||
|
||||
/* Port A (bit addressable): */
|
||||
#define bmPORT_A_OUTPUTS 0 /* All inputs */
|
||||
#define bmPORT_A_INITIAL 0
|
||||
|
||||
/* Port B: GPIF FD[7:0] */
|
||||
// FIFO Input
|
||||
|
||||
/* Port C */
|
||||
#define bmPORT_C_OUTPUTS 0
|
||||
#define bmPORT_C_INITIAL 0
|
||||
|
||||
/* Port D: GPIF FD[15:8] */
|
||||
#define bmPORT_D_OUTPUTS 0
|
||||
#define bmPORT_D_INITIAL 0
|
||||
|
||||
/* Port E: not bit addressible */
|
||||
#define bmPORT_E_OUTPUTS 0
|
||||
#define bmPORT_E_INITIAL 0
|
||||
|
||||
#endif
|
||||
53
firmware/GN3S_v2/include/gn3s_se4110.h
Normal file
53
firmware/GN3S_v2/include/gn3s_se4110.h
Normal file
@@ -0,0 +1,53 @@
|
||||
/*
|
||||
* Code from: USRP - Universal Software Radio Peripheral (GNU Radio)
|
||||
*
|
||||
* Initial modifications by:
|
||||
*
|
||||
* Stephan Esterhuizen, Aerospace Engineering Sciences
|
||||
* University of Colorado at Boulder
|
||||
* Boulder CO, USA
|
||||
*
|
||||
* Further modifications for use with the SiGe USB module to accompany
|
||||
* the textbook: "A Software-Defined GPS and Galileo Receiver: A
|
||||
* Single-Frequency Approach" by Kai Borre, Dennis Akos, et.al. by:
|
||||
*
|
||||
* Marcus Junered, GNSS Research Group
|
||||
* Lulea University of Technology
|
||||
* Lulea, Sweden
|
||||
*
|
||||
* http://ccar.colorado.edu/gnss
|
||||
*
|
||||
* ---------------------------------------------------------------------
|
||||
*
|
||||
* GN3S - GNSS IF Streamer for Windows
|
||||
* Copyright (C) 2006 Marcus Junered
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _GN3S_SE4110_
|
||||
#define _GN3S_SE4110_
|
||||
|
||||
#include "fx2regs.h"
|
||||
#include "delay.h"
|
||||
|
||||
/* Prototypes */
|
||||
char init_se4110(void);
|
||||
char enable_se4110(void);
|
||||
char disable_se4110(void);
|
||||
char reset_se4110(void);
|
||||
char program_3w(void);
|
||||
#endif
|
||||
27
firmware/GN3S_v2/include/gpif_inline.h
Normal file
27
firmware/GN3S_v2/include/gpif_inline.h
Normal file
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Machine generated by "edit-gpif". Do not edit by hand.
|
||||
*/
|
||||
|
||||
#define setup_flowstate_common() \
|
||||
do { \
|
||||
FLOWSTATE = 0x80; \
|
||||
FLOWLOGIC = 0xed; \
|
||||
FLOWEQ0CTL = 0x00; \
|
||||
FLOWEQ1CTL = 0x00; \
|
||||
FLOWHOLDOFF = 0x00; \
|
||||
FLOWSTB = 0x00; \
|
||||
FLOWSTBEDGE = 0x03; \
|
||||
FLOWSTBHPERIOD = 0x02; \
|
||||
GPIFHOLDAMOUNT = 0x00; \
|
||||
} while (0)
|
||||
|
||||
#define setup_flowstate_read() \
|
||||
do { \
|
||||
FLOWLOGIC = 0xed; \
|
||||
} while (0)
|
||||
|
||||
#define setup_flowstate_write() \
|
||||
do { \
|
||||
FLOWLOGIC = 0xee; \
|
||||
} while (0)
|
||||
|
||||
172
firmware/GN3S_v2/include/isr.h
Normal file
172
firmware/GN3S_v2/include/isr.h
Normal file
@@ -0,0 +1,172 @@
|
||||
/* -*- c++ -*- */
|
||||
/*
|
||||
* Copyright 2003 Free Software Foundation, Inc.
|
||||
*
|
||||
* This file is part of GNU Radio
|
||||
*
|
||||
* GNU Radio is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* GNU Radio is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with GNU Radio; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
|
||||
* Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef _ISR_H_
|
||||
#define _ISR_H_
|
||||
|
||||
/*
|
||||
* ----------------------------------------------------------------
|
||||
* routines for managing interrupt services routines
|
||||
* ----------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
* The FX2 has three discrete sets of interrupt vectors.
|
||||
* The first set is the standard 8051 vector (13 8-byte entries).
|
||||
* The second set is USB interrupt autovector (32 4-byte entries).
|
||||
* The third set is the FIFO/GPIF autovector (14 4-byte entries).
|
||||
*
|
||||
* Since all the code we're running in the FX2 is ram based, we
|
||||
* forego the typical "initialize the interrupt vectors at link time"
|
||||
* strategy, in favor of calls at run time that install the correct
|
||||
* pointers to functions.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Standard Vector numbers
|
||||
*/
|
||||
|
||||
#define SV_INT_0 0x03
|
||||
#define SV_TIMER_0 0x0b
|
||||
#define SV_INT_1 0x13
|
||||
#define SV_TIMER_1 0x1b
|
||||
#define SV_SERIAL_0 0x23
|
||||
#define SV_TIMER_2 0x2b
|
||||
#define SV_RESUME 0x33
|
||||
#define SV_SERIAL_1 0x3b
|
||||
#define SV_INT_2 0x43 // (INT_2) points at USB autovector
|
||||
#define SV_I2C 0x4b
|
||||
#define SV_INT_4 0x53 // (INT_4) points at FIFO/GPIF autovector
|
||||
#define SV_INT_5 0x5b
|
||||
#define SV_INT_6 0x63
|
||||
|
||||
#define SV_MIN SV_INT_0
|
||||
#define SV_MAX SV_INT_6
|
||||
|
||||
/*
|
||||
* USB Auto Vector numbers
|
||||
*/
|
||||
|
||||
#define UV_SUDAV 0x00
|
||||
#define UV_SOF 0x04
|
||||
#define UV_SUTOK 0x08
|
||||
#define UV_SUSPEND 0x0c
|
||||
#define UV_USBRESET 0x10
|
||||
#define UV_HIGHSPEED 0x14
|
||||
#define UV_EP0ACK 0x18
|
||||
#define UV_SPARE_1C 0x1c
|
||||
#define UV_EP0IN 0x20
|
||||
#define UV_EP0OUT 0x24
|
||||
#define UV_EP1IN 0x28
|
||||
#define UV_EP1OUT 0x2c
|
||||
#define UV_EP2 0x30
|
||||
#define UV_EP4 0x34
|
||||
#define UV_EP6 0x38
|
||||
#define UV_EP8 0x3c
|
||||
#define UV_IBN 0x40
|
||||
#define UV_SPARE_44 0x44
|
||||
#define UV_EP0PINGNAK 0x48
|
||||
#define UV_EP1PINGNAK 0x4c
|
||||
#define UV_EP2PINGNAK 0x50
|
||||
#define UV_EP4PINGNAK 0x54
|
||||
#define UV_EP6PINGNAK 0x58
|
||||
#define UV_EP8PINGNAK 0x5c
|
||||
#define UV_ERRLIMIT 0x60
|
||||
#define UV_SPARE_64 0x64
|
||||
#define UV_SPARE_68 0x68
|
||||
#define UV_SPARE_6C 0x6c
|
||||
#define UV_EP2ISOERR 0x70
|
||||
#define UV_EP4ISOERR 0x74
|
||||
#define UV_EP6ISOERR 0x78
|
||||
#define UV_EP8ISOERR 0x7c
|
||||
|
||||
#define UV_MIN UV_SUDAV
|
||||
#define UV_MAX UV_EP8ISOERR
|
||||
|
||||
/*
|
||||
* FIFO/GPIF Auto Vector numbers
|
||||
*/
|
||||
|
||||
#define FGV_EP2PF 0x80
|
||||
#define FGV_EP4PF 0x84
|
||||
#define FGV_EP6PF 0x88
|
||||
#define FGV_EP8PF 0x8c
|
||||
#define FGV_EP2EF 0x90
|
||||
#define FGV_EP4EF 0x94
|
||||
#define FGV_EP6EF 0x98
|
||||
#define FGV_EP8EF 0x9c
|
||||
#define FGV_EP2FF 0xa0
|
||||
#define FGV_EP4FF 0xa4
|
||||
#define FGV_EP6FF 0xa8
|
||||
#define FGV_EP8FF 0xac
|
||||
#define FGV_GPIFDONE 0xb0
|
||||
#define FGV_GPIFWF 0xb4
|
||||
|
||||
#define FGV_MIN FGV_EP2PF
|
||||
#define FGV_MAX FGV_GPIFWF
|
||||
|
||||
|
||||
/*
|
||||
* Hook standard interrupt vector.
|
||||
*
|
||||
* vector_number is from the SV_<foo> list above.
|
||||
* addr is the address of the interrupt service routine.
|
||||
*/
|
||||
void hook_sv (unsigned char vector_number, unsigned short addr);
|
||||
|
||||
/*
|
||||
* Hook usb interrupt vector.
|
||||
*
|
||||
* vector_number is from the UV_<foo> list above.
|
||||
* addr is the address of the interrupt service routine.
|
||||
*/
|
||||
void hook_uv (unsigned char vector_number, unsigned short addr);
|
||||
|
||||
/*
|
||||
* Hook fifo/gpif interrupt vector.
|
||||
*
|
||||
* vector_number is from the FGV_<foo> list above.
|
||||
* addr is the address of the interrupt service routine.
|
||||
*/
|
||||
void hook_fgv (unsigned char vector_number, unsigned short addr);
|
||||
|
||||
/*
|
||||
* One time call to enable autovectoring for both USB and FIFO/GPIF
|
||||
*/
|
||||
void setup_autovectors (void);
|
||||
|
||||
|
||||
/*
|
||||
* Must be called in each usb interrupt handler
|
||||
*/
|
||||
#define clear_usb_irq() \
|
||||
EXIF &= ~bmEXIF_USBINT; \
|
||||
INT2CLR = 0
|
||||
|
||||
/*
|
||||
* Must be calledin each fifo/gpif interrupt handler
|
||||
*/
|
||||
#define clear_fifo_gpif_irq() \
|
||||
EXIF &= ~bmEXIF_IE4; \
|
||||
INT4CLR = 0
|
||||
|
||||
#endif /* _ISR_H_ */
|
||||
65
firmware/GN3S_v2/include/syncdelay.h
Normal file
65
firmware/GN3S_v2/include/syncdelay.h
Normal file
@@ -0,0 +1,65 @@
|
||||
/* -*- c++ -*- */
|
||||
/*
|
||||
* Copyright 2003 Free Software Foundation, Inc.
|
||||
*
|
||||
* This file is part of GNU Radio
|
||||
*
|
||||
* GNU Radio is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* GNU Radio is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with GNU Radio; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
|
||||
* Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
#ifndef _SYNCDELAY_H_
|
||||
#define _SYNCDELAY_H_
|
||||
|
||||
/*
|
||||
* Magic delay required between access to certain xdata registers (TRM page 15-106).
|
||||
* For our configuration, 48 MHz FX2 / 48 MHz IFCLK, we need three cycles. Each
|
||||
* NOP is a single cycle....
|
||||
*
|
||||
* From TRM page 15-105:
|
||||
*
|
||||
* Under certain conditions, some read and write access to the FX2 registers must
|
||||
* be separated by a "synchronization delay". The delay is necessary only under the
|
||||
* following conditions:
|
||||
*
|
||||
* - between a write to any register in the 0xE600 - 0xE6FF range and a write to one
|
||||
* of the registers listed below.
|
||||
*
|
||||
* - between a write to one of the registers listed below and a read from any register
|
||||
* in the 0xE600 - 0xE6FF range.
|
||||
*
|
||||
* Registers which require a synchronization delay:
|
||||
*
|
||||
* FIFORESET FIFOPINPOLAR
|
||||
* INPKTEND EPxBCH:L
|
||||
* EPxFIFOPFH:L EPxAUTOINLENH:L
|
||||
* EPxFIFOCFG EPxGPIFFLGSEL
|
||||
* PINFLAGSAB PINFLAGSCD
|
||||
* EPxFIFOIE EPxFIFOIRQ
|
||||
* GPIFIE GPIFIRQ
|
||||
* UDMACRCH:L GPIFADRH:L
|
||||
* GPIFTRIG EPxGPIFTRIG
|
||||
* OUTPKTEND REVCTL
|
||||
* GPIFTCB3 GPIFTCB2
|
||||
* GPIFTCB1 GPIFTCB0
|
||||
*/
|
||||
|
||||
/*
|
||||
* FIXME ensure that the peep hole optimizer isn't screwing us
|
||||
*/
|
||||
#define SYNCDELAY _asm nop; nop; nop; _endasm
|
||||
#define NOP _asm nop; _endasm
|
||||
|
||||
|
||||
#endif /* _SYNCDELAY_H_ */
|
||||
35
firmware/GN3S_v2/include/timer.h
Normal file
35
firmware/GN3S_v2/include/timer.h
Normal file
@@ -0,0 +1,35 @@
|
||||
/* -*- c++ -*- */
|
||||
/*
|
||||
* Copyright 2003 Free Software Foundation, Inc.
|
||||
*
|
||||
* This file is part of GNU Radio
|
||||
*
|
||||
* GNU Radio is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* GNU Radio is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with GNU Radio; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
|
||||
* Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef _TIMER_H_
|
||||
#define _TIMER_H_
|
||||
|
||||
/*
|
||||
* Arrange to have isr_tick_handler called at 100 Hz
|
||||
*/
|
||||
void hook_timer_tick (unsigned short isr_tick_handler);
|
||||
|
||||
#define clear_timer_irq() \
|
||||
TF2 = 0 /* clear overflow flag */
|
||||
|
||||
|
||||
#endif /* _TIMER_H_ */
|
||||
38
firmware/GN3S_v2/include/usb_common.h
Normal file
38
firmware/GN3S_v2/include/usb_common.h
Normal file
@@ -0,0 +1,38 @@
|
||||
/* -*- c -*- */
|
||||
/*
|
||||
* Copyright 2003 Free Software Foundation, Inc.
|
||||
*
|
||||
* This file is part of GNU Radio
|
||||
*
|
||||
* GNU Radio is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* GNU Radio is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with GNU Radio; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
|
||||
* Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef _USB_COMMON_H_
|
||||
#define _USB_COMMON_H_
|
||||
|
||||
extern volatile bit _usb_got_SUDAV;
|
||||
extern volatile bit _usb_rx_overrun;
|
||||
|
||||
// Provided by user application to handle VENDOR commands.
|
||||
// returns non-zero if it handled the command.
|
||||
unsigned char app_vendor_cmd (void);
|
||||
|
||||
void usb_install_handlers (void);
|
||||
void usb_handle_setup_packet (void);
|
||||
|
||||
#define usb_setup_packet_avail() _usb_got_SUDAV
|
||||
|
||||
#endif /* _USB_COMMON_H_ */
|
||||
32
firmware/GN3S_v2/include/usb_descriptors.h
Normal file
32
firmware/GN3S_v2/include/usb_descriptors.h
Normal file
@@ -0,0 +1,32 @@
|
||||
/* -*- c++ -*- */
|
||||
/*
|
||||
* Copyright 2003 Free Software Foundation, Inc.
|
||||
*
|
||||
* This file is part of GNU Radio
|
||||
*
|
||||
* GNU Radio is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* GNU Radio is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with GNU Radio; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
|
||||
* Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
extern xdata const char high_speed_device_descr[];
|
||||
extern xdata const char high_speed_devqual_descr[];
|
||||
extern xdata const char high_speed_config_descr[];
|
||||
|
||||
extern xdata const char full_speed_device_descr[];
|
||||
extern xdata const char full_speed_devqual_descr[];
|
||||
extern xdata const char full_speed_config_descr[];
|
||||
|
||||
extern xdata unsigned char nstring_descriptors;
|
||||
extern xdata char * xdata string_descriptors[];
|
||||
88
firmware/GN3S_v2/include/usb_requests.h
Normal file
88
firmware/GN3S_v2/include/usb_requests.h
Normal file
@@ -0,0 +1,88 @@
|
||||
/* -*- c++ -*- */
|
||||
/*
|
||||
* Copyright 2003 Free Software Foundation, Inc.
|
||||
*
|
||||
* This file is part of GNU Radio
|
||||
*
|
||||
* GNU Radio is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* GNU Radio is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with GNU Radio; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
|
||||
* Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
// Standard USB requests.
|
||||
// These are contained in end point 0 setup packets
|
||||
|
||||
|
||||
#ifndef _USB_REQUESTS_H_
|
||||
#define _USB_REQUESTS_H_
|
||||
|
||||
// format of bmRequestType byte
|
||||
|
||||
#define bmRT_DIR_MASK (0x1 << 7)
|
||||
#define bmRT_DIR_IN (1 << 7)
|
||||
#define bmRT_DIR_OUT (0 << 7)
|
||||
|
||||
#define bmRT_TYPE_MASK (0x3 << 5)
|
||||
#define bmRT_TYPE_STD (0 << 5)
|
||||
#define bmRT_TYPE_CLASS (1 << 5)
|
||||
#define bmRT_TYPE_VENDOR (2 << 5)
|
||||
#define bmRT_TYPE_RESERVED (3 << 5)
|
||||
|
||||
#define bmRT_RECIP_MASK (0x1f << 0)
|
||||
#define bmRT_RECIP_DEVICE (0 << 0)
|
||||
#define bmRT_RECIP_INTERFACE (1 << 0)
|
||||
#define bmRT_RECIP_ENDPOINT (2 << 0)
|
||||
#define bmRT_RECIP_OTHER (3 << 0)
|
||||
|
||||
|
||||
// standard request codes (bRequest)
|
||||
|
||||
#define RQ_GET_STATUS 0
|
||||
#define RQ_CLEAR_FEATURE 1
|
||||
#define RQ_RESERVED_2 2
|
||||
#define RQ_SET_FEATURE 3
|
||||
#define RQ_RESERVED_4 4
|
||||
#define RQ_SET_ADDRESS 5
|
||||
#define RQ_GET_DESCR 6
|
||||
#define RQ_SET_DESCR 7
|
||||
#define RQ_GET_CONFIG 8
|
||||
#define RQ_SET_CONFIG 9
|
||||
#define RQ_GET_INTERFACE 10
|
||||
#define RQ_SET_INTERFACE 11
|
||||
#define RQ_SYNCH_FRAME 12
|
||||
|
||||
// standard descriptor types
|
||||
|
||||
#define DT_DEVICE 1
|
||||
#define DT_CONFIG 2
|
||||
#define DT_STRING 3
|
||||
#define DT_INTERFACE 4
|
||||
#define DT_ENDPOINT 5
|
||||
#define DT_DEVQUAL 6
|
||||
#define DT_OTHER_SPEED 7
|
||||
#define DT_INTERFACE_POWER 8
|
||||
|
||||
// standard feature selectors
|
||||
|
||||
#define FS_ENDPOINT_HALT 0 // recip: endpoint
|
||||
#define FS_DEV_REMOTE_WAKEUP 1 // recip: device
|
||||
#define FS_TEST_MODE 2 // recip: device
|
||||
|
||||
// Get Status device attributes
|
||||
|
||||
#define bmGSDA_SELF_POWERED 0x01
|
||||
#define bmGSDA_REM_WAKEUP 0x02
|
||||
|
||||
|
||||
#endif /* _USB_REQUESTS_H_ */
|
||||
97
firmware/GN3S_v2/include/usrp_commands.h
Normal file
97
firmware/GN3S_v2/include/usrp_commands.h
Normal file
@@ -0,0 +1,97 @@
|
||||
/*
|
||||
* USRP - Universal Software Radio Peripheral
|
||||
*
|
||||
* Copyright (C) 2003,2004 Free Software Foundation, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _USRP_COMMANDS_H_
|
||||
#define _USRP_COMMANDS_H_
|
||||
|
||||
|
||||
#define MAX_EP0_PKTSIZE 64 // max size of EP0 packet on FX2
|
||||
|
||||
// ----------------------------------------------------------------
|
||||
// Vendor bmRequestType's
|
||||
// ----------------------------------------------------------------
|
||||
|
||||
#define VRT_VENDOR_IN 0xC0
|
||||
#define VRT_VENDOR_OUT 0x40
|
||||
|
||||
// ----------------------------------------------------------------
|
||||
// USRP Vendor Requests
|
||||
//
|
||||
// Note that Cypress reserves [0xA0,0xAF].
|
||||
// 0xA0 is the firmware load function.
|
||||
// ----------------------------------------------------------------
|
||||
|
||||
|
||||
// IN commands
|
||||
|
||||
#define VRQ_GET_STATUS 0x80
|
||||
#define GS_TX_UNDERRUN 0 // wIndexL // returns 1 byte
|
||||
#define GS_RX_OVERRUN 1 // wIndexL // returns 1 byte
|
||||
|
||||
#define VRQ_I2C_READ 0x81 // wValueL: i2c address; length: how much to read
|
||||
|
||||
#define VRQ_SPI_READ 0x82 // wValue: optional header bytes
|
||||
// wIndexH: enables
|
||||
// wIndexL: format
|
||||
// len: how much to read
|
||||
|
||||
// OUT commands
|
||||
|
||||
#define VRQ_SET_LED 0x01 // wValueL off/on {0,1}; wIndexL: which {0,1}
|
||||
|
||||
#define VRQ_FPGA_LOAD 0x02
|
||||
# define FL_BEGIN 0 // wIndexL: begin fpga programming cycle. stalls if trouble.
|
||||
# define FL_XFER 1 // wIndexL: xfer up to 64 bytes of data
|
||||
# define FL_END 2 // wIndexL: end programming cycle, check for success.
|
||||
// stalls endpoint if trouble.
|
||||
|
||||
#define VRQ_FPGA_WRITE_REG 0x03 // wIndexL: regno; data: 32-bit regval MSB first
|
||||
#define VRQ_FPGA_SET_RESET 0x04 // wValueL: {0,1}
|
||||
#define VRQ_FPGA_SET_TX_ENABLE 0x05 // wValueL: {0,1}
|
||||
#define VRQ_FPGA_SET_RX_ENABLE 0x06 // wValueL: {0,1}
|
||||
// see below VRQ_FPGA_SET_{TX,RX}_RESET
|
||||
|
||||
#define VRQ_SET_SLEEP_BITS 0x07 // wValueH: mask; wValueL: bits. set bits given by mask to bits
|
||||
|
||||
# define SLEEP_ADC0 0x01
|
||||
# define SLEEP_ADC1 0x02
|
||||
# define SLEEP_DAC0 0x04
|
||||
# define SLEEP_DAC1 0x08
|
||||
|
||||
#define VRQ_I2C_WRITE 0x08 // wValueL: i2c address; data: data
|
||||
|
||||
#define VRQ_SPI_WRITE 0x09 // wValue: optional header bytes
|
||||
// wIndexH: enables
|
||||
// wIndexL: format
|
||||
// len: how much to write
|
||||
|
||||
#define VRQ_FPGA_SET_TX_RESET 0x0a // wValueL: {0, 1}
|
||||
#define VRQ_FPGA_SET_RX_RESET 0x0b // wValueL: {0, 1}
|
||||
|
||||
|
||||
// -------------------------------------------------------------------
|
||||
// we store the hashes at fixed addresses in the FX2 internal memory
|
||||
|
||||
#define USRP_HASH_SLOT_0_ADDR 0xe1e0
|
||||
#define USRP_HASH_SLOT_1_ADDR 0xe1f0
|
||||
|
||||
|
||||
|
||||
#endif /* _USRP_COMMANDS_H_ */
|
||||
70
firmware/GN3S_v2/include/usrp_common.h
Normal file
70
firmware/GN3S_v2/include/usrp_common.h
Normal file
@@ -0,0 +1,70 @@
|
||||
/*
|
||||
* USRP - Universal Software Radio Peripheral
|
||||
*
|
||||
* Copyright (C) 2003 Free Software Foundation, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* common defines and prototypes for USRP
|
||||
*
|
||||
* In comments below "TRM" refers to the EZ-USB FX2 Technical Reference Manual
|
||||
*/
|
||||
|
||||
#ifndef _USRPCOMMON_H_
|
||||
#define _USRPCOMMON_H_
|
||||
|
||||
#include "gn3s_regs.h"
|
||||
#include "fx2regs.h"
|
||||
#include "syncdelay.h"
|
||||
|
||||
/*
|
||||
* From TRM page 15-105:
|
||||
*
|
||||
* Under certain conditions, some read and write access to the FX2
|
||||
* registers must be separated by a "synchronization delay". The
|
||||
* delay is necessary only under the following conditions:
|
||||
*
|
||||
* - between a write to any register in the 0xE600 - 0xE6FF range
|
||||
* and a write to one of the registers listed below.
|
||||
*
|
||||
* - between a write to one of the registers listed below and a read
|
||||
* from any register in the 0xE600 - 0xE6FF range.
|
||||
*
|
||||
* Registers which require a synchronization delay:
|
||||
*
|
||||
* FIFORESET FIFOPINPOLAR
|
||||
* INPKTEND EPxBCH:L
|
||||
* EPxFIFOPFH:L EPxAUTOINLENH:L
|
||||
* EPxFIFOCFG EPxGPIFFLGSEL
|
||||
* PINFLAGSAB PINFLAGSCD
|
||||
* EPxFIFOIE EPxFIFOIRQ
|
||||
* GPIFIE GPIFIRQ
|
||||
* UDMACRCH:L GPIFADRH:L
|
||||
* GPIFTRIG EPxGPIFTRIG
|
||||
* OUTPKTEND REVCTL
|
||||
* GPIFTCB3 GPIFTCB2
|
||||
* GPIFTCB1 GPIFTCB0
|
||||
*/
|
||||
|
||||
#define TRUE 1
|
||||
#define FALSE 0
|
||||
|
||||
|
||||
void init_usrp (void);
|
||||
void init_gpif (void);
|
||||
|
||||
#endif /* _USRPCOMMON_H_ */
|
||||
12
firmware/GN3S_v2/lib/Makefile
Normal file
12
firmware/GN3S_v2/lib/Makefile
Normal file
@@ -0,0 +1,12 @@
|
||||
INCLUDES=-I../include
|
||||
|
||||
CC=sdcc -mmcs51 --no-xinit-opt
|
||||
|
||||
all: delay.c fx2utils.c isr.c timer.c usb_common.c
|
||||
$(CC) $(INCLUDES) -c delay.c -o delay.rel
|
||||
$(CC) $(INCLUDES) -c fx2utils.c -o fx2utils.rel
|
||||
$(CC) $(INCLUDES) -c isr.c -o isr.rel
|
||||
$(CC) $(INCLUDES) -c timer.c -o timer.rel
|
||||
$(CC) $(INCLUDES) -c usb_common.c -o usb_common.rel
|
||||
clean:
|
||||
rm -f *.ihx *.rel *.rst *.lnk *.lst *.map *.asm *.sym
|
||||
179
firmware/GN3S_v2/lib/delay.asm
Normal file
179
firmware/GN3S_v2/lib/delay.asm
Normal file
@@ -0,0 +1,179 @@
|
||||
;--------------------------------------------------------
|
||||
; File Created by SDCC : free open source ANSI-C Compiler
|
||||
; Version 2.9.0 #5416 (Feb 3 2010) (UNIX)
|
||||
; This file was generated Mon Jul 30 11:40:52 2012
|
||||
;--------------------------------------------------------
|
||||
.module delay
|
||||
.optsdcc -mmcs51 --model-small
|
||||
|
||||
;--------------------------------------------------------
|
||||
; Public variables in this module
|
||||
;--------------------------------------------------------
|
||||
.globl _mdelay
|
||||
.globl _udelay
|
||||
;--------------------------------------------------------
|
||||
; special function registers
|
||||
;--------------------------------------------------------
|
||||
.area RSEG (DATA)
|
||||
;--------------------------------------------------------
|
||||
; special function bits
|
||||
;--------------------------------------------------------
|
||||
.area RSEG (DATA)
|
||||
;--------------------------------------------------------
|
||||
; overlayable register banks
|
||||
;--------------------------------------------------------
|
||||
.area REG_BANK_0 (REL,OVR,DATA)
|
||||
.ds 8
|
||||
;--------------------------------------------------------
|
||||
; internal ram data
|
||||
;--------------------------------------------------------
|
||||
.area DSEG (DATA)
|
||||
;--------------------------------------------------------
|
||||
; overlayable items in internal ram
|
||||
;--------------------------------------------------------
|
||||
.area OSEG (OVR,DATA)
|
||||
;--------------------------------------------------------
|
||||
; indirectly addressable internal ram data
|
||||
;--------------------------------------------------------
|
||||
.area ISEG (DATA)
|
||||
;--------------------------------------------------------
|
||||
; absolute internal ram data
|
||||
;--------------------------------------------------------
|
||||
.area IABS (ABS,DATA)
|
||||
.area IABS (ABS,DATA)
|
||||
;--------------------------------------------------------
|
||||
; bit data
|
||||
;--------------------------------------------------------
|
||||
.area BSEG (BIT)
|
||||
;--------------------------------------------------------
|
||||
; paged external ram data
|
||||
;--------------------------------------------------------
|
||||
.area PSEG (PAG,XDATA)
|
||||
;--------------------------------------------------------
|
||||
; external ram data
|
||||
;--------------------------------------------------------
|
||||
.area XSEG (XDATA)
|
||||
;--------------------------------------------------------
|
||||
; absolute external ram data
|
||||
;--------------------------------------------------------
|
||||
.area XABS (ABS,XDATA)
|
||||
;--------------------------------------------------------
|
||||
; external initialized ram data
|
||||
;--------------------------------------------------------
|
||||
.area HOME (CODE)
|
||||
.area GSINIT0 (CODE)
|
||||
.area GSINIT1 (CODE)
|
||||
.area GSINIT2 (CODE)
|
||||
.area GSINIT3 (CODE)
|
||||
.area GSINIT4 (CODE)
|
||||
.area GSINIT5 (CODE)
|
||||
.area GSINIT (CODE)
|
||||
.area GSFINAL (CODE)
|
||||
.area CSEG (CODE)
|
||||
;--------------------------------------------------------
|
||||
; global & static initialisations
|
||||
;--------------------------------------------------------
|
||||
.area HOME (CODE)
|
||||
.area GSINIT (CODE)
|
||||
.area GSFINAL (CODE)
|
||||
.area GSINIT (CODE)
|
||||
;--------------------------------------------------------
|
||||
; Home
|
||||
;--------------------------------------------------------
|
||||
.area HOME (CODE)
|
||||
.area HOME (CODE)
|
||||
;--------------------------------------------------------
|
||||
; code
|
||||
;--------------------------------------------------------
|
||||
.area CSEG (CODE)
|
||||
;------------------------------------------------------------
|
||||
;Allocation info for local variables in function 'udelay1'
|
||||
;------------------------------------------------------------
|
||||
;------------------------------------------------------------
|
||||
; delay.c:27: udelay1 (void) _naked
|
||||
; -----------------------------------------
|
||||
; function udelay1
|
||||
; -----------------------------------------
|
||||
_udelay1:
|
||||
; naked function: no prologue.
|
||||
; delay.c:31: _endasm;
|
||||
; lcall that got us here took 4 bus cycles
|
||||
ret ; 4 bus cycles
|
||||
|
||||
; naked function: no epilogue.
|
||||
;------------------------------------------------------------
|
||||
;Allocation info for local variables in function 'udelay'
|
||||
;------------------------------------------------------------
|
||||
;usecs Allocated to registers r2
|
||||
;------------------------------------------------------------
|
||||
; delay.c:38: udelay (unsigned char usecs)
|
||||
; -----------------------------------------
|
||||
; function udelay
|
||||
; -----------------------------------------
|
||||
_udelay:
|
||||
ar2 = 0x02
|
||||
ar3 = 0x03
|
||||
ar4 = 0x04
|
||||
ar5 = 0x05
|
||||
ar6 = 0x06
|
||||
ar7 = 0x07
|
||||
ar0 = 0x00
|
||||
ar1 = 0x01
|
||||
mov r2,dpl
|
||||
; delay.c:40: do {
|
||||
00101$:
|
||||
; delay.c:41: udelay1 ();
|
||||
lcall _udelay1
|
||||
; delay.c:42: } while (--usecs != 0);
|
||||
djnz r2,00101$
|
||||
ret
|
||||
;------------------------------------------------------------
|
||||
;Allocation info for local variables in function 'mdelay1'
|
||||
;------------------------------------------------------------
|
||||
;------------------------------------------------------------
|
||||
; delay.c:54: mdelay1 (void) _naked
|
||||
; -----------------------------------------
|
||||
; function mdelay1
|
||||
; -----------------------------------------
|
||||
_mdelay1:
|
||||
; naked function: no prologue.
|
||||
; delay.c:65: _endasm;
|
||||
|
||||
mov dptr,#(-1200 & 0xffff)
|
||||
002$:
|
||||
inc dptr ; 3 bus cycles
|
||||
mov a, dpl ; 2 bus cycles
|
||||
orl a, dph ; 2 bus cycles
|
||||
jnz 002$ ; 3 bus cycles
|
||||
|
||||
ret
|
||||
|
||||
; naked function: no epilogue.
|
||||
;------------------------------------------------------------
|
||||
;Allocation info for local variables in function 'mdelay'
|
||||
;------------------------------------------------------------
|
||||
;msecs Allocated to registers r2 r3
|
||||
;------------------------------------------------------------
|
||||
; delay.c:69: mdelay (unsigned int msecs)
|
||||
; -----------------------------------------
|
||||
; function mdelay
|
||||
; -----------------------------------------
|
||||
_mdelay:
|
||||
mov r2,dpl
|
||||
mov r3,dph
|
||||
; delay.c:71: do {
|
||||
00101$:
|
||||
; delay.c:72: mdelay1 ();
|
||||
lcall _mdelay1
|
||||
; delay.c:73: } while (--msecs != 0);
|
||||
dec r2
|
||||
cjne r2,#0xff,00108$
|
||||
dec r3
|
||||
00108$:
|
||||
mov a,r2
|
||||
orl a,r3
|
||||
jnz 00101$
|
||||
ret
|
||||
.area CSEG (CODE)
|
||||
.area CONST (CODE)
|
||||
.area CABS (ABS,CODE)
|
||||
76
firmware/GN3S_v2/lib/delay.c
Normal file
76
firmware/GN3S_v2/lib/delay.c
Normal file
@@ -0,0 +1,76 @@
|
||||
/* -*- c++ -*- */
|
||||
/*
|
||||
* Copyright 2003 Free Software Foundation, Inc.
|
||||
*
|
||||
* This file is part of GNU Radio
|
||||
*
|
||||
* GNU Radio is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* GNU Radio is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with GNU Radio; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
|
||||
* Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Delay approximately 1 microsecond (including overhead in udelay).
|
||||
*/
|
||||
static void
|
||||
udelay1 (void) _naked
|
||||
{
|
||||
_asm ; lcall that got us here took 4 bus cycles
|
||||
ret ; 4 bus cycles
|
||||
_endasm;
|
||||
}
|
||||
|
||||
/*
|
||||
* delay for approximately usecs microseconds
|
||||
*/
|
||||
void
|
||||
udelay (unsigned char usecs)
|
||||
{
|
||||
do {
|
||||
udelay1 ();
|
||||
} while (--usecs != 0);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Delay approximately 1 millisecond.
|
||||
* We're running at 48 MHz, so we need 48,000 clock cycles.
|
||||
*
|
||||
* Note however, that each bus cycle takes 4 clock cycles (not obvious,
|
||||
* but explains the factor of 4 problem below).
|
||||
*/
|
||||
static void
|
||||
mdelay1 (void) _naked
|
||||
{
|
||||
_asm
|
||||
mov dptr,#(-1200 & 0xffff)
|
||||
002$:
|
||||
inc dptr ; 3 bus cycles
|
||||
mov a, dpl ; 2 bus cycles
|
||||
orl a, dph ; 2 bus cycles
|
||||
jnz 002$ ; 3 bus cycles
|
||||
|
||||
ret
|
||||
_endasm;
|
||||
}
|
||||
|
||||
void
|
||||
mdelay (unsigned int msecs)
|
||||
{
|
||||
do {
|
||||
mdelay1 ();
|
||||
} while (--msecs != 0);
|
||||
}
|
||||
|
||||
|
||||
179
firmware/GN3S_v2/lib/delay.lst
Normal file
179
firmware/GN3S_v2/lib/delay.lst
Normal file
@@ -0,0 +1,179 @@
|
||||
1 ;--------------------------------------------------------
|
||||
2 ; File Created by SDCC : free open source ANSI-C Compiler
|
||||
3 ; Version 2.9.0 #5416 (Feb 3 2010) (UNIX)
|
||||
4 ; This file was generated Mon Jul 30 11:40:52 2012
|
||||
5 ;--------------------------------------------------------
|
||||
6 .module delay
|
||||
7 .optsdcc -mmcs51 --model-small
|
||||
8
|
||||
9 ;--------------------------------------------------------
|
||||
10 ; Public variables in this module
|
||||
11 ;--------------------------------------------------------
|
||||
12 .globl _mdelay
|
||||
13 .globl _udelay
|
||||
14 ;--------------------------------------------------------
|
||||
15 ; special function registers
|
||||
16 ;--------------------------------------------------------
|
||||
17 .area RSEG (DATA)
|
||||
18 ;--------------------------------------------------------
|
||||
19 ; special function bits
|
||||
20 ;--------------------------------------------------------
|
||||
21 .area RSEG (DATA)
|
||||
22 ;--------------------------------------------------------
|
||||
23 ; overlayable register banks
|
||||
24 ;--------------------------------------------------------
|
||||
25 .area REG_BANK_0 (REL,OVR,DATA)
|
||||
0000 26 .ds 8
|
||||
27 ;--------------------------------------------------------
|
||||
28 ; internal ram data
|
||||
29 ;--------------------------------------------------------
|
||||
30 .area DSEG (DATA)
|
||||
31 ;--------------------------------------------------------
|
||||
32 ; overlayable items in internal ram
|
||||
33 ;--------------------------------------------------------
|
||||
34 .area OSEG (OVR,DATA)
|
||||
35 ;--------------------------------------------------------
|
||||
36 ; indirectly addressable internal ram data
|
||||
37 ;--------------------------------------------------------
|
||||
38 .area ISEG (DATA)
|
||||
39 ;--------------------------------------------------------
|
||||
40 ; absolute internal ram data
|
||||
41 ;--------------------------------------------------------
|
||||
42 .area IABS (ABS,DATA)
|
||||
43 .area IABS (ABS,DATA)
|
||||
44 ;--------------------------------------------------------
|
||||
45 ; bit data
|
||||
46 ;--------------------------------------------------------
|
||||
47 .area BSEG (BIT)
|
||||
48 ;--------------------------------------------------------
|
||||
49 ; paged external ram data
|
||||
50 ;--------------------------------------------------------
|
||||
51 .area PSEG (PAG,XDATA)
|
||||
52 ;--------------------------------------------------------
|
||||
53 ; external ram data
|
||||
54 ;--------------------------------------------------------
|
||||
55 .area XSEG (XDATA)
|
||||
56 ;--------------------------------------------------------
|
||||
57 ; absolute external ram data
|
||||
58 ;--------------------------------------------------------
|
||||
59 .area XABS (ABS,XDATA)
|
||||
60 ;--------------------------------------------------------
|
||||
61 ; external initialized ram data
|
||||
62 ;--------------------------------------------------------
|
||||
63 .area HOME (CODE)
|
||||
64 .area GSINIT0 (CODE)
|
||||
65 .area GSINIT1 (CODE)
|
||||
66 .area GSINIT2 (CODE)
|
||||
67 .area GSINIT3 (CODE)
|
||||
68 .area GSINIT4 (CODE)
|
||||
69 .area GSINIT5 (CODE)
|
||||
70 .area GSINIT (CODE)
|
||||
71 .area GSFINAL (CODE)
|
||||
72 .area CSEG (CODE)
|
||||
73 ;--------------------------------------------------------
|
||||
74 ; global & static initialisations
|
||||
75 ;--------------------------------------------------------
|
||||
76 .area HOME (CODE)
|
||||
77 .area GSINIT (CODE)
|
||||
78 .area GSFINAL (CODE)
|
||||
79 .area GSINIT (CODE)
|
||||
80 ;--------------------------------------------------------
|
||||
81 ; Home
|
||||
82 ;--------------------------------------------------------
|
||||
83 .area HOME (CODE)
|
||||
84 .area HOME (CODE)
|
||||
85 ;--------------------------------------------------------
|
||||
86 ; code
|
||||
87 ;--------------------------------------------------------
|
||||
88 .area CSEG (CODE)
|
||||
89 ;------------------------------------------------------------
|
||||
90 ;Allocation info for local variables in function 'udelay1'
|
||||
91 ;------------------------------------------------------------
|
||||
92 ;------------------------------------------------------------
|
||||
93 ; delay.c:27: udelay1 (void) _naked
|
||||
94 ; -----------------------------------------
|
||||
95 ; function udelay1
|
||||
96 ; -----------------------------------------
|
||||
0000 97 _udelay1:
|
||||
98 ; naked function: no prologue.
|
||||
99 ; delay.c:31: _endasm;
|
||||
100 ; lcall that got us here took 4 bus cycles
|
||||
0000 22 101 ret ; 4 bus cycles
|
||||
102
|
||||
103 ; naked function: no epilogue.
|
||||
104 ;------------------------------------------------------------
|
||||
105 ;Allocation info for local variables in function 'udelay'
|
||||
106 ;------------------------------------------------------------
|
||||
107 ;usecs Allocated to registers r2
|
||||
108 ;------------------------------------------------------------
|
||||
109 ; delay.c:38: udelay (unsigned char usecs)
|
||||
110 ; -----------------------------------------
|
||||
111 ; function udelay
|
||||
112 ; -----------------------------------------
|
||||
0001 113 _udelay:
|
||||
0002 114 ar2 = 0x02
|
||||
0003 115 ar3 = 0x03
|
||||
0004 116 ar4 = 0x04
|
||||
0005 117 ar5 = 0x05
|
||||
0006 118 ar6 = 0x06
|
||||
0007 119 ar7 = 0x07
|
||||
0000 120 ar0 = 0x00
|
||||
0001 121 ar1 = 0x01
|
||||
0001 AA 82 122 mov r2,dpl
|
||||
123 ; delay.c:40: do {
|
||||
0003 124 00101$:
|
||||
125 ; delay.c:41: udelay1 ();
|
||||
0003 12s00r00 126 lcall _udelay1
|
||||
127 ; delay.c:42: } while (--usecs != 0);
|
||||
0006 DA FB 128 djnz r2,00101$
|
||||
0008 22 129 ret
|
||||
130 ;------------------------------------------------------------
|
||||
131 ;Allocation info for local variables in function 'mdelay1'
|
||||
132 ;------------------------------------------------------------
|
||||
133 ;------------------------------------------------------------
|
||||
134 ; delay.c:54: mdelay1 (void) _naked
|
||||
135 ; -----------------------------------------
|
||||
136 ; function mdelay1
|
||||
137 ; -----------------------------------------
|
||||
0009 138 _mdelay1:
|
||||
139 ; naked function: no prologue.
|
||||
140 ; delay.c:65: _endasm;
|
||||
141
|
||||
0009 90 FB 50 142 mov dptr,#(-1200 & 0xffff)
|
||||
000C 143 002$:
|
||||
000C A3 144 inc dptr ; 3 bus cycles
|
||||
000D E5 82 145 mov a, dpl ; 2 bus cycles
|
||||
000F 45 83 146 orl a, dph ; 2 bus cycles
|
||||
0011 70 F9 147 jnz 002$ ; 3 bus cycles
|
||||
148
|
||||
0013 22 149 ret
|
||||
150
|
||||
151 ; naked function: no epilogue.
|
||||
152 ;------------------------------------------------------------
|
||||
153 ;Allocation info for local variables in function 'mdelay'
|
||||
154 ;------------------------------------------------------------
|
||||
155 ;msecs Allocated to registers r2 r3
|
||||
156 ;------------------------------------------------------------
|
||||
157 ; delay.c:69: mdelay (unsigned int msecs)
|
||||
158 ; -----------------------------------------
|
||||
159 ; function mdelay
|
||||
160 ; -----------------------------------------
|
||||
0014 161 _mdelay:
|
||||
0014 AA 82 162 mov r2,dpl
|
||||
0016 AB 83 163 mov r3,dph
|
||||
164 ; delay.c:71: do {
|
||||
0018 165 00101$:
|
||||
166 ; delay.c:72: mdelay1 ();
|
||||
0018 12s00r09 167 lcall _mdelay1
|
||||
168 ; delay.c:73: } while (--msecs != 0);
|
||||
001B 1A 169 dec r2
|
||||
001C BA FF 01 170 cjne r2,#0xff,00108$
|
||||
001F 1B 171 dec r3
|
||||
0020 172 00108$:
|
||||
0020 EA 173 mov a,r2
|
||||
0021 4B 174 orl a,r3
|
||||
0022 70 F4 175 jnz 00101$
|
||||
0024 22 176 ret
|
||||
177 .area CSEG (CODE)
|
||||
178 .area CONST (CODE)
|
||||
179 .area CABS (ABS,CODE)
|
||||
63
firmware/GN3S_v2/lib/delay.rel
Normal file
63
firmware/GN3S_v2/lib/delay.rel
Normal file
@@ -0,0 +1,63 @@
|
||||
XH
|
||||
H 17 areas 2 global symbols
|
||||
M delay
|
||||
O -mmcs51 --model-small
|
||||
A _CODE size 0 flags 0 addr 0
|
||||
A RSEG size 0 flags 0 addr 0
|
||||
A REG_BANK_0 size 8 flags 4 addr 0
|
||||
A DSEG size 0 flags 0 addr 0
|
||||
A OSEG size 0 flags 4 addr 0
|
||||
A ISEG size 0 flags 0 addr 0
|
||||
A IABS size 0 flags 8 addr 0
|
||||
A BSEG size 0 flags 80 addr 0
|
||||
A PSEG size 0 flags 50 addr 0
|
||||
A XSEG size 0 flags 40 addr 0
|
||||
A XABS size 0 flags 48 addr 0
|
||||
A HOME size 0 flags 20 addr 0
|
||||
A GSINIT0 size 0 flags 20 addr 0
|
||||
A GSINIT1 size 0 flags 20 addr 0
|
||||
A GSINIT2 size 0 flags 20 addr 0
|
||||
A GSINIT3 size 0 flags 20 addr 0
|
||||
A GSINIT4 size 0 flags 20 addr 0
|
||||
A GSINIT5 size 0 flags 20 addr 0
|
||||
A GSINIT size 0 flags 20 addr 0
|
||||
A GSFINAL size 0 flags 20 addr 0
|
||||
A CSEG size 25 flags 20 addr 0
|
||||
S _mdelay Def0014
|
||||
S _udelay Def0001
|
||||
A CONST size 0 flags 20 addr 0
|
||||
A CABS size 0 flags 28 addr 0
|
||||
T 00 00
|
||||
R 00 00 00 02
|
||||
T 00 00
|
||||
R 00 00 00 14
|
||||
T 00 00 22
|
||||
R 00 00 00 14
|
||||
T 00 01
|
||||
R 00 00 00 14
|
||||
T 00 01 AA 82
|
||||
R 00 00 00 14
|
||||
T 00 03
|
||||
R 00 00 00 14
|
||||
T 00 03 12 00 00 DA FB 22
|
||||
R 00 00 00 14 00 03 00 14
|
||||
T 00 09
|
||||
R 00 00 00 14
|
||||
T 00 09 90 FB 50
|
||||
R 00 00 00 14
|
||||
T 00 0C
|
||||
R 00 00 00 14
|
||||
T 00 0C A3 E5 82 45 83 70 F9 22
|
||||
R 00 00 00 14
|
||||
T 00 14
|
||||
R 00 00 00 14
|
||||
T 00 14 AA 82 AB 83
|
||||
R 00 00 00 14
|
||||
T 00 18
|
||||
R 00 00 00 14
|
||||
T 00 18 12 00 09 1A BA FF 01 1B
|
||||
R 00 00 00 14 00 03 00 14
|
||||
T 00 20
|
||||
R 00 00 00 14
|
||||
T 00 20 EA 4B 70 F4 22
|
||||
R 00 00 00 14
|
||||
380
firmware/GN3S_v2/lib/delay.sym
Normal file
380
firmware/GN3S_v2/lib/delay.sym
Normal file
@@ -0,0 +1,380 @@
|
||||
ASxxxx Assembler V01.70 + NoICE + SDCC mods + Flat24 Feb-1999 (Intel 8051), page 1.
|
||||
|
||||
Symbol Table
|
||||
|
||||
A 00D6
|
||||
AC 00D6
|
||||
ACC 00E0
|
||||
ACC.0 00E0
|
||||
ACC.1 00E1
|
||||
ACC.2 00E2
|
||||
ACC.3 00E3
|
||||
ACC.4 00E4
|
||||
ACC.5 00E5
|
||||
ACC.6 00E6
|
||||
ACC.7 00E7
|
||||
B 00F0
|
||||
B.0 00F0
|
||||
B.1 00F1
|
||||
B.2 00F2
|
||||
B.3 00F3
|
||||
B.4 00F4
|
||||
B.5 00F5
|
||||
B.6 00F6
|
||||
B.7 00F7
|
||||
CPRL2 00C8
|
||||
CT2 00C9
|
||||
CY 00D7
|
||||
DPH 0083
|
||||
DPL 0082
|
||||
EA 00AF
|
||||
ES 00AC
|
||||
ET0 00A9
|
||||
ET1 00AB
|
||||
ET2 00AD
|
||||
EX0 00A8
|
||||
EX1 00AA
|
||||
EXEN2 00CB
|
||||
EXF2 00CE
|
||||
F0 00D5
|
||||
IE 00A8
|
||||
IE.0 00A8
|
||||
IE.1 00A9
|
||||
IE.2 00AA
|
||||
IE.3 00AB
|
||||
IE.4 00AC
|
||||
IE.5 00AD
|
||||
IE.7 00AF
|
||||
IE0 0089
|
||||
IE1 008B
|
||||
INT0 00B2
|
||||
INT1 00B3
|
||||
IP 00B8
|
||||
IP.0 00B8
|
||||
IP.1 00B9
|
||||
IP.2 00BA
|
||||
IP.3 00BB
|
||||
IP.4 00BC
|
||||
IP.5 00BD
|
||||
IT0 0088
|
||||
IT1 008A
|
||||
OV 00D2
|
||||
P 00D0
|
||||
P0 0080
|
||||
P0.0 0080
|
||||
P0.1 0081
|
||||
P0.2 0082
|
||||
P0.3 0083
|
||||
P0.4 0084
|
||||
P0.5 0085
|
||||
P0.6 0086
|
||||
P0.7 0087
|
||||
P1 0090
|
||||
P1.0 0090
|
||||
P1.1 0091
|
||||
P1.2 0092
|
||||
P1.3 0093
|
||||
P1.4 0094
|
||||
P1.5 0095
|
||||
P1.6 0096
|
||||
P1.7 0097
|
||||
P2 00A0
|
||||
P2.0 00A0
|
||||
P2.1 00A1
|
||||
P2.2 00A2
|
||||
P2.3 00A3
|
||||
P2.4 00A4
|
||||
P2.5 00A5
|
||||
P2.6 00A6
|
||||
P2.7 00A7
|
||||
P3 00B0
|
||||
P3.0 00B0
|
||||
P3.1 00B1
|
||||
P3.2 00B2
|
||||
P3.3 00B3
|
||||
P3.4 00B4
|
||||
P3.5 00B5
|
||||
P3.6 00B6
|
||||
P3.7 00B7
|
||||
PCON 0087
|
||||
PS 00BC
|
||||
PSW 00D0
|
||||
PSW.0 00D0
|
||||
PSW.1 00D1
|
||||
PSW.2 00D2
|
||||
PSW.3 00D3
|
||||
PSW.4 00D4
|
||||
PSW.5 00D5
|
||||
PSW.6 00D6
|
||||
PSW.7 00D7
|
||||
PT0 00B9
|
||||
PT1 00BB
|
||||
PT2 00BD
|
||||
PX0 00B8
|
||||
PX1 00BA
|
||||
RB8 009A
|
||||
RCAP2H 00CB
|
||||
RCAP2L 00CA
|
||||
RCLK 00CD
|
||||
REN 009C
|
||||
RI 0098
|
||||
RS0 00D3
|
||||
RS1 00D4
|
||||
RXD 00B0
|
||||
SBUF 0099
|
||||
SCON 0098
|
||||
SCON.0 0098
|
||||
SCON.1 0099
|
||||
SCON.2 009A
|
||||
SCON.3 009B
|
||||
SCON.4 009C
|
||||
SCON.5 009D
|
||||
SCON.6 009E
|
||||
SCON.7 009F
|
||||
SM0 009F
|
||||
SM1 009E
|
||||
SM2 009D
|
||||
SP 0081
|
||||
T2CON 00C8
|
||||
T2CON.0 00C8
|
||||
T2CON.1 00C9
|
||||
T2CON.2 00CA
|
||||
T2CON.3 00CB
|
||||
T2CON.4 00CC
|
||||
T2CON.5 00CD
|
||||
T2CON.6 00CE
|
||||
T2CON.7 00CF
|
||||
TB8 009B
|
||||
TCLK 00CC
|
||||
TCON 0088
|
||||
TCON.0 0088
|
||||
TCON.1 0089
|
||||
TCON.2 008A
|
||||
TCON.3 008B
|
||||
TCON.4 008C
|
||||
TCON.5 008D
|
||||
TCON.6 008E
|
||||
TCON.7 008F
|
||||
TF0 008D
|
||||
TF1 008F
|
||||
TF2 00CF
|
||||
TH0 008C
|
||||
TH1 008D
|
||||
TH2 00CD
|
||||
TI 0099
|
||||
TL0 008A
|
||||
TL1 008B
|
||||
TL2 00CC
|
||||
TMOD 0089
|
||||
TR0 008C
|
||||
TR1 008E
|
||||
TR2 00CA
|
||||
TXD 00B1
|
||||
14 _mdelay 0014 GR
|
||||
14 _mdelay1 0009 R
|
||||
14 _udelay 0001 GR
|
||||
14 _udelay1 0000 R
|
||||
a 00D6
|
||||
ac 00D6
|
||||
acc 00E0
|
||||
acc.0 00E0
|
||||
acc.1 00E1
|
||||
acc.2 00E2
|
||||
acc.3 00E3
|
||||
acc.4 00E4
|
||||
acc.5 00E5
|
||||
acc.6 00E6
|
||||
acc.7 00E7
|
||||
ar0 = 0000
|
||||
ar1 = 0001
|
||||
ar2 = 0002
|
||||
ar3 = 0003
|
||||
ar4 = 0004
|
||||
ar5 = 0005
|
||||
ar6 = 0006
|
||||
ar7 = 0007
|
||||
b 00F0
|
||||
b.0 00F0
|
||||
b.1 00F1
|
||||
b.2 00F2
|
||||
b.3 00F3
|
||||
b.4 00F4
|
||||
b.5 00F5
|
||||
b.6 00F6
|
||||
b.7 00F7
|
||||
cprl2 00C8
|
||||
ct2 00C9
|
||||
cy 00D7
|
||||
dph 0083
|
||||
dpl 0082
|
||||
ea 00AF
|
||||
es 00AC
|
||||
et0 00A9
|
||||
et1 00AB
|
||||
et2 00AD
|
||||
ex0 00A8
|
||||
ex1 00AA
|
||||
exen2 00CB
|
||||
exf2 00CE
|
||||
f0 00D5
|
||||
ie 00A8
|
||||
ie.0 00A8
|
||||
ie.1 00A9
|
||||
ie.2 00AA
|
||||
ie.3 00AB
|
||||
ie.4 00AC
|
||||
ie.5 00AD
|
||||
ie.7 00AF
|
||||
ie0 0089
|
||||
ie1 008B
|
||||
int0 00B2
|
||||
int1 00B3
|
||||
ip 00B8
|
||||
ip.0 00B8
|
||||
ip.1 00B9
|
||||
ip.2 00BA
|
||||
ip.3 00BB
|
||||
ip.4 00BC
|
||||
ip.5 00BD
|
||||
it0 0088
|
||||
it1 008A
|
||||
ov 00D2
|
||||
p 00D0
|
||||
p0 0080
|
||||
p0.0 0080
|
||||
p0.1 0081
|
||||
p0.2 0082
|
||||
p0.3 0083
|
||||
p0.4 0084
|
||||
p0.5 0085
|
||||
p0.6 0086
|
||||
p0.7 0087
|
||||
p1 0090
|
||||
p1.0 0090
|
||||
p1.1 0091
|
||||
p1.2 0092
|
||||
p1.3 0093
|
||||
p1.4 0094
|
||||
p1.5 0095
|
||||
p1.6 0096
|
||||
p1.7 0097
|
||||
p2 00A0
|
||||
p2.0 00A0
|
||||
p2.1 00A1
|
||||
p2.2 00A2
|
||||
p2.3 00A3
|
||||
p2.4 00A4
|
||||
p2.5 00A5
|
||||
p2.6 00A6
|
||||
p2.7 00A7
|
||||
p3 00B0
|
||||
p3.0 00B0
|
||||
p3.1 00B1
|
||||
p3.2 00B2
|
||||
p3.3 00B3
|
||||
p3.4 00B4
|
||||
p3.5 00B5
|
||||
p3.6 00B6
|
||||
p3.7 00B7
|
||||
pcon 0087
|
||||
ps 00BC
|
||||
psw 00D0
|
||||
psw.0 00D0
|
||||
psw.1 00D1
|
||||
psw.2 00D2
|
||||
psw.3 00D3
|
||||
psw.4 00D4
|
||||
psw.5 00D5
|
||||
psw.6 00D6
|
||||
psw.7 00D7
|
||||
pt0 00B9
|
||||
pt1 00BB
|
||||
pt2 00BD
|
||||
px0 00B8
|
||||
px1 00BA
|
||||
rb8 009A
|
||||
rcap2h 00CB
|
||||
rcap2l 00CA
|
||||
rclk 00CD
|
||||
ren 009C
|
||||
ri 0098
|
||||
rs0 00D3
|
||||
rs1 00D4
|
||||
rxd 00B0
|
||||
sbuf 0099
|
||||
scon 0098
|
||||
scon.0 0098
|
||||
scon.1 0099
|
||||
scon.2 009A
|
||||
scon.3 009B
|
||||
scon.4 009C
|
||||
scon.5 009D
|
||||
scon.6 009E
|
||||
scon.7 009F
|
||||
sm0 009F
|
||||
sm1 009E
|
||||
sm2 009D
|
||||
sp 0081
|
||||
t2con 00C8
|
||||
t2con.0 00C8
|
||||
t2con.1 00C9
|
||||
t2con.2 00CA
|
||||
t2con.3 00CB
|
||||
t2con.4 00CC
|
||||
t2con.5 00CD
|
||||
t2con.6 00CE
|
||||
t2con.7 00CF
|
||||
tb8 009B
|
||||
tclk 00CC
|
||||
tcon 0088
|
||||
tcon.0 0088
|
||||
tcon.1 0089
|
||||
tcon.2 008A
|
||||
tcon.3 008B
|
||||
tcon.4 008C
|
||||
tcon.5 008D
|
||||
tcon.6 008E
|
||||
tcon.7 008F
|
||||
tf0 008D
|
||||
tf1 008F
|
||||
tf2 00CF
|
||||
th0 008C
|
||||
th1 008D
|
||||
th2 00CD
|
||||
ti 0099
|
||||
tl0 008A
|
||||
tl1 008B
|
||||
tl2 00CC
|
||||
tmod 0089
|
||||
tr0 008C
|
||||
tr1 008E
|
||||
tr2 00CA
|
||||
txd 00B1
|
||||
|
||||
ASxxxx Assembler V01.70 + NoICE + SDCC mods + Flat24 Feb-1999 (Intel 8051), page 2.
|
||||
|
||||
Area Table
|
||||
|
||||
0 _CODE size 0 flags 0
|
||||
1 RSEG size 0 flags 0
|
||||
2 REG_BANK_0 size 8 flags 4
|
||||
3 DSEG size 0 flags 0
|
||||
4 OSEG size 0 flags 4
|
||||
5 ISEG size 0 flags 0
|
||||
6 IABS size 0 flags 8
|
||||
7 BSEG size 0 flags 80
|
||||
8 PSEG size 0 flags 50
|
||||
9 XSEG size 0 flags 40
|
||||
A XABS size 0 flags 48
|
||||
B HOME size 0 flags 20
|
||||
C GSINIT0 size 0 flags 20
|
||||
D GSINIT1 size 0 flags 20
|
||||
E GSINIT2 size 0 flags 20
|
||||
F GSINIT3 size 0 flags 20
|
||||
10 GSINIT4 size 0 flags 20
|
||||
11 GSINIT5 size 0 flags 20
|
||||
12 GSINIT size 0 flags 20
|
||||
13 GSFINAL size 0 flags 20
|
||||
14 CSEG size 25 flags 20
|
||||
15 CONST size 0 flags 20
|
||||
16 CABS size 0 flags 28
|
||||
821
firmware/GN3S_v2/lib/fx2utils.asm
Normal file
821
firmware/GN3S_v2/lib/fx2utils.asm
Normal file
@@ -0,0 +1,821 @@
|
||||
;--------------------------------------------------------
|
||||
; File Created by SDCC : free open source ANSI-C Compiler
|
||||
; Version 2.9.0 #5416 (Feb 3 2010) (UNIX)
|
||||
; This file was generated Mon Jul 30 11:40:52 2012
|
||||
;--------------------------------------------------------
|
||||
.module fx2utils
|
||||
.optsdcc -mmcs51 --model-small
|
||||
|
||||
;--------------------------------------------------------
|
||||
; Public variables in this module
|
||||
;--------------------------------------------------------
|
||||
.globl _EIPX6
|
||||
.globl _EIPX5
|
||||
.globl _EIPX4
|
||||
.globl _PI2C
|
||||
.globl _PUSB
|
||||
.globl _EIEX6
|
||||
.globl _EIEX5
|
||||
.globl _EIEX4
|
||||
.globl _EI2C
|
||||
.globl _EIUSB
|
||||
.globl _SMOD1
|
||||
.globl _ERESI
|
||||
.globl _RESI
|
||||
.globl _INT6
|
||||
.globl _CY
|
||||
.globl _AC
|
||||
.globl _F0
|
||||
.globl _RS1
|
||||
.globl _RS0
|
||||
.globl _OV
|
||||
.globl _FL
|
||||
.globl _P
|
||||
.globl _TF2
|
||||
.globl _EXF2
|
||||
.globl _RCLK
|
||||
.globl _TCLK
|
||||
.globl _EXEN2
|
||||
.globl _TR2
|
||||
.globl _C_T2
|
||||
.globl _CP_RL2
|
||||
.globl _SM01
|
||||
.globl _SM11
|
||||
.globl _SM21
|
||||
.globl _REN1
|
||||
.globl _TB81
|
||||
.globl _RB81
|
||||
.globl _TI1
|
||||
.globl _RI1
|
||||
.globl _PS1
|
||||
.globl _PT2
|
||||
.globl _PS0
|
||||
.globl _PT1
|
||||
.globl _PX1
|
||||
.globl _PT0
|
||||
.globl _PX0
|
||||
.globl _D7
|
||||
.globl _D6
|
||||
.globl _D5
|
||||
.globl _D4
|
||||
.globl _D3
|
||||
.globl _D2
|
||||
.globl _D1
|
||||
.globl _D0
|
||||
.globl _EA
|
||||
.globl _ES1
|
||||
.globl _ET2
|
||||
.globl _ES0
|
||||
.globl _ET1
|
||||
.globl _EX1
|
||||
.globl _ET0
|
||||
.globl _EX0
|
||||
.globl _SM0
|
||||
.globl _SM1
|
||||
.globl _SM2
|
||||
.globl _REN
|
||||
.globl _TB8
|
||||
.globl _RB8
|
||||
.globl _TI
|
||||
.globl _RI
|
||||
.globl _TF1
|
||||
.globl _TR1
|
||||
.globl _TF0
|
||||
.globl _TR0
|
||||
.globl _IE1
|
||||
.globl _IT1
|
||||
.globl _IE0
|
||||
.globl _IT0
|
||||
.globl _SEL
|
||||
.globl _A7
|
||||
.globl _A6
|
||||
.globl _A5
|
||||
.globl _A4
|
||||
.globl _A3
|
||||
.globl _A2
|
||||
.globl _A1
|
||||
.globl _A0
|
||||
.globl _EIP
|
||||
.globl _B
|
||||
.globl _EIE
|
||||
.globl _ACC
|
||||
.globl _EICON
|
||||
.globl _PSW
|
||||
.globl _TH2
|
||||
.globl _TL2
|
||||
.globl _RCAP2H
|
||||
.globl _RCAP2L
|
||||
.globl _T2CON
|
||||
.globl _SBUF1
|
||||
.globl _SCON1
|
||||
.globl _GPIFSGLDATLNOX
|
||||
.globl _GPIFSGLDATLX
|
||||
.globl _GPIFSGLDATH
|
||||
.globl _GPIFTRIG
|
||||
.globl _EP01STAT
|
||||
.globl _IP
|
||||
.globl _OEE
|
||||
.globl _OED
|
||||
.globl _OEC
|
||||
.globl _OEB
|
||||
.globl _OEA
|
||||
.globl _IOE
|
||||
.globl _IOD
|
||||
.globl _AUTOPTRSETUP
|
||||
.globl _EP68FIFOFLGS
|
||||
.globl _EP24FIFOFLGS
|
||||
.globl _EP2468STAT
|
||||
.globl _IE
|
||||
.globl _INT4CLR
|
||||
.globl _INT2CLR
|
||||
.globl _IOC
|
||||
.globl _AUTODAT2
|
||||
.globl _AUTOPTRL2
|
||||
.globl _AUTOPTRH2
|
||||
.globl _AUTODAT1
|
||||
.globl _APTR1L
|
||||
.globl _APTR1H
|
||||
.globl _SBUF0
|
||||
.globl _SCON0
|
||||
.globl _MPAGE
|
||||
.globl _EXIF
|
||||
.globl _IOB
|
||||
.globl _CKCON
|
||||
.globl _TH1
|
||||
.globl _TH0
|
||||
.globl _TL1
|
||||
.globl _TL0
|
||||
.globl _TMOD
|
||||
.globl _TCON
|
||||
.globl _PCON
|
||||
.globl _DPS
|
||||
.globl _DPH1
|
||||
.globl _DPL1
|
||||
.globl _DPH
|
||||
.globl _DPL
|
||||
.globl _SP
|
||||
.globl _IOA
|
||||
.globl _EP8FIFOBUF
|
||||
.globl _EP6FIFOBUF
|
||||
.globl _EP4FIFOBUF
|
||||
.globl _EP2FIFOBUF
|
||||
.globl _EP1INBUF
|
||||
.globl _EP1OUTBUF
|
||||
.globl _EP0BUF
|
||||
.globl _CT4
|
||||
.globl _CT3
|
||||
.globl _CT2
|
||||
.globl _CT1
|
||||
.globl _USBTEST
|
||||
.globl _TESTCFG
|
||||
.globl _DBUG
|
||||
.globl _UDMACRCQUAL
|
||||
.globl _UDMACRCL
|
||||
.globl _UDMACRCH
|
||||
.globl _GPIFHOLDAMOUNT
|
||||
.globl _FLOWSTBHPERIOD
|
||||
.globl _FLOWSTBEDGE
|
||||
.globl _FLOWSTB
|
||||
.globl _FLOWHOLDOFF
|
||||
.globl _FLOWEQ1CTL
|
||||
.globl _FLOWEQ0CTL
|
||||
.globl _FLOWLOGIC
|
||||
.globl _FLOWSTATE
|
||||
.globl _GPIFABORT
|
||||
.globl _GPIFREADYSTAT
|
||||
.globl _GPIFREADYCFG
|
||||
.globl _XGPIFSGLDATLNOX
|
||||
.globl _XGPIFSGLDATLX
|
||||
.globl _XGPIFSGLDATH
|
||||
.globl _EP8GPIFTRIG
|
||||
.globl _EP8GPIFPFSTOP
|
||||
.globl _EP8GPIFFLGSEL
|
||||
.globl _EP6GPIFTRIG
|
||||
.globl _EP6GPIFPFSTOP
|
||||
.globl _EP6GPIFFLGSEL
|
||||
.globl _EP4GPIFTRIG
|
||||
.globl _EP4GPIFPFSTOP
|
||||
.globl _EP4GPIFFLGSEL
|
||||
.globl _EP2GPIFTRIG
|
||||
.globl _EP2GPIFPFSTOP
|
||||
.globl _EP2GPIFFLGSEL
|
||||
.globl _GPIFTCB0
|
||||
.globl _GPIFTCB1
|
||||
.globl _GPIFTCB2
|
||||
.globl _GPIFTCB3
|
||||
.globl _GPIFADRL
|
||||
.globl _GPIFADRH
|
||||
.globl _GPIFCTLCFG
|
||||
.globl _GPIFIDLECTL
|
||||
.globl _GPIFIDLECS
|
||||
.globl _GPIFWFSELECT
|
||||
.globl _SETUPDAT
|
||||
.globl _SUDPTRCTL
|
||||
.globl _SUDPTRL
|
||||
.globl _SUDPTRH
|
||||
.globl _EP8FIFOBCL
|
||||
.globl _EP8FIFOBCH
|
||||
.globl _EP6FIFOBCL
|
||||
.globl _EP6FIFOBCH
|
||||
.globl _EP4FIFOBCL
|
||||
.globl _EP4FIFOBCH
|
||||
.globl _EP2FIFOBCL
|
||||
.globl _EP2FIFOBCH
|
||||
.globl _EP8FIFOFLGS
|
||||
.globl _EP6FIFOFLGS
|
||||
.globl _EP4FIFOFLGS
|
||||
.globl _EP2FIFOFLGS
|
||||
.globl _EP8CS
|
||||
.globl _EP6CS
|
||||
.globl _EP4CS
|
||||
.globl _EP2CS
|
||||
.globl _EP1INCS
|
||||
.globl _EP1OUTCS
|
||||
.globl _EP0CS
|
||||
.globl _EP8BCL
|
||||
.globl _EP8BCH
|
||||
.globl _EP6BCL
|
||||
.globl _EP6BCH
|
||||
.globl _EP4BCL
|
||||
.globl _EP4BCH
|
||||
.globl _EP2BCL
|
||||
.globl _EP2BCH
|
||||
.globl _EP1INBC
|
||||
.globl _EP1OUTBC
|
||||
.globl _EP0BCL
|
||||
.globl _EP0BCH
|
||||
.globl _FNADDR
|
||||
.globl _MICROFRAME
|
||||
.globl _USBFRAMEL
|
||||
.globl _USBFRAMEH
|
||||
.globl _TOGCTL
|
||||
.globl _WAKEUPCS
|
||||
.globl _SUSPEND
|
||||
.globl _USBCS
|
||||
.globl _XAUTODAT2
|
||||
.globl _XAUTODAT1
|
||||
.globl _I2CTL
|
||||
.globl _I2DAT
|
||||
.globl _I2CS
|
||||
.globl _PORTECFG
|
||||
.globl _PORTCCFG
|
||||
.globl _PORTACFG
|
||||
.globl _INTSETUP
|
||||
.globl _INT4IVEC
|
||||
.globl _INT2IVEC
|
||||
.globl _CLRERRCNT
|
||||
.globl _ERRCNTLIM
|
||||
.globl _USBERRIRQ
|
||||
.globl _USBERRIE
|
||||
.globl _GPIFIRQ
|
||||
.globl _GPIFIE
|
||||
.globl _EPIRQ
|
||||
.globl _EPIE
|
||||
.globl _USBIRQ
|
||||
.globl _USBIE
|
||||
.globl _NAKIRQ
|
||||
.globl _NAKIE
|
||||
.globl _IBNIRQ
|
||||
.globl _IBNIE
|
||||
.globl _EP8FIFOIRQ
|
||||
.globl _EP8FIFOIE
|
||||
.globl _EP6FIFOIRQ
|
||||
.globl _EP6FIFOIE
|
||||
.globl _EP4FIFOIRQ
|
||||
.globl _EP4FIFOIE
|
||||
.globl _EP2FIFOIRQ
|
||||
.globl _EP2FIFOIE
|
||||
.globl _OUTPKTEND
|
||||
.globl _INPKTEND
|
||||
.globl _EP8ISOINPKTS
|
||||
.globl _EP6ISOINPKTS
|
||||
.globl _EP4ISOINPKTS
|
||||
.globl _EP2ISOINPKTS
|
||||
.globl _EP8FIFOPFL
|
||||
.globl _EP8FIFOPFH
|
||||
.globl _EP6FIFOPFL
|
||||
.globl _EP6FIFOPFH
|
||||
.globl _EP4FIFOPFL
|
||||
.globl _EP4FIFOPFH
|
||||
.globl _EP2FIFOPFL
|
||||
.globl _EP2FIFOPFH
|
||||
.globl _EP8AUTOINLENL
|
||||
.globl _EP8AUTOINLENH
|
||||
.globl _EP6AUTOINLENL
|
||||
.globl _EP6AUTOINLENH
|
||||
.globl _EP4AUTOINLENL
|
||||
.globl _EP4AUTOINLENH
|
||||
.globl _EP2AUTOINLENL
|
||||
.globl _EP2AUTOINLENH
|
||||
.globl _EP8FIFOCFG
|
||||
.globl _EP6FIFOCFG
|
||||
.globl _EP4FIFOCFG
|
||||
.globl _EP2FIFOCFG
|
||||
.globl _EP8CFG
|
||||
.globl _EP6CFG
|
||||
.globl _EP4CFG
|
||||
.globl _EP2CFG
|
||||
.globl _EP1INCFG
|
||||
.globl _EP1OUTCFG
|
||||
.globl _REVCTL
|
||||
.globl _REVID
|
||||
.globl _FIFOPINPOLAR
|
||||
.globl _UART230
|
||||
.globl _BPADDRL
|
||||
.globl _BPADDRH
|
||||
.globl _BREAKPT
|
||||
.globl _FIFORESET
|
||||
.globl _PINFLAGSCD
|
||||
.globl _PINFLAGSAB
|
||||
.globl _IFCONFIG
|
||||
.globl _CPUCS
|
||||
.globl _RES_WAVEDATA_END
|
||||
.globl _GPIF_WAVE_DATA
|
||||
.globl _fx2_stall_ep0
|
||||
.globl _fx2_reset_data_toggle
|
||||
.globl _fx2_renumerate
|
||||
;--------------------------------------------------------
|
||||
; special function registers
|
||||
;--------------------------------------------------------
|
||||
.area RSEG (DATA)
|
||||
_IOA = 0x0080
|
||||
_SP = 0x0081
|
||||
_DPL = 0x0082
|
||||
_DPH = 0x0083
|
||||
_DPL1 = 0x0084
|
||||
_DPH1 = 0x0085
|
||||
_DPS = 0x0086
|
||||
_PCON = 0x0087
|
||||
_TCON = 0x0088
|
||||
_TMOD = 0x0089
|
||||
_TL0 = 0x008a
|
||||
_TL1 = 0x008b
|
||||
_TH0 = 0x008c
|
||||
_TH1 = 0x008d
|
||||
_CKCON = 0x008e
|
||||
_IOB = 0x0090
|
||||
_EXIF = 0x0091
|
||||
_MPAGE = 0x0092
|
||||
_SCON0 = 0x0098
|
||||
_SBUF0 = 0x0099
|
||||
_APTR1H = 0x009a
|
||||
_APTR1L = 0x009b
|
||||
_AUTODAT1 = 0x009c
|
||||
_AUTOPTRH2 = 0x009d
|
||||
_AUTOPTRL2 = 0x009e
|
||||
_AUTODAT2 = 0x009f
|
||||
_IOC = 0x00a0
|
||||
_INT2CLR = 0x00a1
|
||||
_INT4CLR = 0x00a2
|
||||
_IE = 0x00a8
|
||||
_EP2468STAT = 0x00aa
|
||||
_EP24FIFOFLGS = 0x00ab
|
||||
_EP68FIFOFLGS = 0x00ac
|
||||
_AUTOPTRSETUP = 0x00af
|
||||
_IOD = 0x00b0
|
||||
_IOE = 0x00b1
|
||||
_OEA = 0x00b2
|
||||
_OEB = 0x00b3
|
||||
_OEC = 0x00b4
|
||||
_OED = 0x00b5
|
||||
_OEE = 0x00b6
|
||||
_IP = 0x00b8
|
||||
_EP01STAT = 0x00ba
|
||||
_GPIFTRIG = 0x00bb
|
||||
_GPIFSGLDATH = 0x00bd
|
||||
_GPIFSGLDATLX = 0x00be
|
||||
_GPIFSGLDATLNOX = 0x00bf
|
||||
_SCON1 = 0x00c0
|
||||
_SBUF1 = 0x00c1
|
||||
_T2CON = 0x00c8
|
||||
_RCAP2L = 0x00ca
|
||||
_RCAP2H = 0x00cb
|
||||
_TL2 = 0x00cc
|
||||
_TH2 = 0x00cd
|
||||
_PSW = 0x00d0
|
||||
_EICON = 0x00d8
|
||||
_ACC = 0x00e0
|
||||
_EIE = 0x00e8
|
||||
_B = 0x00f0
|
||||
_EIP = 0x00f8
|
||||
;--------------------------------------------------------
|
||||
; special function bits
|
||||
;--------------------------------------------------------
|
||||
.area RSEG (DATA)
|
||||
_A0 = 0x0080
|
||||
_A1 = 0x0081
|
||||
_A2 = 0x0082
|
||||
_A3 = 0x0083
|
||||
_A4 = 0x0084
|
||||
_A5 = 0x0085
|
||||
_A6 = 0x0086
|
||||
_A7 = 0x0087
|
||||
_SEL = 0x0086
|
||||
_IT0 = 0x0088
|
||||
_IE0 = 0x0089
|
||||
_IT1 = 0x008a
|
||||
_IE1 = 0x008b
|
||||
_TR0 = 0x008c
|
||||
_TF0 = 0x008d
|
||||
_TR1 = 0x008e
|
||||
_TF1 = 0x008f
|
||||
_RI = 0x0098
|
||||
_TI = 0x0099
|
||||
_RB8 = 0x009a
|
||||
_TB8 = 0x009b
|
||||
_REN = 0x009c
|
||||
_SM2 = 0x009d
|
||||
_SM1 = 0x009e
|
||||
_SM0 = 0x009f
|
||||
_EX0 = 0x00a8
|
||||
_ET0 = 0x00a9
|
||||
_EX1 = 0x00aa
|
||||
_ET1 = 0x00ab
|
||||
_ES0 = 0x00ac
|
||||
_ET2 = 0x00ad
|
||||
_ES1 = 0x00ae
|
||||
_EA = 0x00af
|
||||
_D0 = 0x00b0
|
||||
_D1 = 0x00b1
|
||||
_D2 = 0x00b2
|
||||
_D3 = 0x00b3
|
||||
_D4 = 0x00b4
|
||||
_D5 = 0x00b5
|
||||
_D6 = 0x00b6
|
||||
_D7 = 0x00b7
|
||||
_PX0 = 0x00b8
|
||||
_PT0 = 0x00b9
|
||||
_PX1 = 0x00ba
|
||||
_PT1 = 0x00bb
|
||||
_PS0 = 0x00bc
|
||||
_PT2 = 0x00bd
|
||||
_PS1 = 0x00be
|
||||
_RI1 = 0x00c0
|
||||
_TI1 = 0x00c1
|
||||
_RB81 = 0x00c2
|
||||
_TB81 = 0x00c3
|
||||
_REN1 = 0x00c4
|
||||
_SM21 = 0x00c5
|
||||
_SM11 = 0x00c6
|
||||
_SM01 = 0x00c7
|
||||
_CP_RL2 = 0x00c8
|
||||
_C_T2 = 0x00c9
|
||||
_TR2 = 0x00ca
|
||||
_EXEN2 = 0x00cb
|
||||
_TCLK = 0x00cc
|
||||
_RCLK = 0x00cd
|
||||
_EXF2 = 0x00ce
|
||||
_TF2 = 0x00cf
|
||||
_P = 0x00d0
|
||||
_FL = 0x00d1
|
||||
_OV = 0x00d2
|
||||
_RS0 = 0x00d3
|
||||
_RS1 = 0x00d4
|
||||
_F0 = 0x00d5
|
||||
_AC = 0x00d6
|
||||
_CY = 0x00d7
|
||||
_INT6 = 0x00db
|
||||
_RESI = 0x00dc
|
||||
_ERESI = 0x00dd
|
||||
_SMOD1 = 0x00df
|
||||
_EIUSB = 0x00e8
|
||||
_EI2C = 0x00e9
|
||||
_EIEX4 = 0x00ea
|
||||
_EIEX5 = 0x00eb
|
||||
_EIEX6 = 0x00ec
|
||||
_PUSB = 0x00f8
|
||||
_PI2C = 0x00f9
|
||||
_EIPX4 = 0x00fa
|
||||
_EIPX5 = 0x00fb
|
||||
_EIPX6 = 0x00fc
|
||||
;--------------------------------------------------------
|
||||
; overlayable register banks
|
||||
;--------------------------------------------------------
|
||||
.area REG_BANK_0 (REL,OVR,DATA)
|
||||
.ds 8
|
||||
;--------------------------------------------------------
|
||||
; internal ram data
|
||||
;--------------------------------------------------------
|
||||
.area DSEG (DATA)
|
||||
;--------------------------------------------------------
|
||||
; overlayable items in internal ram
|
||||
;--------------------------------------------------------
|
||||
.area OSEG (OVR,DATA)
|
||||
;--------------------------------------------------------
|
||||
; indirectly addressable internal ram data
|
||||
;--------------------------------------------------------
|
||||
.area ISEG (DATA)
|
||||
;--------------------------------------------------------
|
||||
; absolute internal ram data
|
||||
;--------------------------------------------------------
|
||||
.area IABS (ABS,DATA)
|
||||
.area IABS (ABS,DATA)
|
||||
;--------------------------------------------------------
|
||||
; bit data
|
||||
;--------------------------------------------------------
|
||||
.area BSEG (BIT)
|
||||
;--------------------------------------------------------
|
||||
; paged external ram data
|
||||
;--------------------------------------------------------
|
||||
.area PSEG (PAG,XDATA)
|
||||
;--------------------------------------------------------
|
||||
; external ram data
|
||||
;--------------------------------------------------------
|
||||
.area XSEG (XDATA)
|
||||
_GPIF_WAVE_DATA = 0xe400
|
||||
_RES_WAVEDATA_END = 0xe480
|
||||
_CPUCS = 0xe600
|
||||
_IFCONFIG = 0xe601
|
||||
_PINFLAGSAB = 0xe602
|
||||
_PINFLAGSCD = 0xe603
|
||||
_FIFORESET = 0xe604
|
||||
_BREAKPT = 0xe605
|
||||
_BPADDRH = 0xe606
|
||||
_BPADDRL = 0xe607
|
||||
_UART230 = 0xe608
|
||||
_FIFOPINPOLAR = 0xe609
|
||||
_REVID = 0xe60a
|
||||
_REVCTL = 0xe60b
|
||||
_EP1OUTCFG = 0xe610
|
||||
_EP1INCFG = 0xe611
|
||||
_EP2CFG = 0xe612
|
||||
_EP4CFG = 0xe613
|
||||
_EP6CFG = 0xe614
|
||||
_EP8CFG = 0xe615
|
||||
_EP2FIFOCFG = 0xe618
|
||||
_EP4FIFOCFG = 0xe619
|
||||
_EP6FIFOCFG = 0xe61a
|
||||
_EP8FIFOCFG = 0xe61b
|
||||
_EP2AUTOINLENH = 0xe620
|
||||
_EP2AUTOINLENL = 0xe621
|
||||
_EP4AUTOINLENH = 0xe622
|
||||
_EP4AUTOINLENL = 0xe623
|
||||
_EP6AUTOINLENH = 0xe624
|
||||
_EP6AUTOINLENL = 0xe625
|
||||
_EP8AUTOINLENH = 0xe626
|
||||
_EP8AUTOINLENL = 0xe627
|
||||
_EP2FIFOPFH = 0xe630
|
||||
_EP2FIFOPFL = 0xe631
|
||||
_EP4FIFOPFH = 0xe632
|
||||
_EP4FIFOPFL = 0xe633
|
||||
_EP6FIFOPFH = 0xe634
|
||||
_EP6FIFOPFL = 0xe635
|
||||
_EP8FIFOPFH = 0xe636
|
||||
_EP8FIFOPFL = 0xe637
|
||||
_EP2ISOINPKTS = 0xe640
|
||||
_EP4ISOINPKTS = 0xe641
|
||||
_EP6ISOINPKTS = 0xe642
|
||||
_EP8ISOINPKTS = 0xe643
|
||||
_INPKTEND = 0xe648
|
||||
_OUTPKTEND = 0xe649
|
||||
_EP2FIFOIE = 0xe650
|
||||
_EP2FIFOIRQ = 0xe651
|
||||
_EP4FIFOIE = 0xe652
|
||||
_EP4FIFOIRQ = 0xe653
|
||||
_EP6FIFOIE = 0xe654
|
||||
_EP6FIFOIRQ = 0xe655
|
||||
_EP8FIFOIE = 0xe656
|
||||
_EP8FIFOIRQ = 0xe657
|
||||
_IBNIE = 0xe658
|
||||
_IBNIRQ = 0xe659
|
||||
_NAKIE = 0xe65a
|
||||
_NAKIRQ = 0xe65b
|
||||
_USBIE = 0xe65c
|
||||
_USBIRQ = 0xe65d
|
||||
_EPIE = 0xe65e
|
||||
_EPIRQ = 0xe65f
|
||||
_GPIFIE = 0xe660
|
||||
_GPIFIRQ = 0xe661
|
||||
_USBERRIE = 0xe662
|
||||
_USBERRIRQ = 0xe663
|
||||
_ERRCNTLIM = 0xe664
|
||||
_CLRERRCNT = 0xe665
|
||||
_INT2IVEC = 0xe666
|
||||
_INT4IVEC = 0xe667
|
||||
_INTSETUP = 0xe668
|
||||
_PORTACFG = 0xe670
|
||||
_PORTCCFG = 0xe671
|
||||
_PORTECFG = 0xe672
|
||||
_I2CS = 0xe678
|
||||
_I2DAT = 0xe679
|
||||
_I2CTL = 0xe67a
|
||||
_XAUTODAT1 = 0xe67b
|
||||
_XAUTODAT2 = 0xe67c
|
||||
_USBCS = 0xe680
|
||||
_SUSPEND = 0xe681
|
||||
_WAKEUPCS = 0xe682
|
||||
_TOGCTL = 0xe683
|
||||
_USBFRAMEH = 0xe684
|
||||
_USBFRAMEL = 0xe685
|
||||
_MICROFRAME = 0xe686
|
||||
_FNADDR = 0xe687
|
||||
_EP0BCH = 0xe68a
|
||||
_EP0BCL = 0xe68b
|
||||
_EP1OUTBC = 0xe68d
|
||||
_EP1INBC = 0xe68f
|
||||
_EP2BCH = 0xe690
|
||||
_EP2BCL = 0xe691
|
||||
_EP4BCH = 0xe694
|
||||
_EP4BCL = 0xe695
|
||||
_EP6BCH = 0xe698
|
||||
_EP6BCL = 0xe699
|
||||
_EP8BCH = 0xe69c
|
||||
_EP8BCL = 0xe69d
|
||||
_EP0CS = 0xe6a0
|
||||
_EP1OUTCS = 0xe6a1
|
||||
_EP1INCS = 0xe6a2
|
||||
_EP2CS = 0xe6a3
|
||||
_EP4CS = 0xe6a4
|
||||
_EP6CS = 0xe6a5
|
||||
_EP8CS = 0xe6a6
|
||||
_EP2FIFOFLGS = 0xe6a7
|
||||
_EP4FIFOFLGS = 0xe6a8
|
||||
_EP6FIFOFLGS = 0xe6a9
|
||||
_EP8FIFOFLGS = 0xe6aa
|
||||
_EP2FIFOBCH = 0xe6ab
|
||||
_EP2FIFOBCL = 0xe6ac
|
||||
_EP4FIFOBCH = 0xe6ad
|
||||
_EP4FIFOBCL = 0xe6ae
|
||||
_EP6FIFOBCH = 0xe6af
|
||||
_EP6FIFOBCL = 0xe6b0
|
||||
_EP8FIFOBCH = 0xe6b1
|
||||
_EP8FIFOBCL = 0xe6b2
|
||||
_SUDPTRH = 0xe6b3
|
||||
_SUDPTRL = 0xe6b4
|
||||
_SUDPTRCTL = 0xe6b5
|
||||
_SETUPDAT = 0xe6b8
|
||||
_GPIFWFSELECT = 0xe6c0
|
||||
_GPIFIDLECS = 0xe6c1
|
||||
_GPIFIDLECTL = 0xe6c2
|
||||
_GPIFCTLCFG = 0xe6c3
|
||||
_GPIFADRH = 0xe6c4
|
||||
_GPIFADRL = 0xe6c5
|
||||
_GPIFTCB3 = 0xe6ce
|
||||
_GPIFTCB2 = 0xe6cf
|
||||
_GPIFTCB1 = 0xe6d0
|
||||
_GPIFTCB0 = 0xe6d1
|
||||
_EP2GPIFFLGSEL = 0xe6d2
|
||||
_EP2GPIFPFSTOP = 0xe6d3
|
||||
_EP2GPIFTRIG = 0xe6d4
|
||||
_EP4GPIFFLGSEL = 0xe6da
|
||||
_EP4GPIFPFSTOP = 0xe6db
|
||||
_EP4GPIFTRIG = 0xe6dc
|
||||
_EP6GPIFFLGSEL = 0xe6e2
|
||||
_EP6GPIFPFSTOP = 0xe6e3
|
||||
_EP6GPIFTRIG = 0xe6e4
|
||||
_EP8GPIFFLGSEL = 0xe6ea
|
||||
_EP8GPIFPFSTOP = 0xe6eb
|
||||
_EP8GPIFTRIG = 0xe6ec
|
||||
_XGPIFSGLDATH = 0xe6f0
|
||||
_XGPIFSGLDATLX = 0xe6f1
|
||||
_XGPIFSGLDATLNOX = 0xe6f2
|
||||
_GPIFREADYCFG = 0xe6f3
|
||||
_GPIFREADYSTAT = 0xe6f4
|
||||
_GPIFABORT = 0xe6f5
|
||||
_FLOWSTATE = 0xe6c6
|
||||
_FLOWLOGIC = 0xe6c7
|
||||
_FLOWEQ0CTL = 0xe6c8
|
||||
_FLOWEQ1CTL = 0xe6c9
|
||||
_FLOWHOLDOFF = 0xe6ca
|
||||
_FLOWSTB = 0xe6cb
|
||||
_FLOWSTBEDGE = 0xe6cc
|
||||
_FLOWSTBHPERIOD = 0xe6cd
|
||||
_GPIFHOLDAMOUNT = 0xe60c
|
||||
_UDMACRCH = 0xe67d
|
||||
_UDMACRCL = 0xe67e
|
||||
_UDMACRCQUAL = 0xe67f
|
||||
_DBUG = 0xe6f8
|
||||
_TESTCFG = 0xe6f9
|
||||
_USBTEST = 0xe6fa
|
||||
_CT1 = 0xe6fb
|
||||
_CT2 = 0xe6fc
|
||||
_CT3 = 0xe6fd
|
||||
_CT4 = 0xe6fe
|
||||
_EP0BUF = 0xe740
|
||||
_EP1OUTBUF = 0xe780
|
||||
_EP1INBUF = 0xe7c0
|
||||
_EP2FIFOBUF = 0xf000
|
||||
_EP4FIFOBUF = 0xf400
|
||||
_EP6FIFOBUF = 0xf800
|
||||
_EP8FIFOBUF = 0xfc00
|
||||
;--------------------------------------------------------
|
||||
; absolute external ram data
|
||||
;--------------------------------------------------------
|
||||
.area XABS (ABS,XDATA)
|
||||
;--------------------------------------------------------
|
||||
; external initialized ram data
|
||||
;--------------------------------------------------------
|
||||
.area HOME (CODE)
|
||||
.area GSINIT0 (CODE)
|
||||
.area GSINIT1 (CODE)
|
||||
.area GSINIT2 (CODE)
|
||||
.area GSINIT3 (CODE)
|
||||
.area GSINIT4 (CODE)
|
||||
.area GSINIT5 (CODE)
|
||||
.area GSINIT (CODE)
|
||||
.area GSFINAL (CODE)
|
||||
.area CSEG (CODE)
|
||||
;--------------------------------------------------------
|
||||
; global & static initialisations
|
||||
;--------------------------------------------------------
|
||||
.area HOME (CODE)
|
||||
.area GSINIT (CODE)
|
||||
.area GSFINAL (CODE)
|
||||
.area GSINIT (CODE)
|
||||
;--------------------------------------------------------
|
||||
; Home
|
||||
;--------------------------------------------------------
|
||||
.area HOME (CODE)
|
||||
.area HOME (CODE)
|
||||
;--------------------------------------------------------
|
||||
; code
|
||||
;--------------------------------------------------------
|
||||
.area CSEG (CODE)
|
||||
;------------------------------------------------------------
|
||||
;Allocation info for local variables in function 'fx2_stall_ep0'
|
||||
;------------------------------------------------------------
|
||||
;------------------------------------------------------------
|
||||
; fx2utils.c:28: fx2_stall_ep0 (void)
|
||||
; -----------------------------------------
|
||||
; function fx2_stall_ep0
|
||||
; -----------------------------------------
|
||||
_fx2_stall_ep0:
|
||||
ar2 = 0x02
|
||||
ar3 = 0x03
|
||||
ar4 = 0x04
|
||||
ar5 = 0x05
|
||||
ar6 = 0x06
|
||||
ar7 = 0x07
|
||||
ar0 = 0x00
|
||||
ar1 = 0x01
|
||||
; fx2utils.c:30: EP0CS |= bmEPSTALL;
|
||||
mov dptr,#_EP0CS
|
||||
movx a,@dptr
|
||||
orl a,#0x01
|
||||
movx @dptr,a
|
||||
ret
|
||||
;------------------------------------------------------------
|
||||
;Allocation info for local variables in function 'fx2_reset_data_toggle'
|
||||
;------------------------------------------------------------
|
||||
;ep Allocated to registers r2
|
||||
;------------------------------------------------------------
|
||||
; fx2utils.c:34: fx2_reset_data_toggle (unsigned char ep)
|
||||
; -----------------------------------------
|
||||
; function fx2_reset_data_toggle
|
||||
; -----------------------------------------
|
||||
_fx2_reset_data_toggle:
|
||||
mov r2,dpl
|
||||
; fx2utils.c:36: TOGCTL = ((ep & 0x80) >> 3 | (ep & 0x0f));
|
||||
mov a,#0x80
|
||||
anl a,r2
|
||||
swap a
|
||||
rl a
|
||||
anl a,#0x1f
|
||||
mov r3,a
|
||||
mov a,#0x0F
|
||||
anl a,r2
|
||||
mov dptr,#_TOGCTL
|
||||
orl a,r3
|
||||
movx @dptr,a
|
||||
; fx2utils.c:37: TOGCTL |= bmRESETTOGGLE;
|
||||
mov dptr,#_TOGCTL
|
||||
movx a,@dptr
|
||||
orl a,#0x20
|
||||
movx @dptr,a
|
||||
ret
|
||||
;------------------------------------------------------------
|
||||
;Allocation info for local variables in function 'fx2_renumerate'
|
||||
;------------------------------------------------------------
|
||||
;------------------------------------------------------------
|
||||
; fx2utils.c:41: fx2_renumerate (void)
|
||||
; -----------------------------------------
|
||||
; function fx2_renumerate
|
||||
; -----------------------------------------
|
||||
_fx2_renumerate:
|
||||
; fx2utils.c:43: USBCS |= bmDISCON | bmRENUM;
|
||||
mov dptr,#_USBCS
|
||||
movx a,@dptr
|
||||
orl a,#0x0A
|
||||
movx @dptr,a
|
||||
; fx2utils.c:45: mdelay (250);
|
||||
mov dptr,#0x00FA
|
||||
lcall _mdelay
|
||||
; fx2utils.c:47: USBIRQ = 0xff; // clear any pending USB irqs...
|
||||
mov dptr,#_USBIRQ
|
||||
mov a,#0xFF
|
||||
movx @dptr,a
|
||||
; fx2utils.c:48: EPIRQ = 0xff; // they're from before the renumeration
|
||||
mov dptr,#_EPIRQ
|
||||
mov a,#0xFF
|
||||
movx @dptr,a
|
||||
; fx2utils.c:50: EXIF &= ~bmEXIF_USBINT;
|
||||
anl _EXIF,#0xEF
|
||||
; fx2utils.c:52: USBCS &= ~bmDISCON; // reconnect USB
|
||||
mov dptr,#_USBCS
|
||||
movx a,@dptr
|
||||
anl a,#0xF7
|
||||
movx @dptr,a
|
||||
ret
|
||||
.area CSEG (CODE)
|
||||
.area CONST (CODE)
|
||||
.area CABS (ABS,CODE)
|
||||
53
firmware/GN3S_v2/lib/fx2utils.c
Normal file
53
firmware/GN3S_v2/lib/fx2utils.c
Normal file
@@ -0,0 +1,53 @@
|
||||
/* -*- c++ -*- */
|
||||
/*
|
||||
* Copyright 2003 Free Software Foundation, Inc.
|
||||
*
|
||||
* This file is part of GNU Radio
|
||||
*
|
||||
* GNU Radio is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* GNU Radio is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with GNU Radio; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
|
||||
* Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#include "fx2utils.h"
|
||||
#include "fx2regs.h"
|
||||
#include "delay.h"
|
||||
|
||||
void
|
||||
fx2_stall_ep0 (void)
|
||||
{
|
||||
EP0CS |= bmEPSTALL;
|
||||
}
|
||||
|
||||
void
|
||||
fx2_reset_data_toggle (unsigned char ep)
|
||||
{
|
||||
TOGCTL = ((ep & 0x80) >> 3 | (ep & 0x0f));
|
||||
TOGCTL |= bmRESETTOGGLE;
|
||||
}
|
||||
|
||||
void
|
||||
fx2_renumerate (void)
|
||||
{
|
||||
USBCS |= bmDISCON | bmRENUM;
|
||||
|
||||
mdelay (250);
|
||||
|
||||
USBIRQ = 0xff; // clear any pending USB irqs...
|
||||
EPIRQ = 0xff; // they're from before the renumeration
|
||||
|
||||
EXIF &= ~bmEXIF_USBINT;
|
||||
|
||||
USBCS &= ~bmDISCON; // reconnect USB
|
||||
}
|
||||
821
firmware/GN3S_v2/lib/fx2utils.lst
Normal file
821
firmware/GN3S_v2/lib/fx2utils.lst
Normal file
@@ -0,0 +1,821 @@
|
||||
1 ;--------------------------------------------------------
|
||||
2 ; File Created by SDCC : free open source ANSI-C Compiler
|
||||
3 ; Version 2.9.0 #5416 (Feb 3 2010) (UNIX)
|
||||
4 ; This file was generated Mon Jul 30 11:40:52 2012
|
||||
5 ;--------------------------------------------------------
|
||||
6 .module fx2utils
|
||||
7 .optsdcc -mmcs51 --model-small
|
||||
8
|
||||
9 ;--------------------------------------------------------
|
||||
10 ; Public variables in this module
|
||||
11 ;--------------------------------------------------------
|
||||
12 .globl _EIPX6
|
||||
13 .globl _EIPX5
|
||||
14 .globl _EIPX4
|
||||
15 .globl _PI2C
|
||||
16 .globl _PUSB
|
||||
17 .globl _EIEX6
|
||||
18 .globl _EIEX5
|
||||
19 .globl _EIEX4
|
||||
20 .globl _EI2C
|
||||
21 .globl _EIUSB
|
||||
22 .globl _SMOD1
|
||||
23 .globl _ERESI
|
||||
24 .globl _RESI
|
||||
25 .globl _INT6
|
||||
26 .globl _CY
|
||||
27 .globl _AC
|
||||
28 .globl _F0
|
||||
29 .globl _RS1
|
||||
30 .globl _RS0
|
||||
31 .globl _OV
|
||||
32 .globl _FL
|
||||
33 .globl _P
|
||||
34 .globl _TF2
|
||||
35 .globl _EXF2
|
||||
36 .globl _RCLK
|
||||
37 .globl _TCLK
|
||||
38 .globl _EXEN2
|
||||
39 .globl _TR2
|
||||
40 .globl _C_T2
|
||||
41 .globl _CP_RL2
|
||||
42 .globl _SM01
|
||||
43 .globl _SM11
|
||||
44 .globl _SM21
|
||||
45 .globl _REN1
|
||||
46 .globl _TB81
|
||||
47 .globl _RB81
|
||||
48 .globl _TI1
|
||||
49 .globl _RI1
|
||||
50 .globl _PS1
|
||||
51 .globl _PT2
|
||||
52 .globl _PS0
|
||||
53 .globl _PT1
|
||||
54 .globl _PX1
|
||||
55 .globl _PT0
|
||||
56 .globl _PX0
|
||||
57 .globl _D7
|
||||
58 .globl _D6
|
||||
59 .globl _D5
|
||||
60 .globl _D4
|
||||
61 .globl _D3
|
||||
62 .globl _D2
|
||||
63 .globl _D1
|
||||
64 .globl _D0
|
||||
65 .globl _EA
|
||||
66 .globl _ES1
|
||||
67 .globl _ET2
|
||||
68 .globl _ES0
|
||||
69 .globl _ET1
|
||||
70 .globl _EX1
|
||||
71 .globl _ET0
|
||||
72 .globl _EX0
|
||||
73 .globl _SM0
|
||||
74 .globl _SM1
|
||||
75 .globl _SM2
|
||||
76 .globl _REN
|
||||
77 .globl _TB8
|
||||
78 .globl _RB8
|
||||
79 .globl _TI
|
||||
80 .globl _RI
|
||||
81 .globl _TF1
|
||||
82 .globl _TR1
|
||||
83 .globl _TF0
|
||||
84 .globl _TR0
|
||||
85 .globl _IE1
|
||||
86 .globl _IT1
|
||||
87 .globl _IE0
|
||||
88 .globl _IT0
|
||||
89 .globl _SEL
|
||||
90 .globl _A7
|
||||
91 .globl _A6
|
||||
92 .globl _A5
|
||||
93 .globl _A4
|
||||
94 .globl _A3
|
||||
95 .globl _A2
|
||||
96 .globl _A1
|
||||
97 .globl _A0
|
||||
98 .globl _EIP
|
||||
99 .globl _B
|
||||
100 .globl _EIE
|
||||
101 .globl _ACC
|
||||
102 .globl _EICON
|
||||
103 .globl _PSW
|
||||
104 .globl _TH2
|
||||
105 .globl _TL2
|
||||
106 .globl _RCAP2H
|
||||
107 .globl _RCAP2L
|
||||
108 .globl _T2CON
|
||||
109 .globl _SBUF1
|
||||
110 .globl _SCON1
|
||||
111 .globl _GPIFSGLDATLNOX
|
||||
112 .globl _GPIFSGLDATLX
|
||||
113 .globl _GPIFSGLDATH
|
||||
114 .globl _GPIFTRIG
|
||||
115 .globl _EP01STAT
|
||||
116 .globl _IP
|
||||
117 .globl _OEE
|
||||
118 .globl _OED
|
||||
119 .globl _OEC
|
||||
120 .globl _OEB
|
||||
121 .globl _OEA
|
||||
122 .globl _IOE
|
||||
123 .globl _IOD
|
||||
124 .globl _AUTOPTRSETUP
|
||||
125 .globl _EP68FIFOFLGS
|
||||
126 .globl _EP24FIFOFLGS
|
||||
127 .globl _EP2468STAT
|
||||
128 .globl _IE
|
||||
129 .globl _INT4CLR
|
||||
130 .globl _INT2CLR
|
||||
131 .globl _IOC
|
||||
132 .globl _AUTODAT2
|
||||
133 .globl _AUTOPTRL2
|
||||
134 .globl _AUTOPTRH2
|
||||
135 .globl _AUTODAT1
|
||||
136 .globl _APTR1L
|
||||
137 .globl _APTR1H
|
||||
138 .globl _SBUF0
|
||||
139 .globl _SCON0
|
||||
140 .globl _MPAGE
|
||||
141 .globl _EXIF
|
||||
142 .globl _IOB
|
||||
143 .globl _CKCON
|
||||
144 .globl _TH1
|
||||
145 .globl _TH0
|
||||
146 .globl _TL1
|
||||
147 .globl _TL0
|
||||
148 .globl _TMOD
|
||||
149 .globl _TCON
|
||||
150 .globl _PCON
|
||||
151 .globl _DPS
|
||||
152 .globl _DPH1
|
||||
153 .globl _DPL1
|
||||
154 .globl _DPH
|
||||
155 .globl _DPL
|
||||
156 .globl _SP
|
||||
157 .globl _IOA
|
||||
158 .globl _EP8FIFOBUF
|
||||
159 .globl _EP6FIFOBUF
|
||||
160 .globl _EP4FIFOBUF
|
||||
161 .globl _EP2FIFOBUF
|
||||
162 .globl _EP1INBUF
|
||||
163 .globl _EP1OUTBUF
|
||||
164 .globl _EP0BUF
|
||||
165 .globl _CT4
|
||||
166 .globl _CT3
|
||||
167 .globl _CT2
|
||||
168 .globl _CT1
|
||||
169 .globl _USBTEST
|
||||
170 .globl _TESTCFG
|
||||
171 .globl _DBUG
|
||||
172 .globl _UDMACRCQUAL
|
||||
173 .globl _UDMACRCL
|
||||
174 .globl _UDMACRCH
|
||||
175 .globl _GPIFHOLDAMOUNT
|
||||
176 .globl _FLOWSTBHPERIOD
|
||||
177 .globl _FLOWSTBEDGE
|
||||
178 .globl _FLOWSTB
|
||||
179 .globl _FLOWHOLDOFF
|
||||
180 .globl _FLOWEQ1CTL
|
||||
181 .globl _FLOWEQ0CTL
|
||||
182 .globl _FLOWLOGIC
|
||||
183 .globl _FLOWSTATE
|
||||
184 .globl _GPIFABORT
|
||||
185 .globl _GPIFREADYSTAT
|
||||
186 .globl _GPIFREADYCFG
|
||||
187 .globl _XGPIFSGLDATLNOX
|
||||
188 .globl _XGPIFSGLDATLX
|
||||
189 .globl _XGPIFSGLDATH
|
||||
190 .globl _EP8GPIFTRIG
|
||||
191 .globl _EP8GPIFPFSTOP
|
||||
192 .globl _EP8GPIFFLGSEL
|
||||
193 .globl _EP6GPIFTRIG
|
||||
194 .globl _EP6GPIFPFSTOP
|
||||
195 .globl _EP6GPIFFLGSEL
|
||||
196 .globl _EP4GPIFTRIG
|
||||
197 .globl _EP4GPIFPFSTOP
|
||||
198 .globl _EP4GPIFFLGSEL
|
||||
199 .globl _EP2GPIFTRIG
|
||||
200 .globl _EP2GPIFPFSTOP
|
||||
201 .globl _EP2GPIFFLGSEL
|
||||
202 .globl _GPIFTCB0
|
||||
203 .globl _GPIFTCB1
|
||||
204 .globl _GPIFTCB2
|
||||
205 .globl _GPIFTCB3
|
||||
206 .globl _GPIFADRL
|
||||
207 .globl _GPIFADRH
|
||||
208 .globl _GPIFCTLCFG
|
||||
209 .globl _GPIFIDLECTL
|
||||
210 .globl _GPIFIDLECS
|
||||
211 .globl _GPIFWFSELECT
|
||||
212 .globl _SETUPDAT
|
||||
213 .globl _SUDPTRCTL
|
||||
214 .globl _SUDPTRL
|
||||
215 .globl _SUDPTRH
|
||||
216 .globl _EP8FIFOBCL
|
||||
217 .globl _EP8FIFOBCH
|
||||
218 .globl _EP6FIFOBCL
|
||||
219 .globl _EP6FIFOBCH
|
||||
220 .globl _EP4FIFOBCL
|
||||
221 .globl _EP4FIFOBCH
|
||||
222 .globl _EP2FIFOBCL
|
||||
223 .globl _EP2FIFOBCH
|
||||
224 .globl _EP8FIFOFLGS
|
||||
225 .globl _EP6FIFOFLGS
|
||||
226 .globl _EP4FIFOFLGS
|
||||
227 .globl _EP2FIFOFLGS
|
||||
228 .globl _EP8CS
|
||||
229 .globl _EP6CS
|
||||
230 .globl _EP4CS
|
||||
231 .globl _EP2CS
|
||||
232 .globl _EP1INCS
|
||||
233 .globl _EP1OUTCS
|
||||
234 .globl _EP0CS
|
||||
235 .globl _EP8BCL
|
||||
236 .globl _EP8BCH
|
||||
237 .globl _EP6BCL
|
||||
238 .globl _EP6BCH
|
||||
239 .globl _EP4BCL
|
||||
240 .globl _EP4BCH
|
||||
241 .globl _EP2BCL
|
||||
242 .globl _EP2BCH
|
||||
243 .globl _EP1INBC
|
||||
244 .globl _EP1OUTBC
|
||||
245 .globl _EP0BCL
|
||||
246 .globl _EP0BCH
|
||||
247 .globl _FNADDR
|
||||
248 .globl _MICROFRAME
|
||||
249 .globl _USBFRAMEL
|
||||
250 .globl _USBFRAMEH
|
||||
251 .globl _TOGCTL
|
||||
252 .globl _WAKEUPCS
|
||||
253 .globl _SUSPEND
|
||||
254 .globl _USBCS
|
||||
255 .globl _XAUTODAT2
|
||||
256 .globl _XAUTODAT1
|
||||
257 .globl _I2CTL
|
||||
258 .globl _I2DAT
|
||||
259 .globl _I2CS
|
||||
260 .globl _PORTECFG
|
||||
261 .globl _PORTCCFG
|
||||
262 .globl _PORTACFG
|
||||
263 .globl _INTSETUP
|
||||
264 .globl _INT4IVEC
|
||||
265 .globl _INT2IVEC
|
||||
266 .globl _CLRERRCNT
|
||||
267 .globl _ERRCNTLIM
|
||||
268 .globl _USBERRIRQ
|
||||
269 .globl _USBERRIE
|
||||
270 .globl _GPIFIRQ
|
||||
271 .globl _GPIFIE
|
||||
272 .globl _EPIRQ
|
||||
273 .globl _EPIE
|
||||
274 .globl _USBIRQ
|
||||
275 .globl _USBIE
|
||||
276 .globl _NAKIRQ
|
||||
277 .globl _NAKIE
|
||||
278 .globl _IBNIRQ
|
||||
279 .globl _IBNIE
|
||||
280 .globl _EP8FIFOIRQ
|
||||
281 .globl _EP8FIFOIE
|
||||
282 .globl _EP6FIFOIRQ
|
||||
283 .globl _EP6FIFOIE
|
||||
284 .globl _EP4FIFOIRQ
|
||||
285 .globl _EP4FIFOIE
|
||||
286 .globl _EP2FIFOIRQ
|
||||
287 .globl _EP2FIFOIE
|
||||
288 .globl _OUTPKTEND
|
||||
289 .globl _INPKTEND
|
||||
290 .globl _EP8ISOINPKTS
|
||||
291 .globl _EP6ISOINPKTS
|
||||
292 .globl _EP4ISOINPKTS
|
||||
293 .globl _EP2ISOINPKTS
|
||||
294 .globl _EP8FIFOPFL
|
||||
295 .globl _EP8FIFOPFH
|
||||
296 .globl _EP6FIFOPFL
|
||||
297 .globl _EP6FIFOPFH
|
||||
298 .globl _EP4FIFOPFL
|
||||
299 .globl _EP4FIFOPFH
|
||||
300 .globl _EP2FIFOPFL
|
||||
301 .globl _EP2FIFOPFH
|
||||
302 .globl _EP8AUTOINLENL
|
||||
303 .globl _EP8AUTOINLENH
|
||||
304 .globl _EP6AUTOINLENL
|
||||
305 .globl _EP6AUTOINLENH
|
||||
306 .globl _EP4AUTOINLENL
|
||||
307 .globl _EP4AUTOINLENH
|
||||
308 .globl _EP2AUTOINLENL
|
||||
309 .globl _EP2AUTOINLENH
|
||||
310 .globl _EP8FIFOCFG
|
||||
311 .globl _EP6FIFOCFG
|
||||
312 .globl _EP4FIFOCFG
|
||||
313 .globl _EP2FIFOCFG
|
||||
314 .globl _EP8CFG
|
||||
315 .globl _EP6CFG
|
||||
316 .globl _EP4CFG
|
||||
317 .globl _EP2CFG
|
||||
318 .globl _EP1INCFG
|
||||
319 .globl _EP1OUTCFG
|
||||
320 .globl _REVCTL
|
||||
321 .globl _REVID
|
||||
322 .globl _FIFOPINPOLAR
|
||||
323 .globl _UART230
|
||||
324 .globl _BPADDRL
|
||||
325 .globl _BPADDRH
|
||||
326 .globl _BREAKPT
|
||||
327 .globl _FIFORESET
|
||||
328 .globl _PINFLAGSCD
|
||||
329 .globl _PINFLAGSAB
|
||||
330 .globl _IFCONFIG
|
||||
331 .globl _CPUCS
|
||||
332 .globl _RES_WAVEDATA_END
|
||||
333 .globl _GPIF_WAVE_DATA
|
||||
334 .globl _fx2_stall_ep0
|
||||
335 .globl _fx2_reset_data_toggle
|
||||
336 .globl _fx2_renumerate
|
||||
337 ;--------------------------------------------------------
|
||||
338 ; special function registers
|
||||
339 ;--------------------------------------------------------
|
||||
340 .area RSEG (DATA)
|
||||
0080 341 _IOA = 0x0080
|
||||
0081 342 _SP = 0x0081
|
||||
0082 343 _DPL = 0x0082
|
||||
0083 344 _DPH = 0x0083
|
||||
0084 345 _DPL1 = 0x0084
|
||||
0085 346 _DPH1 = 0x0085
|
||||
0086 347 _DPS = 0x0086
|
||||
0087 348 _PCON = 0x0087
|
||||
0088 349 _TCON = 0x0088
|
||||
0089 350 _TMOD = 0x0089
|
||||
008A 351 _TL0 = 0x008a
|
||||
008B 352 _TL1 = 0x008b
|
||||
008C 353 _TH0 = 0x008c
|
||||
008D 354 _TH1 = 0x008d
|
||||
008E 355 _CKCON = 0x008e
|
||||
0090 356 _IOB = 0x0090
|
||||
0091 357 _EXIF = 0x0091
|
||||
0092 358 _MPAGE = 0x0092
|
||||
0098 359 _SCON0 = 0x0098
|
||||
0099 360 _SBUF0 = 0x0099
|
||||
009A 361 _APTR1H = 0x009a
|
||||
009B 362 _APTR1L = 0x009b
|
||||
009C 363 _AUTODAT1 = 0x009c
|
||||
009D 364 _AUTOPTRH2 = 0x009d
|
||||
009E 365 _AUTOPTRL2 = 0x009e
|
||||
009F 366 _AUTODAT2 = 0x009f
|
||||
00A0 367 _IOC = 0x00a0
|
||||
00A1 368 _INT2CLR = 0x00a1
|
||||
00A2 369 _INT4CLR = 0x00a2
|
||||
00A8 370 _IE = 0x00a8
|
||||
00AA 371 _EP2468STAT = 0x00aa
|
||||
00AB 372 _EP24FIFOFLGS = 0x00ab
|
||||
00AC 373 _EP68FIFOFLGS = 0x00ac
|
||||
00AF 374 _AUTOPTRSETUP = 0x00af
|
||||
00B0 375 _IOD = 0x00b0
|
||||
00B1 376 _IOE = 0x00b1
|
||||
00B2 377 _OEA = 0x00b2
|
||||
00B3 378 _OEB = 0x00b3
|
||||
00B4 379 _OEC = 0x00b4
|
||||
00B5 380 _OED = 0x00b5
|
||||
00B6 381 _OEE = 0x00b6
|
||||
00B8 382 _IP = 0x00b8
|
||||
00BA 383 _EP01STAT = 0x00ba
|
||||
00BB 384 _GPIFTRIG = 0x00bb
|
||||
00BD 385 _GPIFSGLDATH = 0x00bd
|
||||
00BE 386 _GPIFSGLDATLX = 0x00be
|
||||
00BF 387 _GPIFSGLDATLNOX = 0x00bf
|
||||
00C0 388 _SCON1 = 0x00c0
|
||||
00C1 389 _SBUF1 = 0x00c1
|
||||
00C8 390 _T2CON = 0x00c8
|
||||
00CA 391 _RCAP2L = 0x00ca
|
||||
00CB 392 _RCAP2H = 0x00cb
|
||||
00CC 393 _TL2 = 0x00cc
|
||||
00CD 394 _TH2 = 0x00cd
|
||||
00D0 395 _PSW = 0x00d0
|
||||
00D8 396 _EICON = 0x00d8
|
||||
00E0 397 _ACC = 0x00e0
|
||||
00E8 398 _EIE = 0x00e8
|
||||
00F0 399 _B = 0x00f0
|
||||
00F8 400 _EIP = 0x00f8
|
||||
401 ;--------------------------------------------------------
|
||||
402 ; special function bits
|
||||
403 ;--------------------------------------------------------
|
||||
404 .area RSEG (DATA)
|
||||
0080 405 _A0 = 0x0080
|
||||
0081 406 _A1 = 0x0081
|
||||
0082 407 _A2 = 0x0082
|
||||
0083 408 _A3 = 0x0083
|
||||
0084 409 _A4 = 0x0084
|
||||
0085 410 _A5 = 0x0085
|
||||
0086 411 _A6 = 0x0086
|
||||
0087 412 _A7 = 0x0087
|
||||
0086 413 _SEL = 0x0086
|
||||
0088 414 _IT0 = 0x0088
|
||||
0089 415 _IE0 = 0x0089
|
||||
008A 416 _IT1 = 0x008a
|
||||
008B 417 _IE1 = 0x008b
|
||||
008C 418 _TR0 = 0x008c
|
||||
008D 419 _TF0 = 0x008d
|
||||
008E 420 _TR1 = 0x008e
|
||||
008F 421 _TF1 = 0x008f
|
||||
0098 422 _RI = 0x0098
|
||||
0099 423 _TI = 0x0099
|
||||
009A 424 _RB8 = 0x009a
|
||||
009B 425 _TB8 = 0x009b
|
||||
009C 426 _REN = 0x009c
|
||||
009D 427 _SM2 = 0x009d
|
||||
009E 428 _SM1 = 0x009e
|
||||
009F 429 _SM0 = 0x009f
|
||||
00A8 430 _EX0 = 0x00a8
|
||||
00A9 431 _ET0 = 0x00a9
|
||||
00AA 432 _EX1 = 0x00aa
|
||||
00AB 433 _ET1 = 0x00ab
|
||||
00AC 434 _ES0 = 0x00ac
|
||||
00AD 435 _ET2 = 0x00ad
|
||||
00AE 436 _ES1 = 0x00ae
|
||||
00AF 437 _EA = 0x00af
|
||||
00B0 438 _D0 = 0x00b0
|
||||
00B1 439 _D1 = 0x00b1
|
||||
00B2 440 _D2 = 0x00b2
|
||||
00B3 441 _D3 = 0x00b3
|
||||
00B4 442 _D4 = 0x00b4
|
||||
00B5 443 _D5 = 0x00b5
|
||||
00B6 444 _D6 = 0x00b6
|
||||
00B7 445 _D7 = 0x00b7
|
||||
00B8 446 _PX0 = 0x00b8
|
||||
00B9 447 _PT0 = 0x00b9
|
||||
00BA 448 _PX1 = 0x00ba
|
||||
00BB 449 _PT1 = 0x00bb
|
||||
00BC 450 _PS0 = 0x00bc
|
||||
00BD 451 _PT2 = 0x00bd
|
||||
00BE 452 _PS1 = 0x00be
|
||||
00C0 453 _RI1 = 0x00c0
|
||||
00C1 454 _TI1 = 0x00c1
|
||||
00C2 455 _RB81 = 0x00c2
|
||||
00C3 456 _TB81 = 0x00c3
|
||||
00C4 457 _REN1 = 0x00c4
|
||||
00C5 458 _SM21 = 0x00c5
|
||||
00C6 459 _SM11 = 0x00c6
|
||||
00C7 460 _SM01 = 0x00c7
|
||||
00C8 461 _CP_RL2 = 0x00c8
|
||||
00C9 462 _C_T2 = 0x00c9
|
||||
00CA 463 _TR2 = 0x00ca
|
||||
00CB 464 _EXEN2 = 0x00cb
|
||||
00CC 465 _TCLK = 0x00cc
|
||||
00CD 466 _RCLK = 0x00cd
|
||||
00CE 467 _EXF2 = 0x00ce
|
||||
00CF 468 _TF2 = 0x00cf
|
||||
00D0 469 _P = 0x00d0
|
||||
00D1 470 _FL = 0x00d1
|
||||
00D2 471 _OV = 0x00d2
|
||||
00D3 472 _RS0 = 0x00d3
|
||||
00D4 473 _RS1 = 0x00d4
|
||||
00D5 474 _F0 = 0x00d5
|
||||
00D6 475 _AC = 0x00d6
|
||||
00D7 476 _CY = 0x00d7
|
||||
00DB 477 _INT6 = 0x00db
|
||||
00DC 478 _RESI = 0x00dc
|
||||
00DD 479 _ERESI = 0x00dd
|
||||
00DF 480 _SMOD1 = 0x00df
|
||||
00E8 481 _EIUSB = 0x00e8
|
||||
00E9 482 _EI2C = 0x00e9
|
||||
00EA 483 _EIEX4 = 0x00ea
|
||||
00EB 484 _EIEX5 = 0x00eb
|
||||
00EC 485 _EIEX6 = 0x00ec
|
||||
00F8 486 _PUSB = 0x00f8
|
||||
00F9 487 _PI2C = 0x00f9
|
||||
00FA 488 _EIPX4 = 0x00fa
|
||||
00FB 489 _EIPX5 = 0x00fb
|
||||
00FC 490 _EIPX6 = 0x00fc
|
||||
491 ;--------------------------------------------------------
|
||||
492 ; overlayable register banks
|
||||
493 ;--------------------------------------------------------
|
||||
494 .area REG_BANK_0 (REL,OVR,DATA)
|
||||
0000 495 .ds 8
|
||||
496 ;--------------------------------------------------------
|
||||
497 ; internal ram data
|
||||
498 ;--------------------------------------------------------
|
||||
499 .area DSEG (DATA)
|
||||
500 ;--------------------------------------------------------
|
||||
501 ; overlayable items in internal ram
|
||||
502 ;--------------------------------------------------------
|
||||
503 .area OSEG (OVR,DATA)
|
||||
504 ;--------------------------------------------------------
|
||||
505 ; indirectly addressable internal ram data
|
||||
506 ;--------------------------------------------------------
|
||||
507 .area ISEG (DATA)
|
||||
508 ;--------------------------------------------------------
|
||||
509 ; absolute internal ram data
|
||||
510 ;--------------------------------------------------------
|
||||
511 .area IABS (ABS,DATA)
|
||||
512 .area IABS (ABS,DATA)
|
||||
513 ;--------------------------------------------------------
|
||||
514 ; bit data
|
||||
515 ;--------------------------------------------------------
|
||||
516 .area BSEG (BIT)
|
||||
517 ;--------------------------------------------------------
|
||||
518 ; paged external ram data
|
||||
519 ;--------------------------------------------------------
|
||||
520 .area PSEG (PAG,XDATA)
|
||||
521 ;--------------------------------------------------------
|
||||
522 ; external ram data
|
||||
523 ;--------------------------------------------------------
|
||||
524 .area XSEG (XDATA)
|
||||
E400 525 _GPIF_WAVE_DATA = 0xe400
|
||||
E480 526 _RES_WAVEDATA_END = 0xe480
|
||||
E600 527 _CPUCS = 0xe600
|
||||
E601 528 _IFCONFIG = 0xe601
|
||||
E602 529 _PINFLAGSAB = 0xe602
|
||||
E603 530 _PINFLAGSCD = 0xe603
|
||||
E604 531 _FIFORESET = 0xe604
|
||||
E605 532 _BREAKPT = 0xe605
|
||||
E606 533 _BPADDRH = 0xe606
|
||||
E607 534 _BPADDRL = 0xe607
|
||||
E608 535 _UART230 = 0xe608
|
||||
E609 536 _FIFOPINPOLAR = 0xe609
|
||||
E60A 537 _REVID = 0xe60a
|
||||
E60B 538 _REVCTL = 0xe60b
|
||||
E610 539 _EP1OUTCFG = 0xe610
|
||||
E611 540 _EP1INCFG = 0xe611
|
||||
E612 541 _EP2CFG = 0xe612
|
||||
E613 542 _EP4CFG = 0xe613
|
||||
E614 543 _EP6CFG = 0xe614
|
||||
E615 544 _EP8CFG = 0xe615
|
||||
E618 545 _EP2FIFOCFG = 0xe618
|
||||
E619 546 _EP4FIFOCFG = 0xe619
|
||||
E61A 547 _EP6FIFOCFG = 0xe61a
|
||||
E61B 548 _EP8FIFOCFG = 0xe61b
|
||||
E620 549 _EP2AUTOINLENH = 0xe620
|
||||
E621 550 _EP2AUTOINLENL = 0xe621
|
||||
E622 551 _EP4AUTOINLENH = 0xe622
|
||||
E623 552 _EP4AUTOINLENL = 0xe623
|
||||
E624 553 _EP6AUTOINLENH = 0xe624
|
||||
E625 554 _EP6AUTOINLENL = 0xe625
|
||||
E626 555 _EP8AUTOINLENH = 0xe626
|
||||
E627 556 _EP8AUTOINLENL = 0xe627
|
||||
E630 557 _EP2FIFOPFH = 0xe630
|
||||
E631 558 _EP2FIFOPFL = 0xe631
|
||||
E632 559 _EP4FIFOPFH = 0xe632
|
||||
E633 560 _EP4FIFOPFL = 0xe633
|
||||
E634 561 _EP6FIFOPFH = 0xe634
|
||||
E635 562 _EP6FIFOPFL = 0xe635
|
||||
E636 563 _EP8FIFOPFH = 0xe636
|
||||
E637 564 _EP8FIFOPFL = 0xe637
|
||||
E640 565 _EP2ISOINPKTS = 0xe640
|
||||
E641 566 _EP4ISOINPKTS = 0xe641
|
||||
E642 567 _EP6ISOINPKTS = 0xe642
|
||||
E643 568 _EP8ISOINPKTS = 0xe643
|
||||
E648 569 _INPKTEND = 0xe648
|
||||
E649 570 _OUTPKTEND = 0xe649
|
||||
E650 571 _EP2FIFOIE = 0xe650
|
||||
E651 572 _EP2FIFOIRQ = 0xe651
|
||||
E652 573 _EP4FIFOIE = 0xe652
|
||||
E653 574 _EP4FIFOIRQ = 0xe653
|
||||
E654 575 _EP6FIFOIE = 0xe654
|
||||
E655 576 _EP6FIFOIRQ = 0xe655
|
||||
E656 577 _EP8FIFOIE = 0xe656
|
||||
E657 578 _EP8FIFOIRQ = 0xe657
|
||||
E658 579 _IBNIE = 0xe658
|
||||
E659 580 _IBNIRQ = 0xe659
|
||||
E65A 581 _NAKIE = 0xe65a
|
||||
E65B 582 _NAKIRQ = 0xe65b
|
||||
E65C 583 _USBIE = 0xe65c
|
||||
E65D 584 _USBIRQ = 0xe65d
|
||||
E65E 585 _EPIE = 0xe65e
|
||||
E65F 586 _EPIRQ = 0xe65f
|
||||
E660 587 _GPIFIE = 0xe660
|
||||
E661 588 _GPIFIRQ = 0xe661
|
||||
E662 589 _USBERRIE = 0xe662
|
||||
E663 590 _USBERRIRQ = 0xe663
|
||||
E664 591 _ERRCNTLIM = 0xe664
|
||||
E665 592 _CLRERRCNT = 0xe665
|
||||
E666 593 _INT2IVEC = 0xe666
|
||||
E667 594 _INT4IVEC = 0xe667
|
||||
E668 595 _INTSETUP = 0xe668
|
||||
E670 596 _PORTACFG = 0xe670
|
||||
E671 597 _PORTCCFG = 0xe671
|
||||
E672 598 _PORTECFG = 0xe672
|
||||
E678 599 _I2CS = 0xe678
|
||||
E679 600 _I2DAT = 0xe679
|
||||
E67A 601 _I2CTL = 0xe67a
|
||||
E67B 602 _XAUTODAT1 = 0xe67b
|
||||
E67C 603 _XAUTODAT2 = 0xe67c
|
||||
E680 604 _USBCS = 0xe680
|
||||
E681 605 _SUSPEND = 0xe681
|
||||
E682 606 _WAKEUPCS = 0xe682
|
||||
E683 607 _TOGCTL = 0xe683
|
||||
E684 608 _USBFRAMEH = 0xe684
|
||||
E685 609 _USBFRAMEL = 0xe685
|
||||
E686 610 _MICROFRAME = 0xe686
|
||||
E687 611 _FNADDR = 0xe687
|
||||
E68A 612 _EP0BCH = 0xe68a
|
||||
E68B 613 _EP0BCL = 0xe68b
|
||||
E68D 614 _EP1OUTBC = 0xe68d
|
||||
E68F 615 _EP1INBC = 0xe68f
|
||||
E690 616 _EP2BCH = 0xe690
|
||||
E691 617 _EP2BCL = 0xe691
|
||||
E694 618 _EP4BCH = 0xe694
|
||||
E695 619 _EP4BCL = 0xe695
|
||||
E698 620 _EP6BCH = 0xe698
|
||||
E699 621 _EP6BCL = 0xe699
|
||||
E69C 622 _EP8BCH = 0xe69c
|
||||
E69D 623 _EP8BCL = 0xe69d
|
||||
E6A0 624 _EP0CS = 0xe6a0
|
||||
E6A1 625 _EP1OUTCS = 0xe6a1
|
||||
E6A2 626 _EP1INCS = 0xe6a2
|
||||
E6A3 627 _EP2CS = 0xe6a3
|
||||
E6A4 628 _EP4CS = 0xe6a4
|
||||
E6A5 629 _EP6CS = 0xe6a5
|
||||
E6A6 630 _EP8CS = 0xe6a6
|
||||
E6A7 631 _EP2FIFOFLGS = 0xe6a7
|
||||
E6A8 632 _EP4FIFOFLGS = 0xe6a8
|
||||
E6A9 633 _EP6FIFOFLGS = 0xe6a9
|
||||
E6AA 634 _EP8FIFOFLGS = 0xe6aa
|
||||
E6AB 635 _EP2FIFOBCH = 0xe6ab
|
||||
E6AC 636 _EP2FIFOBCL = 0xe6ac
|
||||
E6AD 637 _EP4FIFOBCH = 0xe6ad
|
||||
E6AE 638 _EP4FIFOBCL = 0xe6ae
|
||||
E6AF 639 _EP6FIFOBCH = 0xe6af
|
||||
E6B0 640 _EP6FIFOBCL = 0xe6b0
|
||||
E6B1 641 _EP8FIFOBCH = 0xe6b1
|
||||
E6B2 642 _EP8FIFOBCL = 0xe6b2
|
||||
E6B3 643 _SUDPTRH = 0xe6b3
|
||||
E6B4 644 _SUDPTRL = 0xe6b4
|
||||
E6B5 645 _SUDPTRCTL = 0xe6b5
|
||||
E6B8 646 _SETUPDAT = 0xe6b8
|
||||
E6C0 647 _GPIFWFSELECT = 0xe6c0
|
||||
E6C1 648 _GPIFIDLECS = 0xe6c1
|
||||
E6C2 649 _GPIFIDLECTL = 0xe6c2
|
||||
E6C3 650 _GPIFCTLCFG = 0xe6c3
|
||||
E6C4 651 _GPIFADRH = 0xe6c4
|
||||
E6C5 652 _GPIFADRL = 0xe6c5
|
||||
E6CE 653 _GPIFTCB3 = 0xe6ce
|
||||
E6CF 654 _GPIFTCB2 = 0xe6cf
|
||||
E6D0 655 _GPIFTCB1 = 0xe6d0
|
||||
E6D1 656 _GPIFTCB0 = 0xe6d1
|
||||
E6D2 657 _EP2GPIFFLGSEL = 0xe6d2
|
||||
E6D3 658 _EP2GPIFPFSTOP = 0xe6d3
|
||||
E6D4 659 _EP2GPIFTRIG = 0xe6d4
|
||||
E6DA 660 _EP4GPIFFLGSEL = 0xe6da
|
||||
E6DB 661 _EP4GPIFPFSTOP = 0xe6db
|
||||
E6DC 662 _EP4GPIFTRIG = 0xe6dc
|
||||
E6E2 663 _EP6GPIFFLGSEL = 0xe6e2
|
||||
E6E3 664 _EP6GPIFPFSTOP = 0xe6e3
|
||||
E6E4 665 _EP6GPIFTRIG = 0xe6e4
|
||||
E6EA 666 _EP8GPIFFLGSEL = 0xe6ea
|
||||
E6EB 667 _EP8GPIFPFSTOP = 0xe6eb
|
||||
E6EC 668 _EP8GPIFTRIG = 0xe6ec
|
||||
E6F0 669 _XGPIFSGLDATH = 0xe6f0
|
||||
E6F1 670 _XGPIFSGLDATLX = 0xe6f1
|
||||
E6F2 671 _XGPIFSGLDATLNOX = 0xe6f2
|
||||
E6F3 672 _GPIFREADYCFG = 0xe6f3
|
||||
E6F4 673 _GPIFREADYSTAT = 0xe6f4
|
||||
E6F5 674 _GPIFABORT = 0xe6f5
|
||||
E6C6 675 _FLOWSTATE = 0xe6c6
|
||||
E6C7 676 _FLOWLOGIC = 0xe6c7
|
||||
E6C8 677 _FLOWEQ0CTL = 0xe6c8
|
||||
E6C9 678 _FLOWEQ1CTL = 0xe6c9
|
||||
E6CA 679 _FLOWHOLDOFF = 0xe6ca
|
||||
E6CB 680 _FLOWSTB = 0xe6cb
|
||||
E6CC 681 _FLOWSTBEDGE = 0xe6cc
|
||||
E6CD 682 _FLOWSTBHPERIOD = 0xe6cd
|
||||
E60C 683 _GPIFHOLDAMOUNT = 0xe60c
|
||||
E67D 684 _UDMACRCH = 0xe67d
|
||||
E67E 685 _UDMACRCL = 0xe67e
|
||||
E67F 686 _UDMACRCQUAL = 0xe67f
|
||||
E6F8 687 _DBUG = 0xe6f8
|
||||
E6F9 688 _TESTCFG = 0xe6f9
|
||||
E6FA 689 _USBTEST = 0xe6fa
|
||||
E6FB 690 _CT1 = 0xe6fb
|
||||
E6FC 691 _CT2 = 0xe6fc
|
||||
E6FD 692 _CT3 = 0xe6fd
|
||||
E6FE 693 _CT4 = 0xe6fe
|
||||
E740 694 _EP0BUF = 0xe740
|
||||
E780 695 _EP1OUTBUF = 0xe780
|
||||
E7C0 696 _EP1INBUF = 0xe7c0
|
||||
F000 697 _EP2FIFOBUF = 0xf000
|
||||
F400 698 _EP4FIFOBUF = 0xf400
|
||||
F800 699 _EP6FIFOBUF = 0xf800
|
||||
FC00 700 _EP8FIFOBUF = 0xfc00
|
||||
701 ;--------------------------------------------------------
|
||||
702 ; absolute external ram data
|
||||
703 ;--------------------------------------------------------
|
||||
704 .area XABS (ABS,XDATA)
|
||||
705 ;--------------------------------------------------------
|
||||
706 ; external initialized ram data
|
||||
707 ;--------------------------------------------------------
|
||||
708 .area HOME (CODE)
|
||||
709 .area GSINIT0 (CODE)
|
||||
710 .area GSINIT1 (CODE)
|
||||
711 .area GSINIT2 (CODE)
|
||||
712 .area GSINIT3 (CODE)
|
||||
713 .area GSINIT4 (CODE)
|
||||
714 .area GSINIT5 (CODE)
|
||||
715 .area GSINIT (CODE)
|
||||
716 .area GSFINAL (CODE)
|
||||
717 .area CSEG (CODE)
|
||||
718 ;--------------------------------------------------------
|
||||
719 ; global & static initialisations
|
||||
720 ;--------------------------------------------------------
|
||||
721 .area HOME (CODE)
|
||||
722 .area GSINIT (CODE)
|
||||
723 .area GSFINAL (CODE)
|
||||
724 .area GSINIT (CODE)
|
||||
725 ;--------------------------------------------------------
|
||||
726 ; Home
|
||||
727 ;--------------------------------------------------------
|
||||
728 .area HOME (CODE)
|
||||
729 .area HOME (CODE)
|
||||
730 ;--------------------------------------------------------
|
||||
731 ; code
|
||||
732 ;--------------------------------------------------------
|
||||
733 .area CSEG (CODE)
|
||||
734 ;------------------------------------------------------------
|
||||
735 ;Allocation info for local variables in function 'fx2_stall_ep0'
|
||||
736 ;------------------------------------------------------------
|
||||
737 ;------------------------------------------------------------
|
||||
738 ; fx2utils.c:28: fx2_stall_ep0 (void)
|
||||
739 ; -----------------------------------------
|
||||
740 ; function fx2_stall_ep0
|
||||
741 ; -----------------------------------------
|
||||
0000 742 _fx2_stall_ep0:
|
||||
0002 743 ar2 = 0x02
|
||||
0003 744 ar3 = 0x03
|
||||
0004 745 ar4 = 0x04
|
||||
0005 746 ar5 = 0x05
|
||||
0006 747 ar6 = 0x06
|
||||
0007 748 ar7 = 0x07
|
||||
0000 749 ar0 = 0x00
|
||||
0001 750 ar1 = 0x01
|
||||
751 ; fx2utils.c:30: EP0CS |= bmEPSTALL;
|
||||
0000 90 E6 A0 752 mov dptr,#_EP0CS
|
||||
0003 E0 753 movx a,@dptr
|
||||
0004 44 01 754 orl a,#0x01
|
||||
0006 F0 755 movx @dptr,a
|
||||
0007 22 756 ret
|
||||
757 ;------------------------------------------------------------
|
||||
758 ;Allocation info for local variables in function 'fx2_reset_data_toggle'
|
||||
759 ;------------------------------------------------------------
|
||||
760 ;ep Allocated to registers r2
|
||||
761 ;------------------------------------------------------------
|
||||
762 ; fx2utils.c:34: fx2_reset_data_toggle (unsigned char ep)
|
||||
763 ; -----------------------------------------
|
||||
764 ; function fx2_reset_data_toggle
|
||||
765 ; -----------------------------------------
|
||||
0008 766 _fx2_reset_data_toggle:
|
||||
0008 AA 82 767 mov r2,dpl
|
||||
768 ; fx2utils.c:36: TOGCTL = ((ep & 0x80) >> 3 | (ep & 0x0f));
|
||||
000A 74 80 769 mov a,#0x80
|
||||
000C 5A 770 anl a,r2
|
||||
000D C4 771 swap a
|
||||
000E 23 772 rl a
|
||||
000F 54 1F 773 anl a,#0x1f
|
||||
0011 FB 774 mov r3,a
|
||||
0012 74 0F 775 mov a,#0x0F
|
||||
0014 5A 776 anl a,r2
|
||||
0015 90 E6 83 777 mov dptr,#_TOGCTL
|
||||
0018 4B 778 orl a,r3
|
||||
0019 F0 779 movx @dptr,a
|
||||
780 ; fx2utils.c:37: TOGCTL |= bmRESETTOGGLE;
|
||||
001A 90 E6 83 781 mov dptr,#_TOGCTL
|
||||
001D E0 782 movx a,@dptr
|
||||
001E 44 20 783 orl a,#0x20
|
||||
0020 F0 784 movx @dptr,a
|
||||
0021 22 785 ret
|
||||
786 ;------------------------------------------------------------
|
||||
787 ;Allocation info for local variables in function 'fx2_renumerate'
|
||||
788 ;------------------------------------------------------------
|
||||
789 ;------------------------------------------------------------
|
||||
790 ; fx2utils.c:41: fx2_renumerate (void)
|
||||
791 ; -----------------------------------------
|
||||
792 ; function fx2_renumerate
|
||||
793 ; -----------------------------------------
|
||||
0022 794 _fx2_renumerate:
|
||||
795 ; fx2utils.c:43: USBCS |= bmDISCON | bmRENUM;
|
||||
0022 90 E6 80 796 mov dptr,#_USBCS
|
||||
0025 E0 797 movx a,@dptr
|
||||
0026 44 0A 798 orl a,#0x0A
|
||||
0028 F0 799 movx @dptr,a
|
||||
800 ; fx2utils.c:45: mdelay (250);
|
||||
0029 90 00 FA 801 mov dptr,#0x00FA
|
||||
002C 12s00r00 802 lcall _mdelay
|
||||
803 ; fx2utils.c:47: USBIRQ = 0xff; // clear any pending USB irqs...
|
||||
002F 90 E6 5D 804 mov dptr,#_USBIRQ
|
||||
0032 74 FF 805 mov a,#0xFF
|
||||
0034 F0 806 movx @dptr,a
|
||||
807 ; fx2utils.c:48: EPIRQ = 0xff; // they're from before the renumeration
|
||||
0035 90 E6 5F 808 mov dptr,#_EPIRQ
|
||||
0038 74 FF 809 mov a,#0xFF
|
||||
003A F0 810 movx @dptr,a
|
||||
811 ; fx2utils.c:50: EXIF &= ~bmEXIF_USBINT;
|
||||
003B 53 91 EF 812 anl _EXIF,#0xEF
|
||||
813 ; fx2utils.c:52: USBCS &= ~bmDISCON; // reconnect USB
|
||||
003E 90 E6 80 814 mov dptr,#_USBCS
|
||||
0041 E0 815 movx a,@dptr
|
||||
0042 54 F7 816 anl a,#0xF7
|
||||
0044 F0 817 movx @dptr,a
|
||||
0045 22 818 ret
|
||||
819 .area CSEG (CODE)
|
||||
820 .area CONST (CODE)
|
||||
821 .area CABS (ABS,CODE)
|
||||
373
firmware/GN3S_v2/lib/fx2utils.rel
Normal file
373
firmware/GN3S_v2/lib/fx2utils.rel
Normal file
@@ -0,0 +1,373 @@
|
||||
XH
|
||||
H 17 areas 146 global symbols
|
||||
M fx2utils
|
||||
O -mmcs51 --model-small
|
||||
S _EP8FIFOCFG DefE61B
|
||||
S _EPIRQ DefE65F
|
||||
S _USBERRIE DefE662
|
||||
S _EP6CS DefE6A5
|
||||
S _GPIFHOLDAMOUNT DefE60C
|
||||
S _SBUF1 Def00C1
|
||||
S _EIEX6 Def00EC
|
||||
S _EP1INBC DefE68F
|
||||
S _EP8FIFOBCL DefE6B2
|
||||
S _DBUG DefE6F8
|
||||
S _B Def00F0
|
||||
S _EXEN2 Def00CB
|
||||
S _EPIE DefE65E
|
||||
S _WAKEUPCS DefE682
|
||||
S _EP1OUTBC DefE68D
|
||||
S _EP8CS DefE6A6
|
||||
S _EP2GPIFTRIG DefE6D4
|
||||
S _SP Def0081
|
||||
S _SCON0 Def0098
|
||||
S _AUTODAT1 Def009C
|
||||
S _EI2C Def00E9
|
||||
S _INT2IVEC DefE666
|
||||
S _AUTODAT2 Def009F
|
||||
S _SCON1 Def00C0
|
||||
S _SMOD1 Def00DF
|
||||
S _MICROFRAME DefE686
|
||||
S _SUDPTRCTL DefE6B5
|
||||
S _EP4GPIFTRIG DefE6DC
|
||||
S _EP2468STAT Def00AA
|
||||
S _OV Def00D2
|
||||
S _INT4IVEC DefE667
|
||||
S _GPIFSGLDATLNOX Def00BF
|
||||
S _T2CON Def00C8
|
||||
S _EP6GPIFTRIG DefE6E4
|
||||
S _ACC Def00E0
|
||||
S _EP2FIFOBUF DefF000
|
||||
S _C_T2 Def00C9
|
||||
S _BREAKPT DefE605
|
||||
S _EP2FIFOPFH DefE630
|
||||
S _EP8GPIFTRIG DefE6EC
|
||||
S _AUTOPTRH2 Def009D
|
||||
S _SETUPDAT DefE6B8
|
||||
S _EP2GPIFFLGSEL DefE6D2
|
||||
S _EP4FIFOBUF DefF400
|
||||
S _EIPX4 Def00FA
|
||||
S _EP4FIFOPFH DefE632
|
||||
S _EP2ISOINPKTS DefE640
|
||||
S _GPIFREADYCFG DefE6F3
|
||||
S _EIPX5 Def00FB
|
||||
S _EP4GPIFFLGSEL DefE6DA
|
||||
S _FLOWSTBHPERIOD DefE6CD
|
||||
S _EP6FIFOBUF DefF800
|
||||
S _EXIF Def0091
|
||||
S _RCLK Def00CD
|
||||
S _EIPX6 Def00FC
|
||||
S _EP2FIFOPFL DefE631
|
||||
S _EP6FIFOPFH DefE634
|
||||
S _EP4ISOINPKTS DefE641
|
||||
S _DPH1 Def0085
|
||||
S _AUTOPTRL2 Def009E
|
||||
S _EP6GPIFFLGSEL DefE6E2
|
||||
S _EP8FIFOBUF DefFC00
|
||||
S _TCLK Def00CC
|
||||
S _PI2C Def00F9
|
||||
S _EP4FIFOPFL DefE633
|
||||
S _EP8FIFOPFH DefE636
|
||||
S _EP6ISOINPKTS DefE642
|
||||
S _FNADDR DefE687
|
||||
S _EP8GPIFFLGSEL DefE6EA
|
||||
S _TESTCFG DefE6F9
|
||||
S _PCON Def0087
|
||||
S _P Def00D0
|
||||
S _GPIF_WAVE_DATA DefE400
|
||||
S _EP6FIFOPFL DefE635
|
||||
S _EP8ISOINPKTS DefE643
|
||||
S _I2CS DefE678
|
||||
S _DPL1 Def0084
|
||||
S _GPIFIRQ DefE661
|
||||
S _EP0BCH DefE68A
|
||||
S _EP01STAT Def00BA
|
||||
S _EP8FIFOPFL DefE637
|
||||
S _EP1INCS DefE6A2
|
||||
S _EIE Def00E8
|
||||
S _RESI Def00DC
|
||||
S _GPIFIE DefE660
|
||||
S _EP2BCH DefE690
|
||||
S _EP1OUTCS DefE6A1
|
||||
S _TCON Def0088
|
||||
S _TMOD Def0089
|
||||
S _OEA Def00B2
|
||||
S _EXF2 Def00CE
|
||||
S _EP0BCL DefE68B
|
||||
S _EP4BCH DefE694
|
||||
S _OEB Def00B3
|
||||
S _REN1 Def00C4
|
||||
S _EP2CFG DefE612
|
||||
S _EP2FIFOIRQ DefE651
|
||||
S _GPIFREADYSTAT DefE6F4
|
||||
S _OEC Def00B4
|
||||
S _EP2BCL DefE691
|
||||
S _EP6BCH DefE698
|
||||
S _OED Def00B5
|
||||
S _EP4CFG DefE613
|
||||
S _EP2FIFOIE DefE650
|
||||
S _EP4FIFOIRQ DefE653
|
||||
S _IOA Def0080
|
||||
S _OEE Def00B6
|
||||
S _EP4BCL DefE695
|
||||
S _EP8BCH DefE69C
|
||||
S _IOB Def0090
|
||||
S _PUSB Def00F8
|
||||
S _EP6CFG DefE614
|
||||
S _EP4FIFOIE DefE652
|
||||
S _EP6FIFOIRQ DefE655
|
||||
S _IOC Def00A0
|
||||
S _mdelay Ref0000
|
||||
S _INTSETUP DefE668
|
||||
S _EP6BCL DefE699
|
||||
S _DPH Def0083
|
||||
S _IOD Def00B0
|
||||
S _EP8CFG DefE615
|
||||
S _EP6FIFOIE DefE654
|
||||
S _EP8FIFOIRQ DefE657
|
||||
S _USBFRAMEH DefE684
|
||||
S _IOE Def00B1
|
||||
S _RB81 Def00C2
|
||||
S _EP2AUTOINLENH DefE620
|
||||
S _EP8BCL DefE69D
|
||||
S _GPIFABORT DefE6F5
|
||||
S _INT2CLR Def00A1
|
||||
S _EIP Def00F8
|
||||
S _IE0 Def0089
|
||||
S _EP8FIFOIE DefE656
|
||||
S _IE1 Def008B
|
||||
S _TB81 Def00C3
|
||||
S _EP4AUTOINLENH DefE622
|
||||
S _DPL Def0082
|
||||
S _INT4CLR Def00A2
|
||||
S _AUTOPTRSETUP Def00AF
|
||||
S _RCAP2H Def00CB
|
||||
S _USBFRAMEL DefE685
|
||||
S _XGPIFSGLDATLX DefE6F1
|
||||
S _FLOWEQ0CTL DefE6C8
|
||||
S _FLOWSTB DefE6CB
|
||||
S _SM01 Def00C7
|
||||
S _INT6 Def00DB
|
||||
S _EP2AUTOINLENL DefE621
|
||||
S _EP6AUTOINLENH DefE624
|
||||
S _SUSPEND DefE681
|
||||
S _FLOWEQ1CTL DefE6C9
|
||||
S _EP0BUF DefE740
|
||||
S _SM11 Def00C6
|
||||
S _CP_RL2 Def00C8
|
||||
S _GPIFWFSELECT DefE6C0
|
||||
S _SM21 Def00C5
|
||||
S _EP4AUTOINLENL DefE623
|
||||
S _EP8AUTOINLENH DefE626
|
||||
S _RCAP2L Def00CA
|
||||
S _SEL Def0086
|
||||
S _AC Def00D6
|
||||
S _IFCONFIG DefE601
|
||||
S _IBNIRQ DefE659
|
||||
S _GPIFADRH DefE6C4
|
||||
S _XGPIFSGLDATH DefE6F0
|
||||
S _REN Def009C
|
||||
S _EP6AUTOINLENL DefE625
|
||||
S _NAKIRQ DefE65B
|
||||
S _FLOWLOGIC DefE6C7
|
||||
S _EA Def00AF
|
||||
S _FIFORESET DefE604
|
||||
S _IBNIE DefE658
|
||||
S _GPIFIDLECTL DefE6C2
|
||||
S _UDMACRCH DefE67D
|
||||
S _DPS Def0086
|
||||
S _EP8AUTOINLENL DefE627
|
||||
S _NAKIE DefE65A
|
||||
S _CT1 DefE6FB
|
||||
S _ES0 Def00AC
|
||||
S _FIFOPINPOLAR DefE609
|
||||
S _GPIFADRL DefE6C5
|
||||
S _EP2GPIFPFSTOP DefE6D3
|
||||
S _CT2 DefE6FC
|
||||
S _GPIFSGLDATLX Def00BE
|
||||
S _ET0 Def00A9
|
||||
S _ES1 Def00AE
|
||||
S _SUDPTRH DefE6B3
|
||||
S _USBTEST DefE6FA
|
||||
S _CT3 DefE6FD
|
||||
S _MPAGE Def0092
|
||||
S _TF0 Def008D
|
||||
S _ET1 Def00AB
|
||||
S _EP4GPIFPFSTOP DefE6DB
|
||||
S _UDMACRCL DefE67E
|
||||
S _CT4 DefE6FE
|
||||
S _EP24FIFOFLGS Def00AB
|
||||
S _TF1 Def008F
|
||||
S _ET2 Def00AD
|
||||
S _RES_WAVEDATA_END DefE480
|
||||
S _TH0 Def008C
|
||||
S _RB8 Def009A
|
||||
S _RI1 Def00C0
|
||||
S _TF2 Def00CF
|
||||
S _EP1INCFG DefE611
|
||||
S _TOGCTL DefE683
|
||||
S _EP6GPIFPFSTOP DefE6E3
|
||||
S _TH1 Def008D
|
||||
S _GPIFSGLDATH Def00BD
|
||||
S _IT0 Def0088
|
||||
S _EX0 Def00A8
|
||||
S _EP1OUTCFG DefE610
|
||||
S _SUDPTRL DefE6B4
|
||||
S _CKCON Def008E
|
||||
S _IE Def00A8
|
||||
S _TH2 Def00CD
|
||||
S _EICON Def00D8
|
||||
S _IT1 Def008A
|
||||
S _TB8 Def009B
|
||||
S _EX1 Def00AA
|
||||
S _TI1 Def00C1
|
||||
S _CLRERRCNT DefE665
|
||||
S _GPIFTCB0 DefE6D1
|
||||
S _EP8GPIFPFSTOP DefE6EB
|
||||
S _REVCTL DefE60B
|
||||
S _ERRCNTLIM DefE664
|
||||
S _GPIFTCB1 DefE6D0
|
||||
S _TL0 Def008A
|
||||
S _APTR1H Def009A
|
||||
S _SM0 Def009F
|
||||
S _UART230 DefE608
|
||||
S _GPIFTCB2 DefE6CF
|
||||
S _TL1 Def008B
|
||||
S _A0 Def0080
|
||||
S _SM1 Def009E
|
||||
S _GPIFTCB3 DefE6CE
|
||||
S _UDMACRCQUAL DefE67F
|
||||
S _TL2 Def00CC
|
||||
S _A1 Def0081
|
||||
S _SM2 Def009D
|
||||
S _FL Def00D1
|
||||
S _EP68FIFOFLGS Def00AC
|
||||
S _A2 Def0082
|
||||
S _PS0 Def00BC
|
||||
S _I2DAT DefE679
|
||||
S _APTR1L Def009B
|
||||
S _A3 Def0083
|
||||
S _D0 Def00B0
|
||||
S _PT0 Def00B9
|
||||
S _PS1 Def00BE
|
||||
S _BPADDRH DefE606
|
||||
S _A4 Def0084
|
||||
S _D1 Def00B1
|
||||
S _PT1 Def00BB
|
||||
S _RS0 Def00D3
|
||||
S _USBIRQ DefE65D
|
||||
S _PORTACFG DefE670
|
||||
S _FLOWSTBEDGE DefE6CC
|
||||
S _A5 Def0085
|
||||
S _TR0 Def008C
|
||||
S _D2 Def00B2
|
||||
S _PT2 Def00BD
|
||||
S _RS1 Def00D4
|
||||
S _F0 Def00D5
|
||||
S _PINFLAGSAB DefE602
|
||||
S _EP2FIFOFLGS DefE6A7
|
||||
S _A6 Def0086
|
||||
S _TR1 Def008E
|
||||
S _D3 Def00B3
|
||||
S _USBIE DefE65C
|
||||
S _PORTCCFG DefE671
|
||||
S _EP2FIFOBCH DefE6AB
|
||||
S _A7 Def0087
|
||||
S _D4 Def00B4
|
||||
S _PX0 Def00B8
|
||||
S _TR2 Def00CA
|
||||
S _ERESI Def00DD
|
||||
S _EIUSB Def00E8
|
||||
S _BPADDRL DefE607
|
||||
S _EP4FIFOFLGS DefE6A8
|
||||
S _GPIFCTLCFG DefE6C3
|
||||
S _FLOWSTATE DefE6C6
|
||||
S _IP Def00B8
|
||||
S _D5 Def00B5
|
||||
S _PX1 Def00BA
|
||||
S _REVID DefE60A
|
||||
S _PORTECFG DefE672
|
||||
S _EP4FIFOBCH DefE6AD
|
||||
S _GPIFIDLECS DefE6C1
|
||||
S _FLOWHOLDOFF DefE6CA
|
||||
S _EP1INBUF DefE7C0
|
||||
S _PSW Def00D0
|
||||
S _D6 Def00B6
|
||||
S _PINFLAGSCD DefE603
|
||||
S _EP2FIFOCFG DefE618
|
||||
S _XAUTODAT1 DefE67B
|
||||
S _EP0CS DefE6A0
|
||||
S _EP6FIFOFLGS DefE6A9
|
||||
S _EP1OUTBUF DefE780
|
||||
S _RI Def0098
|
||||
S _D7 Def00B7
|
||||
S _XAUTODAT2 DefE67C
|
||||
S _EP2FIFOBCL DefE6AC
|
||||
S _EP6FIFOBCH DefE6AF
|
||||
S _GPIFTRIG Def00BB
|
||||
S _CY Def00D7
|
||||
S _EP4FIFOCFG DefE619
|
||||
S _INPKTEND DefE648
|
||||
S _EP2CS DefE6A3
|
||||
S _EP8FIFOFLGS DefE6AA
|
||||
S _TI Def0099
|
||||
S _CPUCS DefE600
|
||||
S _OUTPKTEND DefE649
|
||||
S _I2CTL DefE67A
|
||||
S _EP4FIFOBCL DefE6AE
|
||||
S _EP8FIFOBCH DefE6B1
|
||||
S _XGPIFSGLDATLNOX DefE6F2
|
||||
S _EP6FIFOCFG DefE61A
|
||||
S _USBERRIRQ DefE663
|
||||
S _EP4CS DefE6A4
|
||||
S _EIEX4 Def00EA
|
||||
S _USBCS DefE680
|
||||
S _EP6FIFOBCL DefE6B0
|
||||
S _SBUF0 Def0099
|
||||
S _EIEX5 Def00EB
|
||||
A _CODE size 0 flags 0 addr 0
|
||||
A RSEG size 0 flags 0 addr 0
|
||||
A REG_BANK_0 size 8 flags 4 addr 0
|
||||
A DSEG size 0 flags 0 addr 0
|
||||
A OSEG size 0 flags 4 addr 0
|
||||
A ISEG size 0 flags 0 addr 0
|
||||
A IABS size 0 flags 8 addr 0
|
||||
A BSEG size 0 flags 80 addr 0
|
||||
A PSEG size 0 flags 50 addr 0
|
||||
A XSEG size 0 flags 40 addr 0
|
||||
A XABS size 0 flags 48 addr 0
|
||||
A HOME size 0 flags 20 addr 0
|
||||
A GSINIT0 size 0 flags 20 addr 0
|
||||
A GSINIT1 size 0 flags 20 addr 0
|
||||
A GSINIT2 size 0 flags 20 addr 0
|
||||
A GSINIT3 size 0 flags 20 addr 0
|
||||
A GSINIT4 size 0 flags 20 addr 0
|
||||
A GSINIT5 size 0 flags 20 addr 0
|
||||
A GSINIT size 0 flags 20 addr 0
|
||||
A GSFINAL size 0 flags 20 addr 0
|
||||
A CSEG size 46 flags 20 addr 0
|
||||
S _fx2_renumerate Def0022
|
||||
S _fx2_reset_data_toggle Def0008
|
||||
S _fx2_stall_ep0 Def0000
|
||||
A CONST size 0 flags 20 addr 0
|
||||
A CABS size 0 flags 28 addr 0
|
||||
T 00 00
|
||||
R 00 00 00 02
|
||||
T 00 00
|
||||
R 00 00 00 14
|
||||
T 00 00 90 E6 A0 E0 44 01 F0 22
|
||||
R 00 00 00 14
|
||||
T 00 08
|
||||
R 00 00 00 14
|
||||
T 00 08 AA 82 74 80 5A C4 23 54 1F FB 74 0F 5A 90
|
||||
R 00 00 00 14
|
||||
T 00 16 E6 83 4B F0 90 E6 83 E0 44 20 F0 22
|
||||
R 00 00 00 14
|
||||
T 00 22
|
||||
R 00 00 00 14
|
||||
T 00 22 90 E6 80 E0 44 0A F0 90 00 FA 12 00 00 90
|
||||
R 00 00 00 14 02 0D 00 73
|
||||
T 00 30 E6 5D 74 FF F0 90 E6 5F 74 FF F0 53 91 EF
|
||||
R 00 00 00 14
|
||||
T 00 3E 90 E6 80 E0 54 F7 F0 22
|
||||
R 00 00 00 14
|
||||
702
firmware/GN3S_v2/lib/fx2utils.sym
Normal file
702
firmware/GN3S_v2/lib/fx2utils.sym
Normal file
@@ -0,0 +1,702 @@
|
||||
ASxxxx Assembler V01.70 + NoICE + SDCC mods + Flat24 Feb-1999 (Intel 8051), page 1.
|
||||
|
||||
Symbol Table
|
||||
|
||||
A 00D6
|
||||
AC 00D6
|
||||
ACC 00E0
|
||||
ACC.0 00E0
|
||||
ACC.1 00E1
|
||||
ACC.2 00E2
|
||||
ACC.3 00E3
|
||||
ACC.4 00E4
|
||||
ACC.5 00E5
|
||||
ACC.6 00E6
|
||||
ACC.7 00E7
|
||||
B 00F0
|
||||
B.0 00F0
|
||||
B.1 00F1
|
||||
B.2 00F2
|
||||
B.3 00F3
|
||||
B.4 00F4
|
||||
B.5 00F5
|
||||
B.6 00F6
|
||||
B.7 00F7
|
||||
CPRL2 00C8
|
||||
CT2 00C9
|
||||
CY 00D7
|
||||
DPH 0083
|
||||
DPL 0082
|
||||
EA 00AF
|
||||
ES 00AC
|
||||
ET0 00A9
|
||||
ET1 00AB
|
||||
ET2 00AD
|
||||
EX0 00A8
|
||||
EX1 00AA
|
||||
EXEN2 00CB
|
||||
EXF2 00CE
|
||||
F0 00D5
|
||||
IE 00A8
|
||||
IE.0 00A8
|
||||
IE.1 00A9
|
||||
IE.2 00AA
|
||||
IE.3 00AB
|
||||
IE.4 00AC
|
||||
IE.5 00AD
|
||||
IE.7 00AF
|
||||
IE0 0089
|
||||
IE1 008B
|
||||
INT0 00B2
|
||||
INT1 00B3
|
||||
IP 00B8
|
||||
IP.0 00B8
|
||||
IP.1 00B9
|
||||
IP.2 00BA
|
||||
IP.3 00BB
|
||||
IP.4 00BC
|
||||
IP.5 00BD
|
||||
IT0 0088
|
||||
IT1 008A
|
||||
OV 00D2
|
||||
P 00D0
|
||||
P0 0080
|
||||
P0.0 0080
|
||||
P0.1 0081
|
||||
P0.2 0082
|
||||
P0.3 0083
|
||||
P0.4 0084
|
||||
P0.5 0085
|
||||
P0.6 0086
|
||||
P0.7 0087
|
||||
P1 0090
|
||||
P1.0 0090
|
||||
P1.1 0091
|
||||
P1.2 0092
|
||||
P1.3 0093
|
||||
P1.4 0094
|
||||
P1.5 0095
|
||||
P1.6 0096
|
||||
P1.7 0097
|
||||
P2 00A0
|
||||
P2.0 00A0
|
||||
P2.1 00A1
|
||||
P2.2 00A2
|
||||
P2.3 00A3
|
||||
P2.4 00A4
|
||||
P2.5 00A5
|
||||
P2.6 00A6
|
||||
P2.7 00A7
|
||||
P3 00B0
|
||||
P3.0 00B0
|
||||
P3.1 00B1
|
||||
P3.2 00B2
|
||||
P3.3 00B3
|
||||
P3.4 00B4
|
||||
P3.5 00B5
|
||||
P3.6 00B6
|
||||
P3.7 00B7
|
||||
PCON 0087
|
||||
PS 00BC
|
||||
PSW 00D0
|
||||
PSW.0 00D0
|
||||
PSW.1 00D1
|
||||
PSW.2 00D2
|
||||
PSW.3 00D3
|
||||
PSW.4 00D4
|
||||
PSW.5 00D5
|
||||
PSW.6 00D6
|
||||
PSW.7 00D7
|
||||
PT0 00B9
|
||||
PT1 00BB
|
||||
PT2 00BD
|
||||
PX0 00B8
|
||||
PX1 00BA
|
||||
RB8 009A
|
||||
RCAP2H 00CB
|
||||
RCAP2L 00CA
|
||||
RCLK 00CD
|
||||
REN 009C
|
||||
RI 0098
|
||||
RS0 00D3
|
||||
RS1 00D4
|
||||
RXD 00B0
|
||||
SBUF 0099
|
||||
SCON 0098
|
||||
SCON.0 0098
|
||||
SCON.1 0099
|
||||
SCON.2 009A
|
||||
SCON.3 009B
|
||||
SCON.4 009C
|
||||
SCON.5 009D
|
||||
SCON.6 009E
|
||||
SCON.7 009F
|
||||
SM0 009F
|
||||
SM1 009E
|
||||
SM2 009D
|
||||
SP 0081
|
||||
T2CON 00C8
|
||||
T2CON.0 00C8
|
||||
T2CON.1 00C9
|
||||
T2CON.2 00CA
|
||||
T2CON.3 00CB
|
||||
T2CON.4 00CC
|
||||
T2CON.5 00CD
|
||||
T2CON.6 00CE
|
||||
T2CON.7 00CF
|
||||
TB8 009B
|
||||
TCLK 00CC
|
||||
TCON 0088
|
||||
TCON.0 0088
|
||||
TCON.1 0089
|
||||
TCON.2 008A
|
||||
TCON.3 008B
|
||||
TCON.4 008C
|
||||
TCON.5 008D
|
||||
TCON.6 008E
|
||||
TCON.7 008F
|
||||
TF0 008D
|
||||
TF1 008F
|
||||
TF2 00CF
|
||||
TH0 008C
|
||||
TH1 008D
|
||||
TH2 00CD
|
||||
TI 0099
|
||||
TL0 008A
|
||||
TL1 008B
|
||||
TL2 00CC
|
||||
TMOD 0089
|
||||
TR0 008C
|
||||
TR1 008E
|
||||
TR2 00CA
|
||||
TXD 00B1
|
||||
_A0 = 0080 G
|
||||
_A1 = 0081 G
|
||||
_A2 = 0082 G
|
||||
_A3 = 0083 G
|
||||
_A4 = 0084 G
|
||||
_A5 = 0085 G
|
||||
_A6 = 0086 G
|
||||
_A7 = 0087 G
|
||||
_AC = 00D6 G
|
||||
_ACC = 00E0 G
|
||||
_APTR1H = 009A G
|
||||
_APTR1L = 009B G
|
||||
_AUTODAT1 = 009C G
|
||||
_AUTODAT2 = 009F G
|
||||
_AUTOPTRH2 = 009D G
|
||||
_AUTOPTRL2 = 009E G
|
||||
_AUTOPTRSETUP = 00AF G
|
||||
_B = 00F0 G
|
||||
_BPADDRH = E606 G
|
||||
_BPADDRL = E607 G
|
||||
_BREAKPT = E605 G
|
||||
_CKCON = 008E G
|
||||
_CLRERRCNT = E665 G
|
||||
_CPUCS = E600 G
|
||||
_CP_RL2 = 00C8 G
|
||||
_CT1 = E6FB G
|
||||
_CT2 = E6FC G
|
||||
_CT3 = E6FD G
|
||||
_CT4 = E6FE G
|
||||
_CY = 00D7 G
|
||||
_C_T2 = 00C9 G
|
||||
_D0 = 00B0 G
|
||||
_D1 = 00B1 G
|
||||
_D2 = 00B2 G
|
||||
_D3 = 00B3 G
|
||||
_D4 = 00B4 G
|
||||
_D5 = 00B5 G
|
||||
_D6 = 00B6 G
|
||||
_D7 = 00B7 G
|
||||
_DBUG = E6F8 G
|
||||
_DPH = 0083 G
|
||||
_DPH1 = 0085 G
|
||||
_DPL = 0082 G
|
||||
_DPL1 = 0084 G
|
||||
_DPS = 0086 G
|
||||
_EA = 00AF G
|
||||
_EI2C = 00E9 G
|
||||
_EICON = 00D8 G
|
||||
_EIE = 00E8 G
|
||||
_EIEX4 = 00EA G
|
||||
_EIEX5 = 00EB G
|
||||
_EIEX6 = 00EC G
|
||||
_EIP = 00F8 G
|
||||
_EIPX4 = 00FA G
|
||||
_EIPX5 = 00FB G
|
||||
_EIPX6 = 00FC G
|
||||
_EIUSB = 00E8 G
|
||||
_EP01STAT = 00BA G
|
||||
_EP0BCH = E68A G
|
||||
_EP0BCL = E68B G
|
||||
_EP0BUF = E740 G
|
||||
_EP0CS = E6A0 G
|
||||
_EP1INBC = E68F G
|
||||
_EP1INBUF = E7C0 G
|
||||
_EP1INCFG = E611 G
|
||||
_EP1INCS = E6A2 G
|
||||
_EP1OUTBC = E68D G
|
||||
_EP1OUTBUF = E780 G
|
||||
_EP1OUTCFG = E610 G
|
||||
_EP1OUTCS = E6A1 G
|
||||
_EP2468STAT = 00AA G
|
||||
_EP24FIFOFLGS = 00AB G
|
||||
_EP2AUTOINLENH = E620 G
|
||||
_EP2AUTOINLENL = E621 G
|
||||
_EP2BCH = E690 G
|
||||
_EP2BCL = E691 G
|
||||
_EP2CFG = E612 G
|
||||
_EP2CS = E6A3 G
|
||||
_EP2FIFOBCH = E6AB G
|
||||
_EP2FIFOBCL = E6AC G
|
||||
_EP2FIFOBUF = F000 G
|
||||
_EP2FIFOCFG = E618 G
|
||||
_EP2FIFOFLGS = E6A7 G
|
||||
_EP2FIFOIE = E650 G
|
||||
_EP2FIFOIRQ = E651 G
|
||||
_EP2FIFOPFH = E630 G
|
||||
_EP2FIFOPFL = E631 G
|
||||
_EP2GPIFFLGSEL = E6D2 G
|
||||
_EP2GPIFPFSTOP = E6D3 G
|
||||
_EP2GPIFTRIG = E6D4 G
|
||||
_EP2ISOINPKTS = E640 G
|
||||
_EP4AUTOINLENH = E622 G
|
||||
_EP4AUTOINLENL = E623 G
|
||||
_EP4BCH = E694 G
|
||||
_EP4BCL = E695 G
|
||||
_EP4CFG = E613 G
|
||||
_EP4CS = E6A4 G
|
||||
_EP4FIFOBCH = E6AD G
|
||||
_EP4FIFOBCL = E6AE G
|
||||
_EP4FIFOBUF = F400 G
|
||||
_EP4FIFOCFG = E619 G
|
||||
_EP4FIFOFLGS = E6A8 G
|
||||
_EP4FIFOIE = E652 G
|
||||
_EP4FIFOIRQ = E653 G
|
||||
_EP4FIFOPFH = E632 G
|
||||
_EP4FIFOPFL = E633 G
|
||||
_EP4GPIFFLGSEL = E6DA G
|
||||
_EP4GPIFPFSTOP = E6DB G
|
||||
_EP4GPIFTRIG = E6DC G
|
||||
_EP4ISOINPKTS = E641 G
|
||||
_EP68FIFOFLGS = 00AC G
|
||||
_EP6AUTOINLENH = E624 G
|
||||
_EP6AUTOINLENL = E625 G
|
||||
_EP6BCH = E698 G
|
||||
_EP6BCL = E699 G
|
||||
_EP6CFG = E614 G
|
||||
_EP6CS = E6A5 G
|
||||
_EP6FIFOBCH = E6AF G
|
||||
_EP6FIFOBCL = E6B0 G
|
||||
_EP6FIFOBUF = F800 G
|
||||
_EP6FIFOCFG = E61A G
|
||||
_EP6FIFOFLGS = E6A9 G
|
||||
_EP6FIFOIE = E654 G
|
||||
_EP6FIFOIRQ = E655 G
|
||||
_EP6FIFOPFH = E634 G
|
||||
_EP6FIFOPFL = E635 G
|
||||
_EP6GPIFFLGSEL = E6E2 G
|
||||
_EP6GPIFPFSTOP = E6E3 G
|
||||
_EP6GPIFTRIG = E6E4 G
|
||||
_EP6ISOINPKTS = E642 G
|
||||
_EP8AUTOINLENH = E626 G
|
||||
_EP8AUTOINLENL = E627 G
|
||||
_EP8BCH = E69C G
|
||||
_EP8BCL = E69D G
|
||||
_EP8CFG = E615 G
|
||||
_EP8CS = E6A6 G
|
||||
_EP8FIFOBCH = E6B1 G
|
||||
_EP8FIFOBCL = E6B2 G
|
||||
_EP8FIFOBUF = FC00 G
|
||||
_EP8FIFOCFG = E61B G
|
||||
_EP8FIFOFLGS = E6AA G
|
||||
_EP8FIFOIE = E656 G
|
||||
_EP8FIFOIRQ = E657 G
|
||||
_EP8FIFOPFH = E636 G
|
||||
_EP8FIFOPFL = E637 G
|
||||
_EP8GPIFFLGSEL = E6EA G
|
||||
_EP8GPIFPFSTOP = E6EB G
|
||||
_EP8GPIFTRIG = E6EC G
|
||||
_EP8ISOINPKTS = E643 G
|
||||
_EPIE = E65E G
|
||||
_EPIRQ = E65F G
|
||||
_ERESI = 00DD G
|
||||
_ERRCNTLIM = E664 G
|
||||
_ES0 = 00AC G
|
||||
_ES1 = 00AE G
|
||||
_ET0 = 00A9 G
|
||||
_ET1 = 00AB G
|
||||
_ET2 = 00AD G
|
||||
_EX0 = 00A8 G
|
||||
_EX1 = 00AA G
|
||||
_EXEN2 = 00CB G
|
||||
_EXF2 = 00CE G
|
||||
_EXIF = 0091 G
|
||||
_F0 = 00D5 G
|
||||
_FIFOPINPOLAR = E609 G
|
||||
_FIFORESET = E604 G
|
||||
_FL = 00D1 G
|
||||
_FLOWEQ0CTL = E6C8 G
|
||||
_FLOWEQ1CTL = E6C9 G
|
||||
_FLOWHOLDOFF = E6CA G
|
||||
_FLOWLOGIC = E6C7 G
|
||||
_FLOWSTATE = E6C6 G
|
||||
_FLOWSTB = E6CB G
|
||||
_FLOWSTBEDGE = E6CC G
|
||||
_FLOWSTBHPERIOD = E6CD G
|
||||
_FNADDR = E687 G
|
||||
_GPIFABORT = E6F5 G
|
||||
_GPIFADRH = E6C4 G
|
||||
_GPIFADRL = E6C5 G
|
||||
_GPIFCTLCFG = E6C3 G
|
||||
_GPIFHOLDAMOUNT = E60C G
|
||||
_GPIFIDLECS = E6C1 G
|
||||
_GPIFIDLECTL = E6C2 G
|
||||
_GPIFIE = E660 G
|
||||
_GPIFIRQ = E661 G
|
||||
_GPIFREADYCFG = E6F3 G
|
||||
_GPIFREADYSTAT = E6F4 G
|
||||
_GPIFSGLDATH = 00BD G
|
||||
_GPIFSGLDATLNOX = 00BF G
|
||||
_GPIFSGLDATLX = 00BE G
|
||||
_GPIFTCB0 = E6D1 G
|
||||
_GPIFTCB1 = E6D0 G
|
||||
_GPIFTCB2 = E6CF G
|
||||
_GPIFTCB3 = E6CE G
|
||||
_GPIFTRIG = 00BB G
|
||||
_GPIFWFSELECT = E6C0 G
|
||||
_GPIF_WAVE_DATA = E400 G
|
||||
_I2CS = E678 G
|
||||
_I2CTL = E67A G
|
||||
_I2DAT = E679 G
|
||||
_IBNIE = E658 G
|
||||
_IBNIRQ = E659 G
|
||||
_IE = 00A8 G
|
||||
_IE0 = 0089 G
|
||||
_IE1 = 008B G
|
||||
_IFCONFIG = E601 G
|
||||
_INPKTEND = E648 G
|
||||
_INT2CLR = 00A1 G
|
||||
_INT2IVEC = E666 G
|
||||
_INT4CLR = 00A2 G
|
||||
_INT4IVEC = E667 G
|
||||
_INT6 = 00DB G
|
||||
_INTSETUP = E668 G
|
||||
_IOA = 0080 G
|
||||
_IOB = 0090 G
|
||||
_IOC = 00A0 G
|
||||
_IOD = 00B0 G
|
||||
_IOE = 00B1 G
|
||||
_IP = 00B8 G
|
||||
_IT0 = 0088 G
|
||||
_IT1 = 008A G
|
||||
_MICROFRAME = E686 G
|
||||
_MPAGE = 0092 G
|
||||
_NAKIE = E65A G
|
||||
_NAKIRQ = E65B G
|
||||
_OEA = 00B2 G
|
||||
_OEB = 00B3 G
|
||||
_OEC = 00B4 G
|
||||
_OED = 00B5 G
|
||||
_OEE = 00B6 G
|
||||
_OUTPKTEND = E649 G
|
||||
_OV = 00D2 G
|
||||
_P = 00D0 G
|
||||
_PCON = 0087 G
|
||||
_PI2C = 00F9 G
|
||||
_PINFLAGSAB = E602 G
|
||||
_PINFLAGSCD = E603 G
|
||||
_PORTACFG = E670 G
|
||||
_PORTCCFG = E671 G
|
||||
_PORTECFG = E672 G
|
||||
_PS0 = 00BC G
|
||||
_PS1 = 00BE G
|
||||
_PSW = 00D0 G
|
||||
_PT0 = 00B9 G
|
||||
_PT1 = 00BB G
|
||||
_PT2 = 00BD G
|
||||
_PUSB = 00F8 G
|
||||
_PX0 = 00B8 G
|
||||
_PX1 = 00BA G
|
||||
_RB8 = 009A G
|
||||
_RB81 = 00C2 G
|
||||
_RCAP2H = 00CB G
|
||||
_RCAP2L = 00CA G
|
||||
_RCLK = 00CD G
|
||||
_REN = 009C G
|
||||
_REN1 = 00C4 G
|
||||
_RESI = 00DC G
|
||||
_RES_WAVEDATA_END = E480 G
|
||||
_REVCTL = E60B G
|
||||
_REVID = E60A G
|
||||
_RI = 0098 G
|
||||
_RI1 = 00C0 G
|
||||
_RS0 = 00D3 G
|
||||
_RS1 = 00D4 G
|
||||
_SBUF0 = 0099 G
|
||||
_SBUF1 = 00C1 G
|
||||
_SCON0 = 0098 G
|
||||
_SCON1 = 00C0 G
|
||||
_SEL = 0086 G
|
||||
_SETUPDAT = E6B8 G
|
||||
_SM0 = 009F G
|
||||
_SM01 = 00C7 G
|
||||
_SM1 = 009E G
|
||||
_SM11 = 00C6 G
|
||||
_SM2 = 009D G
|
||||
_SM21 = 00C5 G
|
||||
_SMOD1 = 00DF G
|
||||
_SP = 0081 G
|
||||
_SUDPTRCTL = E6B5 G
|
||||
_SUDPTRH = E6B3 G
|
||||
_SUDPTRL = E6B4 G
|
||||
_SUSPEND = E681 G
|
||||
_T2CON = 00C8 G
|
||||
_TB8 = 009B G
|
||||
_TB81 = 00C3 G
|
||||
_TCLK = 00CC G
|
||||
_TCON = 0088 G
|
||||
_TESTCFG = E6F9 G
|
||||
_TF0 = 008D G
|
||||
_TF1 = 008F G
|
||||
_TF2 = 00CF G
|
||||
_TH0 = 008C G
|
||||
_TH1 = 008D G
|
||||
_TH2 = 00CD G
|
||||
_TI = 0099 G
|
||||
_TI1 = 00C1 G
|
||||
_TL0 = 008A G
|
||||
_TL1 = 008B G
|
||||
_TL2 = 00CC G
|
||||
_TMOD = 0089 G
|
||||
_TOGCTL = E683 G
|
||||
_TR0 = 008C G
|
||||
_TR1 = 008E G
|
||||
_TR2 = 00CA G
|
||||
_UART230 = E608 G
|
||||
_UDMACRCH = E67D G
|
||||
_UDMACRCL = E67E G
|
||||
_UDMACRCQUAL = E67F G
|
||||
_USBCS = E680 G
|
||||
_USBERRIE = E662 G
|
||||
_USBERRIRQ = E663 G
|
||||
_USBFRAMEH = E684 G
|
||||
_USBFRAMEL = E685 G
|
||||
_USBIE = E65C G
|
||||
_USBIRQ = E65D G
|
||||
_USBTEST = E6FA G
|
||||
_WAKEUPCS = E682 G
|
||||
_XAUTODAT1 = E67B G
|
||||
_XAUTODAT2 = E67C G
|
||||
_XGPIFSGLDATH = E6F0 G
|
||||
_XGPIFSGLDATLNOX = E6F2 G
|
||||
_XGPIFSGLDATLX = E6F1 G
|
||||
14 _fx2_renumerate 0022 GR
|
||||
14 _fx2_reset_data_toggle 0008 GR
|
||||
14 _fx2_stall_ep0 0000 GR
|
||||
_mdelay **** GX
|
||||
a 00D6
|
||||
ac 00D6
|
||||
acc 00E0
|
||||
acc.0 00E0
|
||||
acc.1 00E1
|
||||
acc.2 00E2
|
||||
acc.3 00E3
|
||||
acc.4 00E4
|
||||
acc.5 00E5
|
||||
acc.6 00E6
|
||||
acc.7 00E7
|
||||
ar0 = 0000
|
||||
ar1 = 0001
|
||||
ar2 = 0002
|
||||
ar3 = 0003
|
||||
ar4 = 0004
|
||||
ar5 = 0005
|
||||
ar6 = 0006
|
||||
ar7 = 0007
|
||||
b 00F0
|
||||
b.0 00F0
|
||||
b.1 00F1
|
||||
b.2 00F2
|
||||
b.3 00F3
|
||||
b.4 00F4
|
||||
b.5 00F5
|
||||
b.6 00F6
|
||||
b.7 00F7
|
||||
cprl2 00C8
|
||||
ct2 00C9
|
||||
cy 00D7
|
||||
dph 0083
|
||||
dpl 0082
|
||||
ea 00AF
|
||||
es 00AC
|
||||
et0 00A9
|
||||
et1 00AB
|
||||
et2 00AD
|
||||
ex0 00A8
|
||||
ex1 00AA
|
||||
exen2 00CB
|
||||
exf2 00CE
|
||||
f0 00D5
|
||||
ie 00A8
|
||||
ie.0 00A8
|
||||
ie.1 00A9
|
||||
ie.2 00AA
|
||||
ie.3 00AB
|
||||
ie.4 00AC
|
||||
ie.5 00AD
|
||||
ie.7 00AF
|
||||
ie0 0089
|
||||
ie1 008B
|
||||
int0 00B2
|
||||
int1 00B3
|
||||
ip 00B8
|
||||
ip.0 00B8
|
||||
ip.1 00B9
|
||||
ip.2 00BA
|
||||
ip.3 00BB
|
||||
ip.4 00BC
|
||||
ip.5 00BD
|
||||
it0 0088
|
||||
it1 008A
|
||||
ov 00D2
|
||||
p 00D0
|
||||
p0 0080
|
||||
p0.0 0080
|
||||
p0.1 0081
|
||||
p0.2 0082
|
||||
p0.3 0083
|
||||
p0.4 0084
|
||||
p0.5 0085
|
||||
p0.6 0086
|
||||
p0.7 0087
|
||||
p1 0090
|
||||
p1.0 0090
|
||||
p1.1 0091
|
||||
p1.2 0092
|
||||
p1.3 0093
|
||||
p1.4 0094
|
||||
p1.5 0095
|
||||
p1.6 0096
|
||||
p1.7 0097
|
||||
p2 00A0
|
||||
p2.0 00A0
|
||||
p2.1 00A1
|
||||
p2.2 00A2
|
||||
p2.3 00A3
|
||||
p2.4 00A4
|
||||
p2.5 00A5
|
||||
p2.6 00A6
|
||||
p2.7 00A7
|
||||
p3 00B0
|
||||
p3.0 00B0
|
||||
p3.1 00B1
|
||||
p3.2 00B2
|
||||
p3.3 00B3
|
||||
p3.4 00B4
|
||||
p3.5 00B5
|
||||
p3.6 00B6
|
||||
p3.7 00B7
|
||||
pcon 0087
|
||||
ps 00BC
|
||||
psw 00D0
|
||||
psw.0 00D0
|
||||
psw.1 00D1
|
||||
psw.2 00D2
|
||||
psw.3 00D3
|
||||
psw.4 00D4
|
||||
psw.5 00D5
|
||||
psw.6 00D6
|
||||
psw.7 00D7
|
||||
pt0 00B9
|
||||
pt1 00BB
|
||||
pt2 00BD
|
||||
px0 00B8
|
||||
px1 00BA
|
||||
rb8 009A
|
||||
rcap2h 00CB
|
||||
rcap2l 00CA
|
||||
rclk 00CD
|
||||
ren 009C
|
||||
ri 0098
|
||||
rs0 00D3
|
||||
rs1 00D4
|
||||
rxd 00B0
|
||||
sbuf 0099
|
||||
scon 0098
|
||||
scon.0 0098
|
||||
scon.1 0099
|
||||
scon.2 009A
|
||||
scon.3 009B
|
||||
scon.4 009C
|
||||
scon.5 009D
|
||||
scon.6 009E
|
||||
scon.7 009F
|
||||
sm0 009F
|
||||
sm1 009E
|
||||
sm2 009D
|
||||
sp 0081
|
||||
t2con 00C8
|
||||
t2con.0 00C8
|
||||
t2con.1 00C9
|
||||
t2con.2 00CA
|
||||
t2con.3 00CB
|
||||
t2con.4 00CC
|
||||
t2con.5 00CD
|
||||
t2con.6 00CE
|
||||
t2con.7 00CF
|
||||
tb8 009B
|
||||
tclk 00CC
|
||||
tcon 0088
|
||||
tcon.0 0088
|
||||
tcon.1 0089
|
||||
tcon.2 008A
|
||||
tcon.3 008B
|
||||
tcon.4 008C
|
||||
tcon.5 008D
|
||||
tcon.6 008E
|
||||
tcon.7 008F
|
||||
tf0 008D
|
||||
tf1 008F
|
||||
tf2 00CF
|
||||
th0 008C
|
||||
th1 008D
|
||||
th2 00CD
|
||||
ti 0099
|
||||
tl0 008A
|
||||
tl1 008B
|
||||
tl2 00CC
|
||||
tmod 0089
|
||||
tr0 008C
|
||||
tr1 008E
|
||||
tr2 00CA
|
||||
txd 00B1
|
||||
|
||||
ASxxxx Assembler V01.70 + NoICE + SDCC mods + Flat24 Feb-1999 (Intel 8051), page 2.
|
||||
|
||||
Area Table
|
||||
|
||||
0 _CODE size 0 flags 0
|
||||
1 RSEG size 0 flags 0
|
||||
2 REG_BANK_0 size 8 flags 4
|
||||
3 DSEG size 0 flags 0
|
||||
4 OSEG size 0 flags 4
|
||||
5 ISEG size 0 flags 0
|
||||
6 IABS size 0 flags 8
|
||||
7 BSEG size 0 flags 80
|
||||
8 PSEG size 0 flags 50
|
||||
9 XSEG size 0 flags 40
|
||||
A XABS size 0 flags 48
|
||||
B HOME size 0 flags 20
|
||||
C GSINIT0 size 0 flags 20
|
||||
D GSINIT1 size 0 flags 20
|
||||
E GSINIT2 size 0 flags 20
|
||||
F GSINIT3 size 0 flags 20
|
||||
10 GSINIT4 size 0 flags 20
|
||||
11 GSINIT5 size 0 flags 20
|
||||
12 GSINIT size 0 flags 20
|
||||
13 GSFINAL size 0 flags 20
|
||||
14 CSEG size 46 flags 20
|
||||
15 CONST size 0 flags 20
|
||||
16 CABS size 0 flags 28
|
||||
123
firmware/GN3S_v2/lib/i2c.c
Normal file
123
firmware/GN3S_v2/lib/i2c.c
Normal file
@@ -0,0 +1,123 @@
|
||||
/* -*- c++ -*- */
|
||||
/*
|
||||
* Copyright 2003 Free Software Foundation, Inc.
|
||||
*
|
||||
* This file is part of GNU Radio
|
||||
*
|
||||
* GNU Radio is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* GNU Radio is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with GNU Radio; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
|
||||
* Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#include "i2c.h"
|
||||
#include "fx2regs.h"
|
||||
#include <string.h>
|
||||
|
||||
|
||||
// issue a stop bus cycle and wait for completion
|
||||
|
||||
|
||||
// returns non-zero if successful, else 0
|
||||
unsigned char
|
||||
i2c_read (unsigned char addr, xdata unsigned char *buf, unsigned char len)
|
||||
{
|
||||
volatile unsigned char junk;
|
||||
|
||||
if (len == 0) // reading zero bytes always works
|
||||
return 1;
|
||||
|
||||
while (I2CS & bmSTOP) // wait for stop to clear
|
||||
;
|
||||
|
||||
I2CS = bmSTART;
|
||||
I2DAT = (addr << 1) | 1; // write address and direction (1's the read bit)
|
||||
|
||||
while ((I2CS & bmDONE) == 0)
|
||||
;
|
||||
|
||||
if ((I2CS & bmBERR) || (I2CS & bmACK) == 0) // no device answered...
|
||||
goto fail;
|
||||
|
||||
if (len == 1)
|
||||
I2CS |= bmLASTRD;
|
||||
|
||||
junk = I2DAT; // trigger the first read cycle
|
||||
|
||||
while (--len != 0){
|
||||
while ((I2CS & bmDONE) == 0)
|
||||
;
|
||||
|
||||
if (I2CS & bmBERR)
|
||||
goto fail;
|
||||
|
||||
if (len == 1)
|
||||
I2CS |= bmLASTRD;
|
||||
|
||||
*buf++ = I2DAT; // get data, trigger another read
|
||||
}
|
||||
|
||||
// wait for final byte
|
||||
|
||||
while ((I2CS & bmDONE) == 0)
|
||||
;
|
||||
|
||||
if (I2CS & bmBERR)
|
||||
goto fail;
|
||||
|
||||
I2CS |= bmSTOP;
|
||||
*buf = I2DAT;
|
||||
|
||||
return 1;
|
||||
|
||||
fail:
|
||||
I2CS |= bmSTOP;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
// returns non-zero if successful, else 0
|
||||
unsigned char
|
||||
i2c_write (unsigned char addr, xdata const unsigned char *buf, unsigned char len)
|
||||
{
|
||||
while (I2CS & bmSTOP) // wait for stop to clear
|
||||
;
|
||||
|
||||
I2CS = bmSTART;
|
||||
I2DAT = (addr << 1) | 0; // write address and direction (0's the write bit)
|
||||
|
||||
while ((I2CS & bmDONE) == 0)
|
||||
;
|
||||
|
||||
if ((I2CS & bmBERR) || (I2CS & bmACK) == 0) // no device answered...
|
||||
goto fail;
|
||||
|
||||
while (len > 0){
|
||||
I2DAT = *buf++;
|
||||
len--;
|
||||
|
||||
while ((I2CS & bmDONE) == 0)
|
||||
;
|
||||
|
||||
if ((I2CS & bmBERR) || (I2CS & bmACK) == 0) // no device answered...
|
||||
goto fail;
|
||||
}
|
||||
|
||||
I2CS |= bmSTOP;
|
||||
return 1;
|
||||
|
||||
fail:
|
||||
I2CS |= bmSTOP;
|
||||
return 0;
|
||||
}
|
||||
1138
firmware/GN3S_v2/lib/isr.asm
Normal file
1138
firmware/GN3S_v2/lib/isr.asm
Normal file
File diff suppressed because it is too large
Load Diff
167
firmware/GN3S_v2/lib/isr.c
Normal file
167
firmware/GN3S_v2/lib/isr.c
Normal file
@@ -0,0 +1,167 @@
|
||||
/* -*- c++ -*- */
|
||||
/*
|
||||
* Copyright 2003 Free Software Foundation, Inc.
|
||||
*
|
||||
* This file is part of GNU Radio
|
||||
*
|
||||
* GNU Radio is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* GNU Radio is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with GNU Radio; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
|
||||
* Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#include "isr.h"
|
||||
#include "fx2regs.h"
|
||||
#include "syncdelay.h"
|
||||
|
||||
extern xdata unsigned char _standard_interrupt_vector[];
|
||||
extern xdata unsigned char _usb_autovector[];
|
||||
extern xdata unsigned char _fifo_gpif_autovector[];
|
||||
|
||||
#define LJMP_OPCODE 0x02
|
||||
|
||||
/*
|
||||
* Hook standard interrupt vector.
|
||||
*
|
||||
* vector_number is from the SV_<foo> list.
|
||||
* addr is the address of the interrupt service routine.
|
||||
*/
|
||||
void
|
||||
hook_sv (unsigned char vector_number, unsigned short addr)
|
||||
{
|
||||
bit t;
|
||||
|
||||
// sanity checks
|
||||
|
||||
if (vector_number < SV_MIN || vector_number > SV_MAX)
|
||||
return;
|
||||
|
||||
if ((vector_number & 0x0f) != 0x03 && (vector_number & 0x0f) != 0x0b)
|
||||
return;
|
||||
|
||||
t = EA;
|
||||
EA = 0;
|
||||
_standard_interrupt_vector[vector_number] = LJMP_OPCODE;
|
||||
_standard_interrupt_vector[vector_number + 1] = addr >> 8;
|
||||
_standard_interrupt_vector[vector_number + 2] = addr & 0xff;
|
||||
EA = t;
|
||||
}
|
||||
|
||||
/*
|
||||
* Hook usb interrupt vector.
|
||||
*
|
||||
* vector_number is from the UV_<foo> list.
|
||||
* addr is the address of the interrupt service routine.
|
||||
*/
|
||||
void
|
||||
hook_uv (unsigned char vector_number, unsigned short addr)
|
||||
{
|
||||
bit t;
|
||||
|
||||
// sanity checks
|
||||
|
||||
if (vector_number < UV_MIN || vector_number > UV_MAX)
|
||||
return;
|
||||
|
||||
if ((vector_number & 0x3) != 0)
|
||||
return;
|
||||
|
||||
t = EA;
|
||||
EA = 0;
|
||||
_usb_autovector[vector_number] = LJMP_OPCODE;
|
||||
_usb_autovector[vector_number + 1] = addr >> 8;
|
||||
_usb_autovector[vector_number + 2] = addr & 0xff;
|
||||
EA = t;
|
||||
}
|
||||
|
||||
/*
|
||||
* Hook fifo/gpif interrupt vector.
|
||||
*
|
||||
* vector_number is from the FGV_<foo> list.
|
||||
* addr is the address of the interrupt service routine.
|
||||
*/
|
||||
void
|
||||
hook_fgv (unsigned char vector_number, unsigned short addr)
|
||||
{
|
||||
bit t;
|
||||
|
||||
// sanity checks
|
||||
|
||||
if (vector_number < FGV_MIN || vector_number > FGV_MAX)
|
||||
return;
|
||||
|
||||
if ((vector_number & 0x3) != 0)
|
||||
return;
|
||||
|
||||
t = EA;
|
||||
EA = 0;
|
||||
_fifo_gpif_autovector[vector_number] = LJMP_OPCODE;
|
||||
_fifo_gpif_autovector[vector_number + 1] = addr >> 8;
|
||||
_fifo_gpif_autovector[vector_number + 2] = addr & 0xff;
|
||||
EA = t;
|
||||
}
|
||||
|
||||
/*
|
||||
* One time call to enable autovectoring for both USB and FIFO/GPIF.
|
||||
*
|
||||
* This disables all USB and FIFO/GPIF interrupts and clears
|
||||
* any pending interrupts too. It leaves the master USB and FIFO/GPIF
|
||||
* interrupts enabled.
|
||||
*/
|
||||
void
|
||||
setup_autovectors (void)
|
||||
{
|
||||
// disable master usb and fifo/gpif interrupt enables
|
||||
EIUSB = 0;
|
||||
EIEX4 = 0;
|
||||
|
||||
hook_sv (SV_INT_2, (unsigned short) _usb_autovector);
|
||||
hook_sv (SV_INT_4, (unsigned short) _fifo_gpif_autovector);
|
||||
|
||||
// disable all fifo interrupt enables
|
||||
SYNCDELAY;
|
||||
EP2FIFOIE = 0; SYNCDELAY;
|
||||
EP4FIFOIE = 0; SYNCDELAY;
|
||||
EP6FIFOIE = 0; SYNCDELAY;
|
||||
EP8FIFOIE = 0; SYNCDELAY;
|
||||
|
||||
// clear all pending fifo irqs
|
||||
EP2FIFOIRQ = 0xff; SYNCDELAY;
|
||||
EP4FIFOIRQ = 0xff; SYNCDELAY;
|
||||
EP6FIFOIRQ = 0xff; SYNCDELAY;
|
||||
EP8FIFOIRQ = 0xff; SYNCDELAY;
|
||||
|
||||
IBNIE = 0;
|
||||
IBNIRQ = 0xff;
|
||||
NAKIE = 0;
|
||||
NAKIRQ = 0xff;
|
||||
USBIE = 0;
|
||||
USBIRQ = 0xff;
|
||||
EPIE = 0;
|
||||
EPIRQ = 0xff;
|
||||
SYNCDELAY; GPIFIE = 0;
|
||||
SYNCDELAY; GPIFIRQ = 0xff;
|
||||
USBERRIE = 0;
|
||||
USBERRIRQ = 0xff;
|
||||
CLRERRCNT = 0;
|
||||
|
||||
INTSETUP = bmAV2EN | bmAV4EN | bmINT4IN;
|
||||
|
||||
// clear master irq's for usb and fifo/gpif
|
||||
EXIF &= ~bmEXIF_USBINT;
|
||||
EXIF &= ~bmEXIF_IE4;
|
||||
|
||||
// enable master usb and fifo/gpif interrrupts
|
||||
EIUSB = 1;
|
||||
EIEX4 = 1;
|
||||
}
|
||||
1138
firmware/GN3S_v2/lib/isr.lst
Normal file
1138
firmware/GN3S_v2/lib/isr.lst
Normal file
File diff suppressed because it is too large
Load Diff
513
firmware/GN3S_v2/lib/isr.rel
Normal file
513
firmware/GN3S_v2/lib/isr.rel
Normal file
@@ -0,0 +1,513 @@
|
||||
XH
|
||||
H 17 areas 14C global symbols
|
||||
M isr
|
||||
O -mmcs51 --model-small
|
||||
S _EP8FIFOCFG DefE61B
|
||||
S _EPIRQ DefE65F
|
||||
S _USBERRIE DefE662
|
||||
S _EP6CS DefE6A5
|
||||
S _GPIFHOLDAMOUNT DefE60C
|
||||
S _SBUF1 Def00C1
|
||||
S _EIEX6 Def00EC
|
||||
S _EP1INBC DefE68F
|
||||
S _EP8FIFOBCL DefE6B2
|
||||
S _DBUG DefE6F8
|
||||
S _B Def00F0
|
||||
S _EXEN2 Def00CB
|
||||
S _EPIE DefE65E
|
||||
S _WAKEUPCS DefE682
|
||||
S _EP1OUTBC DefE68D
|
||||
S _EP8CS DefE6A6
|
||||
S _EP2GPIFTRIG DefE6D4
|
||||
S _SP Def0081
|
||||
S _SCON0 Def0098
|
||||
S _AUTODAT1 Def009C
|
||||
S _EI2C Def00E9
|
||||
S _INT2IVEC DefE666
|
||||
S _AUTODAT2 Def009F
|
||||
S _SCON1 Def00C0
|
||||
S _SMOD1 Def00DF
|
||||
S _MICROFRAME DefE686
|
||||
S _SUDPTRCTL DefE6B5
|
||||
S _EP4GPIFTRIG DefE6DC
|
||||
S _EP2468STAT Def00AA
|
||||
S _OV Def00D2
|
||||
S _INT4IVEC DefE667
|
||||
S _GPIFSGLDATLNOX Def00BF
|
||||
S _T2CON Def00C8
|
||||
S _EP6GPIFTRIG DefE6E4
|
||||
S _ACC Def00E0
|
||||
S _EP2FIFOBUF DefF000
|
||||
S _C_T2 Def00C9
|
||||
S _BREAKPT DefE605
|
||||
S _EP2FIFOPFH DefE630
|
||||
S _EP8GPIFTRIG DefE6EC
|
||||
S _AUTOPTRH2 Def009D
|
||||
S _SETUPDAT DefE6B8
|
||||
S _EP2GPIFFLGSEL DefE6D2
|
||||
S _EP4FIFOBUF DefF400
|
||||
S _EIPX4 Def00FA
|
||||
S _EP4FIFOPFH DefE632
|
||||
S _EP2ISOINPKTS DefE640
|
||||
S _GPIFREADYCFG DefE6F3
|
||||
S _EIPX5 Def00FB
|
||||
S _EP4GPIFFLGSEL DefE6DA
|
||||
S _FLOWSTBHPERIOD DefE6CD
|
||||
S _EP6FIFOBUF DefF800
|
||||
S _EXIF Def0091
|
||||
S _RCLK Def00CD
|
||||
S _EIPX6 Def00FC
|
||||
S _EP2FIFOPFL DefE631
|
||||
S _EP6FIFOPFH DefE634
|
||||
S _EP4ISOINPKTS DefE641
|
||||
S _DPH1 Def0085
|
||||
S _AUTOPTRL2 Def009E
|
||||
S __standard_interrupt_vector Ref0000
|
||||
S _EP6GPIFFLGSEL DefE6E2
|
||||
S _EP8FIFOBUF DefFC00
|
||||
S _TCLK Def00CC
|
||||
S _PI2C Def00F9
|
||||
S _EP4FIFOPFL DefE633
|
||||
S _EP8FIFOPFH DefE636
|
||||
S _EP6ISOINPKTS DefE642
|
||||
S _FNADDR DefE687
|
||||
S _EP8GPIFFLGSEL DefE6EA
|
||||
S _TESTCFG DefE6F9
|
||||
S _PCON Def0087
|
||||
S _P Def00D0
|
||||
S _GPIF_WAVE_DATA DefE400
|
||||
S _EP6FIFOPFL DefE635
|
||||
S _EP8ISOINPKTS DefE643
|
||||
S _I2CS DefE678
|
||||
S _DPL1 Def0084
|
||||
S _GPIFIRQ DefE661
|
||||
S _EP0BCH DefE68A
|
||||
S _EP01STAT Def00BA
|
||||
S __fifo_gpif_autovector Ref0000
|
||||
S _EP8FIFOPFL DefE637
|
||||
S _EP1INCS DefE6A2
|
||||
S _EIE Def00E8
|
||||
S _RESI Def00DC
|
||||
S _GPIFIE DefE660
|
||||
S _EP2BCH DefE690
|
||||
S _EP1OUTCS DefE6A1
|
||||
S _TCON Def0088
|
||||
S _TMOD Def0089
|
||||
S _OEA Def00B2
|
||||
S _EXF2 Def00CE
|
||||
S _EP0BCL DefE68B
|
||||
S _EP4BCH DefE694
|
||||
S _OEB Def00B3
|
||||
S _REN1 Def00C4
|
||||
S _EP2CFG DefE612
|
||||
S _EP2FIFOIRQ DefE651
|
||||
S _GPIFREADYSTAT DefE6F4
|
||||
S _OEC Def00B4
|
||||
S _EP2BCL DefE691
|
||||
S _EP6BCH DefE698
|
||||
S _OED Def00B5
|
||||
S _EP4CFG DefE613
|
||||
S _EP2FIFOIE DefE650
|
||||
S _EP4FIFOIRQ DefE653
|
||||
S _IOA Def0080
|
||||
S _OEE Def00B6
|
||||
S _EP4BCL DefE695
|
||||
S _EP8BCH DefE69C
|
||||
S _IOB Def0090
|
||||
S _PUSB Def00F8
|
||||
S _EP6CFG DefE614
|
||||
S _EP4FIFOIE DefE652
|
||||
S _EP6FIFOIRQ DefE655
|
||||
S _IOC Def00A0
|
||||
S _INTSETUP DefE668
|
||||
S _EP6BCL DefE699
|
||||
S _DPH Def0083
|
||||
S _IOD Def00B0
|
||||
S _EP8CFG DefE615
|
||||
S _EP6FIFOIE DefE654
|
||||
S _EP8FIFOIRQ DefE657
|
||||
S _USBFRAMEH DefE684
|
||||
S _IOE Def00B1
|
||||
S _RB81 Def00C2
|
||||
S _EP2AUTOINLENH DefE620
|
||||
S _EP8BCL DefE69D
|
||||
S _GPIFABORT DefE6F5
|
||||
S _INT2CLR Def00A1
|
||||
S _EIP Def00F8
|
||||
S _IE0 Def0089
|
||||
S _EP8FIFOIE DefE656
|
||||
S _IE1 Def008B
|
||||
S _TB81 Def00C3
|
||||
S _EP4AUTOINLENH DefE622
|
||||
S _DPL Def0082
|
||||
S _INT4CLR Def00A2
|
||||
S _AUTOPTRSETUP Def00AF
|
||||
S _RCAP2H Def00CB
|
||||
S _USBFRAMEL DefE685
|
||||
S _XGPIFSGLDATLX DefE6F1
|
||||
S _FLOWEQ0CTL DefE6C8
|
||||
S _FLOWSTB DefE6CB
|
||||
S _SM01 Def00C7
|
||||
S _INT6 Def00DB
|
||||
S _EP2AUTOINLENL DefE621
|
||||
S _EP6AUTOINLENH DefE624
|
||||
S _SUSPEND DefE681
|
||||
S _FLOWEQ1CTL DefE6C9
|
||||
S _EP0BUF DefE740
|
||||
S _SM11 Def00C6
|
||||
S _CP_RL2 Def00C8
|
||||
S _GPIFWFSELECT DefE6C0
|
||||
S _SM21 Def00C5
|
||||
S _EP4AUTOINLENL DefE623
|
||||
S _EP8AUTOINLENH DefE626
|
||||
S _RCAP2L Def00CA
|
||||
S _SEL Def0086
|
||||
S _AC Def00D6
|
||||
S _IFCONFIG DefE601
|
||||
S _IBNIRQ DefE659
|
||||
S _GPIFADRH DefE6C4
|
||||
S _XGPIFSGLDATH DefE6F0
|
||||
S _REN Def009C
|
||||
S _EP6AUTOINLENL DefE625
|
||||
S _NAKIRQ DefE65B
|
||||
S _FLOWLOGIC DefE6C7
|
||||
S _EA Def00AF
|
||||
S _FIFORESET DefE604
|
||||
S _IBNIE DefE658
|
||||
S _GPIFIDLECTL DefE6C2
|
||||
S _UDMACRCH DefE67D
|
||||
S _DPS Def0086
|
||||
S _EP8AUTOINLENL DefE627
|
||||
S _NAKIE DefE65A
|
||||
S _CT1 DefE6FB
|
||||
S _ES0 Def00AC
|
||||
S _FIFOPINPOLAR DefE609
|
||||
S _GPIFADRL DefE6C5
|
||||
S _EP2GPIFPFSTOP DefE6D3
|
||||
S _CT2 DefE6FC
|
||||
S _GPIFSGLDATLX Def00BE
|
||||
S _ET0 Def00A9
|
||||
S _ES1 Def00AE
|
||||
S _SUDPTRH DefE6B3
|
||||
S _USBTEST DefE6FA
|
||||
S _CT3 DefE6FD
|
||||
S _MPAGE Def0092
|
||||
S _TF0 Def008D
|
||||
S _ET1 Def00AB
|
||||
S _EP4GPIFPFSTOP DefE6DB
|
||||
S _UDMACRCL DefE67E
|
||||
S _CT4 DefE6FE
|
||||
S _EP24FIFOFLGS Def00AB
|
||||
S _TF1 Def008F
|
||||
S _ET2 Def00AD
|
||||
S _RES_WAVEDATA_END DefE480
|
||||
S _TH0 Def008C
|
||||
S _RB8 Def009A
|
||||
S _RI1 Def00C0
|
||||
S _TF2 Def00CF
|
||||
S _EP1INCFG DefE611
|
||||
S _TOGCTL DefE683
|
||||
S _EP6GPIFPFSTOP DefE6E3
|
||||
S _TH1 Def008D
|
||||
S _GPIFSGLDATH Def00BD
|
||||
S _IT0 Def0088
|
||||
S _EX0 Def00A8
|
||||
S _EP1OUTCFG DefE610
|
||||
S _SUDPTRL DefE6B4
|
||||
S _CKCON Def008E
|
||||
S _IE Def00A8
|
||||
S _TH2 Def00CD
|
||||
S _EICON Def00D8
|
||||
S _IT1 Def008A
|
||||
S _TB8 Def009B
|
||||
S _EX1 Def00AA
|
||||
S _TI1 Def00C1
|
||||
S _CLRERRCNT DefE665
|
||||
S _GPIFTCB0 DefE6D1
|
||||
S _EP8GPIFPFSTOP DefE6EB
|
||||
S _REVCTL DefE60B
|
||||
S _ERRCNTLIM DefE664
|
||||
S _GPIFTCB1 DefE6D0
|
||||
S _TL0 Def008A
|
||||
S _APTR1H Def009A
|
||||
S _SM0 Def009F
|
||||
S _UART230 DefE608
|
||||
S _GPIFTCB2 DefE6CF
|
||||
S _TL1 Def008B
|
||||
S _A0 Def0080
|
||||
S _SM1 Def009E
|
||||
S _GPIFTCB3 DefE6CE
|
||||
S _UDMACRCQUAL DefE67F
|
||||
S _TL2 Def00CC
|
||||
S _A1 Def0081
|
||||
S _SM2 Def009D
|
||||
S _FL Def00D1
|
||||
S _EP68FIFOFLGS Def00AC
|
||||
S _A2 Def0082
|
||||
S _PS0 Def00BC
|
||||
S __usb_autovector Ref0000
|
||||
S _I2DAT DefE679
|
||||
S _APTR1L Def009B
|
||||
S _A3 Def0083
|
||||
S _D0 Def00B0
|
||||
S _PT0 Def00B9
|
||||
S _PS1 Def00BE
|
||||
S _BPADDRH DefE606
|
||||
S _A4 Def0084
|
||||
S _D1 Def00B1
|
||||
S _PT1 Def00BB
|
||||
S _RS0 Def00D3
|
||||
S _USBIRQ DefE65D
|
||||
S _PORTACFG DefE670
|
||||
S _FLOWSTBEDGE DefE6CC
|
||||
S _A5 Def0085
|
||||
S _TR0 Def008C
|
||||
S _D2 Def00B2
|
||||
S _PT2 Def00BD
|
||||
S _RS1 Def00D4
|
||||
S _F0 Def00D5
|
||||
S _PINFLAGSAB DefE602
|
||||
S _EP2FIFOFLGS DefE6A7
|
||||
S _A6 Def0086
|
||||
S _TR1 Def008E
|
||||
S _D3 Def00B3
|
||||
S _USBIE DefE65C
|
||||
S _PORTCCFG DefE671
|
||||
S _EP2FIFOBCH DefE6AB
|
||||
S _A7 Def0087
|
||||
S _D4 Def00B4
|
||||
S _PX0 Def00B8
|
||||
S _TR2 Def00CA
|
||||
S _ERESI Def00DD
|
||||
S _EIUSB Def00E8
|
||||
S _BPADDRL DefE607
|
||||
S _EP4FIFOFLGS DefE6A8
|
||||
S _GPIFCTLCFG DefE6C3
|
||||
S _FLOWSTATE DefE6C6
|
||||
S _IP Def00B8
|
||||
S _D5 Def00B5
|
||||
S _PX1 Def00BA
|
||||
S _REVID DefE60A
|
||||
S _PORTECFG DefE672
|
||||
S _EP4FIFOBCH DefE6AD
|
||||
S _GPIFIDLECS DefE6C1
|
||||
S _FLOWHOLDOFF DefE6CA
|
||||
S _EP1INBUF DefE7C0
|
||||
S _PSW Def00D0
|
||||
S _D6 Def00B6
|
||||
S _PINFLAGSCD DefE603
|
||||
S _EP2FIFOCFG DefE618
|
||||
S _XAUTODAT1 DefE67B
|
||||
S _EP0CS DefE6A0
|
||||
S _EP6FIFOFLGS DefE6A9
|
||||
S _EP1OUTBUF DefE780
|
||||
S _RI Def0098
|
||||
S _D7 Def00B7
|
||||
S _XAUTODAT2 DefE67C
|
||||
S _EP2FIFOBCL DefE6AC
|
||||
S _EP6FIFOBCH DefE6AF
|
||||
S _GPIFTRIG Def00BB
|
||||
S _CY Def00D7
|
||||
S _EP4FIFOCFG DefE619
|
||||
S _INPKTEND DefE648
|
||||
S _EP2CS DefE6A3
|
||||
S _EP8FIFOFLGS DefE6AA
|
||||
S _TI Def0099
|
||||
S _CPUCS DefE600
|
||||
S _OUTPKTEND DefE649
|
||||
S _I2CTL DefE67A
|
||||
S _EP4FIFOBCL DefE6AE
|
||||
S _EP8FIFOBCH DefE6B1
|
||||
S _XGPIFSGLDATLNOX DefE6F2
|
||||
S _EP6FIFOCFG DefE61A
|
||||
S _USBERRIRQ DefE663
|
||||
S _EP4CS DefE6A4
|
||||
S _EIEX4 Def00EA
|
||||
S _USBCS DefE680
|
||||
S _EP6FIFOBCL DefE6B0
|
||||
S _SBUF0 Def0099
|
||||
S _EIEX5 Def00EB
|
||||
A _CODE size 0 flags 0 addr 0
|
||||
A RSEG size 0 flags 0 addr 0
|
||||
A REG_BANK_0 size 8 flags 4 addr 0
|
||||
A DSEG size 0 flags 0 addr 0
|
||||
A OSEG size 2 flags 4 addr 0
|
||||
S _hook_fgv_PARM_2 Def0000
|
||||
S _hook_sv_PARM_2 Def0000
|
||||
S _hook_uv_PARM_2 Def0000
|
||||
A ISEG size 0 flags 0 addr 0
|
||||
A IABS size 0 flags 8 addr 0
|
||||
A BSEG size 3 flags 80 addr 0
|
||||
A PSEG size 0 flags 50 addr 0
|
||||
A XSEG size 0 flags 40 addr 0
|
||||
A XABS size 0 flags 48 addr 0
|
||||
A HOME size 0 flags 20 addr 0
|
||||
A GSINIT0 size 0 flags 20 addr 0
|
||||
A GSINIT1 size 0 flags 20 addr 0
|
||||
A GSINIT2 size 0 flags 20 addr 0
|
||||
A GSINIT3 size 0 flags 20 addr 0
|
||||
A GSINIT4 size 0 flags 20 addr 0
|
||||
A GSINIT5 size 0 flags 20 addr 0
|
||||
A GSINIT size 0 flags 20 addr 0
|
||||
A GSFINAL size 0 flags 20 addr 0
|
||||
A CSEG size 1B2 flags 20 addr 0
|
||||
S _hook_sv Def0000
|
||||
S _hook_uv Def0063
|
||||
S _setup_autovectors Def010A
|
||||
S _hook_fgv Def00B4
|
||||
A CONST size 0 flags 20 addr 0
|
||||
A CABS size 0 flags 28 addr 0
|
||||
T 00 00
|
||||
R 00 00 00 02
|
||||
T 00 00
|
||||
R 00 00 00 04
|
||||
T 00 00
|
||||
R 00 00 00 04
|
||||
T 00 00
|
||||
R 00 00 00 04
|
||||
T 00 00
|
||||
R 00 00 00 04
|
||||
T 00 00
|
||||
R 00 00 00 04
|
||||
T 00 00
|
||||
R 00 00 00 04
|
||||
T 00 00
|
||||
R 00 00 00 07
|
||||
T 00 00
|
||||
R 00 00 00 07
|
||||
T 00 01
|
||||
R 00 00 00 07
|
||||
T 00 01
|
||||
R 00 00 00 07
|
||||
T 00 02
|
||||
R 00 00 00 07
|
||||
T 00 02
|
||||
R 00 00 00 07
|
||||
T 00 00
|
||||
R 00 00 00 14
|
||||
T 00 00 AA 82 BA 03 00
|
||||
R 00 00 00 14
|
||||
T 00 05
|
||||
R 00 00 00 14
|
||||
T 00 05 40 05 EA 24 9C 50 01
|
||||
R 00 00 00 14
|
||||
T 00 0C
|
||||
R 00 00 00 14
|
||||
T 00 0C 22
|
||||
R 00 00 00 14
|
||||
T 00 0D
|
||||
R 00 00 00 14
|
||||
T 00 0D 74 0F 5A FB BB 03 02 80 07
|
||||
R 00 00 00 14
|
||||
T 00 16
|
||||
R 00 00 00 14
|
||||
T 00 16 74 0F 5A FB BB 0B 45
|
||||
R 00 00 00 14
|
||||
T 00 1D
|
||||
R 00 00 00 14
|
||||
T 00 1D A2 AF 92 00 00 00 C2 AF EA 24 00 00 00 F5
|
||||
R 00 00 00 14 F1 21 05 00 07 F1 03 0C 00 3C
|
||||
T 00 27 82 E4 34 00 00 00 F5 83 74 02 F0 7B 00 74
|
||||
R 00 00 00 14 F1 83 05 00 3C
|
||||
T 00 33 01 2A FC E4 3B FD EC 24 00 00 00 F5 82 ED
|
||||
R 00 00 00 14 F1 03 0A 00 3C
|
||||
T 00 3F 34 00 00 00 F5 83 E5 00 00 01 FC F0 74 02
|
||||
R 00 00 00 14 F1 83 03 00 3C F1 21 09 00 04
|
||||
T 00 49 2A FA E4 3B FB EA 24 00 00 00 F5 82 EB 34
|
||||
R 00 00 00 14 F1 03 09 00 3C
|
||||
T 00 55 00 00 00 F5 83 AA 00 00 00 7B 00 EA F0 A2
|
||||
R 00 00 00 14 F1 83 02 00 3C F1 21 08 00 04
|
||||
T 00 5F 00 00 00 92 AF
|
||||
R 00 00 00 14 F1 21 02 00 07
|
||||
T 00 62
|
||||
R 00 00 00 14
|
||||
T 00 62 22
|
||||
R 00 00 00 14
|
||||
T 00 63
|
||||
R 00 00 00 14
|
||||
T 00 63 E5 82 FA 24 83 50 01 22
|
||||
R 00 00 00 14
|
||||
T 00 6B
|
||||
R 00 00 00 14
|
||||
T 00 6B EA 54 03 60 01 22
|
||||
R 00 00 00 14
|
||||
T 00 71
|
||||
R 00 00 00 14
|
||||
T 00 71 A2 AF 92 00 00 01 C2 AF EA 24 00 00 00 F5
|
||||
R 00 00 00 14 F1 21 05 00 07 F1 03 0C 00 F3
|
||||
T 00 7B 82 E4 34 00 00 00 F5 83 74 02 F0 7B 00 74
|
||||
R 00 00 00 14 F1 83 05 00 F3
|
||||
T 00 87 01 2A FC E4 3B FD EC 24 00 00 00 F5 82 ED
|
||||
R 00 00 00 14 F1 03 0A 00 F3
|
||||
T 00 93 34 00 00 00 F5 83 E5 00 00 01 F0 74 02 2A
|
||||
R 00 00 00 14 F1 83 03 00 F3 F1 21 09 00 04
|
||||
T 00 9D FA E4 3B FB EA 24 00 00 00 F5 82 EB 34
|
||||
R 00 00 00 14 F1 03 08 00 F3
|
||||
T 00 A8 00 00 00 F5 83 AA 00 00 00 EA F0 A2
|
||||
R 00 00 00 14 F1 83 02 00 F3 F1 21 08 00 04
|
||||
T 00 B0 00 00 01 92 AF 22
|
||||
R 00 00 00 14 F1 21 02 00 07
|
||||
T 00 B4
|
||||
R 00 00 00 14
|
||||
T 00 B4 AA 82 BA 80 00
|
||||
R 00 00 00 14
|
||||
T 00 B9
|
||||
R 00 00 00 14
|
||||
T 00 B9 40 05 EA 24 4B 50 01
|
||||
R 00 00 00 14
|
||||
T 00 C0
|
||||
R 00 00 00 14
|
||||
T 00 C0 22
|
||||
R 00 00 00 14
|
||||
T 00 C1
|
||||
R 00 00 00 14
|
||||
T 00 C1 EA 54 03 60 01 22
|
||||
R 00 00 00 14
|
||||
T 00 C7
|
||||
R 00 00 00 14
|
||||
T 00 C7 A2 AF 92 00 00 02 C2 AF EA 24 00 00 00 F5
|
||||
R 00 00 00 14 F1 21 05 00 07 F1 03 0C 00 51
|
||||
T 00 D1 82 E4 34 00 00 00 F5 83 74 02 F0 7B 00 74
|
||||
R 00 00 00 14 F1 83 05 00 51
|
||||
T 00 DD 01 2A FC E4 3B FD EC 24 00 00 00 F5 82 ED
|
||||
R 00 00 00 14 F1 03 0A 00 51
|
||||
T 00 E9 34 00 00 00 F5 83 E5 00 00 01 F0 74 02 2A
|
||||
R 00 00 00 14 F1 83 03 00 51 F1 21 09 00 04
|
||||
T 00 F3 FA E4 3B FB EA 24 00 00 00 F5 82 EB 34
|
||||
R 00 00 00 14 F1 03 08 00 51
|
||||
T 00 FE 00 00 00 F5 83 AA 00 00 00 EA F0 A2
|
||||
R 00 00 00 14 F1 83 02 00 51 F1 21 08 00 04
|
||||
T 01 06 00 00 02 92 AF 22
|
||||
R 00 00 00 14 F1 21 02 00 07
|
||||
T 01 0A
|
||||
R 00 00 00 14
|
||||
T 01 0A C2 E8 C2 EA 75 00 00 00 00 00 00 75
|
||||
R 00 00 00 14 F1 21 07 00 04 F1 03 0A 00 F3
|
||||
T 01 12 00 00 01 00 00 00 75 82 43 12
|
||||
R 00 00 00 14 F1 21 02 00 04 F1 83 05 00 F3
|
||||
T 01 18 00 00 75 00 00 00
|
||||
R 00 00 00 14 00 02 00 14 F1 21 05 00 04
|
||||
T 01 1C 00 00 00 75 00 00 01
|
||||
R 00 00 00 14 F1 03 02 00 51 F1 21 06 00 04
|
||||
T 01 1F 00 00 00 75 82 53 12 00 00 00 90 E6 50 E4
|
||||
R 00 00 00 14 F1 83 02 00 51 00 09 00 14
|
||||
T 01 2B F0 00 90 E6 52 E4 F0 00 90 E6 54 E4 F0 00
|
||||
R 00 00 00 14
|
||||
T 01 39 90 E6 56 E4 F0 00 90 E6 51 74 FF F0 00 90
|
||||
R 00 00 00 14
|
||||
T 01 47 E6 53 74 FF F0 00 90 E6 55 74 FF F0 00 90
|
||||
R 00 00 00 14
|
||||
T 01 55 E6 57 74 FF F0 00 90 E6 58 E4 F0 90 E6 59
|
||||
R 00 00 00 14
|
||||
T 01 63 74 FF F0 90 E6 5A E4 F0 90 E6 5B 74 FF F0
|
||||
R 00 00 00 14
|
||||
T 01 71 90 E6 5C E4 F0 90 E6 5D 74 FF F0 90 E6 5E
|
||||
R 00 00 00 14
|
||||
T 01 7F E4 F0 90 E6 5F 74 FF F0 00 90 E6 60 E4 F0
|
||||
R 00 00 00 14
|
||||
T 01 8D 00 90 E6 61 74 FF F0 90 E6 62 E4 F0 90
|
||||
R 00 00 00 14
|
||||
T 01 9A E6 63 74 FF F0 90 E6 65 E4 F0 90 E6 68 74
|
||||
R 00 00 00 14
|
||||
T 01 A8 0B F0 53 91 AF D2 E8 D2 EA 22
|
||||
R 00 00 00 14
|
||||
711
firmware/GN3S_v2/lib/isr.sym
Normal file
711
firmware/GN3S_v2/lib/isr.sym
Normal file
@@ -0,0 +1,711 @@
|
||||
ASxxxx Assembler V01.70 + NoICE + SDCC mods + Flat24 Feb-1999 (Intel 8051), page 1.
|
||||
|
||||
Symbol Table
|
||||
|
||||
A 00D6
|
||||
AC 00D6
|
||||
ACC 00E0
|
||||
ACC.0 00E0
|
||||
ACC.1 00E1
|
||||
ACC.2 00E2
|
||||
ACC.3 00E3
|
||||
ACC.4 00E4
|
||||
ACC.5 00E5
|
||||
ACC.6 00E6
|
||||
ACC.7 00E7
|
||||
B 00F0
|
||||
B.0 00F0
|
||||
B.1 00F1
|
||||
B.2 00F2
|
||||
B.3 00F3
|
||||
B.4 00F4
|
||||
B.5 00F5
|
||||
B.6 00F6
|
||||
B.7 00F7
|
||||
CPRL2 00C8
|
||||
CT2 00C9
|
||||
CY 00D7
|
||||
DPH 0083
|
||||
DPL 0082
|
||||
EA 00AF
|
||||
ES 00AC
|
||||
ET0 00A9
|
||||
ET1 00AB
|
||||
ET2 00AD
|
||||
EX0 00A8
|
||||
EX1 00AA
|
||||
EXEN2 00CB
|
||||
EXF2 00CE
|
||||
F0 00D5
|
||||
IE 00A8
|
||||
IE.0 00A8
|
||||
IE.1 00A9
|
||||
IE.2 00AA
|
||||
IE.3 00AB
|
||||
IE.4 00AC
|
||||
IE.5 00AD
|
||||
IE.7 00AF
|
||||
IE0 0089
|
||||
IE1 008B
|
||||
INT0 00B2
|
||||
INT1 00B3
|
||||
IP 00B8
|
||||
IP.0 00B8
|
||||
IP.1 00B9
|
||||
IP.2 00BA
|
||||
IP.3 00BB
|
||||
IP.4 00BC
|
||||
IP.5 00BD
|
||||
IT0 0088
|
||||
IT1 008A
|
||||
OV 00D2
|
||||
P 00D0
|
||||
P0 0080
|
||||
P0.0 0080
|
||||
P0.1 0081
|
||||
P0.2 0082
|
||||
P0.3 0083
|
||||
P0.4 0084
|
||||
P0.5 0085
|
||||
P0.6 0086
|
||||
P0.7 0087
|
||||
P1 0090
|
||||
P1.0 0090
|
||||
P1.1 0091
|
||||
P1.2 0092
|
||||
P1.3 0093
|
||||
P1.4 0094
|
||||
P1.5 0095
|
||||
P1.6 0096
|
||||
P1.7 0097
|
||||
P2 00A0
|
||||
P2.0 00A0
|
||||
P2.1 00A1
|
||||
P2.2 00A2
|
||||
P2.3 00A3
|
||||
P2.4 00A4
|
||||
P2.5 00A5
|
||||
P2.6 00A6
|
||||
P2.7 00A7
|
||||
P3 00B0
|
||||
P3.0 00B0
|
||||
P3.1 00B1
|
||||
P3.2 00B2
|
||||
P3.3 00B3
|
||||
P3.4 00B4
|
||||
P3.5 00B5
|
||||
P3.6 00B6
|
||||
P3.7 00B7
|
||||
PCON 0087
|
||||
PS 00BC
|
||||
PSW 00D0
|
||||
PSW.0 00D0
|
||||
PSW.1 00D1
|
||||
PSW.2 00D2
|
||||
PSW.3 00D3
|
||||
PSW.4 00D4
|
||||
PSW.5 00D5
|
||||
PSW.6 00D6
|
||||
PSW.7 00D7
|
||||
PT0 00B9
|
||||
PT1 00BB
|
||||
PT2 00BD
|
||||
PX0 00B8
|
||||
PX1 00BA
|
||||
RB8 009A
|
||||
RCAP2H 00CB
|
||||
RCAP2L 00CA
|
||||
RCLK 00CD
|
||||
REN 009C
|
||||
RI 0098
|
||||
RS0 00D3
|
||||
RS1 00D4
|
||||
RXD 00B0
|
||||
SBUF 0099
|
||||
SCON 0098
|
||||
SCON.0 0098
|
||||
SCON.1 0099
|
||||
SCON.2 009A
|
||||
SCON.3 009B
|
||||
SCON.4 009C
|
||||
SCON.5 009D
|
||||
SCON.6 009E
|
||||
SCON.7 009F
|
||||
SM0 009F
|
||||
SM1 009E
|
||||
SM2 009D
|
||||
SP 0081
|
||||
T2CON 00C8
|
||||
T2CON.0 00C8
|
||||
T2CON.1 00C9
|
||||
T2CON.2 00CA
|
||||
T2CON.3 00CB
|
||||
T2CON.4 00CC
|
||||
T2CON.5 00CD
|
||||
T2CON.6 00CE
|
||||
T2CON.7 00CF
|
||||
TB8 009B
|
||||
TCLK 00CC
|
||||
TCON 0088
|
||||
TCON.0 0088
|
||||
TCON.1 0089
|
||||
TCON.2 008A
|
||||
TCON.3 008B
|
||||
TCON.4 008C
|
||||
TCON.5 008D
|
||||
TCON.6 008E
|
||||
TCON.7 008F
|
||||
TF0 008D
|
||||
TF1 008F
|
||||
TF2 00CF
|
||||
TH0 008C
|
||||
TH1 008D
|
||||
TH2 00CD
|
||||
TI 0099
|
||||
TL0 008A
|
||||
TL1 008B
|
||||
TL2 00CC
|
||||
TMOD 0089
|
||||
TR0 008C
|
||||
TR1 008E
|
||||
TR2 00CA
|
||||
TXD 00B1
|
||||
_A0 = 0080 G
|
||||
_A1 = 0081 G
|
||||
_A2 = 0082 G
|
||||
_A3 = 0083 G
|
||||
_A4 = 0084 G
|
||||
_A5 = 0085 G
|
||||
_A6 = 0086 G
|
||||
_A7 = 0087 G
|
||||
_AC = 00D6 G
|
||||
_ACC = 00E0 G
|
||||
_APTR1H = 009A G
|
||||
_APTR1L = 009B G
|
||||
_AUTODAT1 = 009C G
|
||||
_AUTODAT2 = 009F G
|
||||
_AUTOPTRH2 = 009D G
|
||||
_AUTOPTRL2 = 009E G
|
||||
_AUTOPTRSETUP = 00AF G
|
||||
_B = 00F0 G
|
||||
_BPADDRH = E606 G
|
||||
_BPADDRL = E607 G
|
||||
_BREAKPT = E605 G
|
||||
_CKCON = 008E G
|
||||
_CLRERRCNT = E665 G
|
||||
_CPUCS = E600 G
|
||||
_CP_RL2 = 00C8 G
|
||||
_CT1 = E6FB G
|
||||
_CT2 = E6FC G
|
||||
_CT3 = E6FD G
|
||||
_CT4 = E6FE G
|
||||
_CY = 00D7 G
|
||||
_C_T2 = 00C9 G
|
||||
_D0 = 00B0 G
|
||||
_D1 = 00B1 G
|
||||
_D2 = 00B2 G
|
||||
_D3 = 00B3 G
|
||||
_D4 = 00B4 G
|
||||
_D5 = 00B5 G
|
||||
_D6 = 00B6 G
|
||||
_D7 = 00B7 G
|
||||
_DBUG = E6F8 G
|
||||
_DPH = 0083 G
|
||||
_DPH1 = 0085 G
|
||||
_DPL = 0082 G
|
||||
_DPL1 = 0084 G
|
||||
_DPS = 0086 G
|
||||
_EA = 00AF G
|
||||
_EI2C = 00E9 G
|
||||
_EICON = 00D8 G
|
||||
_EIE = 00E8 G
|
||||
_EIEX4 = 00EA G
|
||||
_EIEX5 = 00EB G
|
||||
_EIEX6 = 00EC G
|
||||
_EIP = 00F8 G
|
||||
_EIPX4 = 00FA G
|
||||
_EIPX5 = 00FB G
|
||||
_EIPX6 = 00FC G
|
||||
_EIUSB = 00E8 G
|
||||
_EP01STAT = 00BA G
|
||||
_EP0BCH = E68A G
|
||||
_EP0BCL = E68B G
|
||||
_EP0BUF = E740 G
|
||||
_EP0CS = E6A0 G
|
||||
_EP1INBC = E68F G
|
||||
_EP1INBUF = E7C0 G
|
||||
_EP1INCFG = E611 G
|
||||
_EP1INCS = E6A2 G
|
||||
_EP1OUTBC = E68D G
|
||||
_EP1OUTBUF = E780 G
|
||||
_EP1OUTCFG = E610 G
|
||||
_EP1OUTCS = E6A1 G
|
||||
_EP2468STAT = 00AA G
|
||||
_EP24FIFOFLGS = 00AB G
|
||||
_EP2AUTOINLENH = E620 G
|
||||
_EP2AUTOINLENL = E621 G
|
||||
_EP2BCH = E690 G
|
||||
_EP2BCL = E691 G
|
||||
_EP2CFG = E612 G
|
||||
_EP2CS = E6A3 G
|
||||
_EP2FIFOBCH = E6AB G
|
||||
_EP2FIFOBCL = E6AC G
|
||||
_EP2FIFOBUF = F000 G
|
||||
_EP2FIFOCFG = E618 G
|
||||
_EP2FIFOFLGS = E6A7 G
|
||||
_EP2FIFOIE = E650 G
|
||||
_EP2FIFOIRQ = E651 G
|
||||
_EP2FIFOPFH = E630 G
|
||||
_EP2FIFOPFL = E631 G
|
||||
_EP2GPIFFLGSEL = E6D2 G
|
||||
_EP2GPIFPFSTOP = E6D3 G
|
||||
_EP2GPIFTRIG = E6D4 G
|
||||
_EP2ISOINPKTS = E640 G
|
||||
_EP4AUTOINLENH = E622 G
|
||||
_EP4AUTOINLENL = E623 G
|
||||
_EP4BCH = E694 G
|
||||
_EP4BCL = E695 G
|
||||
_EP4CFG = E613 G
|
||||
_EP4CS = E6A4 G
|
||||
_EP4FIFOBCH = E6AD G
|
||||
_EP4FIFOBCL = E6AE G
|
||||
_EP4FIFOBUF = F400 G
|
||||
_EP4FIFOCFG = E619 G
|
||||
_EP4FIFOFLGS = E6A8 G
|
||||
_EP4FIFOIE = E652 G
|
||||
_EP4FIFOIRQ = E653 G
|
||||
_EP4FIFOPFH = E632 G
|
||||
_EP4FIFOPFL = E633 G
|
||||
_EP4GPIFFLGSEL = E6DA G
|
||||
_EP4GPIFPFSTOP = E6DB G
|
||||
_EP4GPIFTRIG = E6DC G
|
||||
_EP4ISOINPKTS = E641 G
|
||||
_EP68FIFOFLGS = 00AC G
|
||||
_EP6AUTOINLENH = E624 G
|
||||
_EP6AUTOINLENL = E625 G
|
||||
_EP6BCH = E698 G
|
||||
_EP6BCL = E699 G
|
||||
_EP6CFG = E614 G
|
||||
_EP6CS = E6A5 G
|
||||
_EP6FIFOBCH = E6AF G
|
||||
_EP6FIFOBCL = E6B0 G
|
||||
_EP6FIFOBUF = F800 G
|
||||
_EP6FIFOCFG = E61A G
|
||||
_EP6FIFOFLGS = E6A9 G
|
||||
_EP6FIFOIE = E654 G
|
||||
_EP6FIFOIRQ = E655 G
|
||||
_EP6FIFOPFH = E634 G
|
||||
_EP6FIFOPFL = E635 G
|
||||
_EP6GPIFFLGSEL = E6E2 G
|
||||
_EP6GPIFPFSTOP = E6E3 G
|
||||
_EP6GPIFTRIG = E6E4 G
|
||||
_EP6ISOINPKTS = E642 G
|
||||
_EP8AUTOINLENH = E626 G
|
||||
_EP8AUTOINLENL = E627 G
|
||||
_EP8BCH = E69C G
|
||||
_EP8BCL = E69D G
|
||||
_EP8CFG = E615 G
|
||||
_EP8CS = E6A6 G
|
||||
_EP8FIFOBCH = E6B1 G
|
||||
_EP8FIFOBCL = E6B2 G
|
||||
_EP8FIFOBUF = FC00 G
|
||||
_EP8FIFOCFG = E61B G
|
||||
_EP8FIFOFLGS = E6AA G
|
||||
_EP8FIFOIE = E656 G
|
||||
_EP8FIFOIRQ = E657 G
|
||||
_EP8FIFOPFH = E636 G
|
||||
_EP8FIFOPFL = E637 G
|
||||
_EP8GPIFFLGSEL = E6EA G
|
||||
_EP8GPIFPFSTOP = E6EB G
|
||||
_EP8GPIFTRIG = E6EC G
|
||||
_EP8ISOINPKTS = E643 G
|
||||
_EPIE = E65E G
|
||||
_EPIRQ = E65F G
|
||||
_ERESI = 00DD G
|
||||
_ERRCNTLIM = E664 G
|
||||
_ES0 = 00AC G
|
||||
_ES1 = 00AE G
|
||||
_ET0 = 00A9 G
|
||||
_ET1 = 00AB G
|
||||
_ET2 = 00AD G
|
||||
_EX0 = 00A8 G
|
||||
_EX1 = 00AA G
|
||||
_EXEN2 = 00CB G
|
||||
_EXF2 = 00CE G
|
||||
_EXIF = 0091 G
|
||||
_F0 = 00D5 G
|
||||
_FIFOPINPOLAR = E609 G
|
||||
_FIFORESET = E604 G
|
||||
_FL = 00D1 G
|
||||
_FLOWEQ0CTL = E6C8 G
|
||||
_FLOWEQ1CTL = E6C9 G
|
||||
_FLOWHOLDOFF = E6CA G
|
||||
_FLOWLOGIC = E6C7 G
|
||||
_FLOWSTATE = E6C6 G
|
||||
_FLOWSTB = E6CB G
|
||||
_FLOWSTBEDGE = E6CC G
|
||||
_FLOWSTBHPERIOD = E6CD G
|
||||
_FNADDR = E687 G
|
||||
_GPIFABORT = E6F5 G
|
||||
_GPIFADRH = E6C4 G
|
||||
_GPIFADRL = E6C5 G
|
||||
_GPIFCTLCFG = E6C3 G
|
||||
_GPIFHOLDAMOUNT = E60C G
|
||||
_GPIFIDLECS = E6C1 G
|
||||
_GPIFIDLECTL = E6C2 G
|
||||
_GPIFIE = E660 G
|
||||
_GPIFIRQ = E661 G
|
||||
_GPIFREADYCFG = E6F3 G
|
||||
_GPIFREADYSTAT = E6F4 G
|
||||
_GPIFSGLDATH = 00BD G
|
||||
_GPIFSGLDATLNOX = 00BF G
|
||||
_GPIFSGLDATLX = 00BE G
|
||||
_GPIFTCB0 = E6D1 G
|
||||
_GPIFTCB1 = E6D0 G
|
||||
_GPIFTCB2 = E6CF G
|
||||
_GPIFTCB3 = E6CE G
|
||||
_GPIFTRIG = 00BB G
|
||||
_GPIFWFSELECT = E6C0 G
|
||||
_GPIF_WAVE_DATA = E400 G
|
||||
_I2CS = E678 G
|
||||
_I2CTL = E67A G
|
||||
_I2DAT = E679 G
|
||||
_IBNIE = E658 G
|
||||
_IBNIRQ = E659 G
|
||||
_IE = 00A8 G
|
||||
_IE0 = 0089 G
|
||||
_IE1 = 008B G
|
||||
_IFCONFIG = E601 G
|
||||
_INPKTEND = E648 G
|
||||
_INT2CLR = 00A1 G
|
||||
_INT2IVEC = E666 G
|
||||
_INT4CLR = 00A2 G
|
||||
_INT4IVEC = E667 G
|
||||
_INT6 = 00DB G
|
||||
_INTSETUP = E668 G
|
||||
_IOA = 0080 G
|
||||
_IOB = 0090 G
|
||||
_IOC = 00A0 G
|
||||
_IOD = 00B0 G
|
||||
_IOE = 00B1 G
|
||||
_IP = 00B8 G
|
||||
_IT0 = 0088 G
|
||||
_IT1 = 008A G
|
||||
_MICROFRAME = E686 G
|
||||
_MPAGE = 0092 G
|
||||
_NAKIE = E65A G
|
||||
_NAKIRQ = E65B G
|
||||
_OEA = 00B2 G
|
||||
_OEB = 00B3 G
|
||||
_OEC = 00B4 G
|
||||
_OED = 00B5 G
|
||||
_OEE = 00B6 G
|
||||
_OUTPKTEND = E649 G
|
||||
_OV = 00D2 G
|
||||
_P = 00D0 G
|
||||
_PCON = 0087 G
|
||||
_PI2C = 00F9 G
|
||||
_PINFLAGSAB = E602 G
|
||||
_PINFLAGSCD = E603 G
|
||||
_PORTACFG = E670 G
|
||||
_PORTCCFG = E671 G
|
||||
_PORTECFG = E672 G
|
||||
_PS0 = 00BC G
|
||||
_PS1 = 00BE G
|
||||
_PSW = 00D0 G
|
||||
_PT0 = 00B9 G
|
||||
_PT1 = 00BB G
|
||||
_PT2 = 00BD G
|
||||
_PUSB = 00F8 G
|
||||
_PX0 = 00B8 G
|
||||
_PX1 = 00BA G
|
||||
_RB8 = 009A G
|
||||
_RB81 = 00C2 G
|
||||
_RCAP2H = 00CB G
|
||||
_RCAP2L = 00CA G
|
||||
_RCLK = 00CD G
|
||||
_REN = 009C G
|
||||
_REN1 = 00C4 G
|
||||
_RESI = 00DC G
|
||||
_RES_WAVEDATA_END = E480 G
|
||||
_REVCTL = E60B G
|
||||
_REVID = E60A G
|
||||
_RI = 0098 G
|
||||
_RI1 = 00C0 G
|
||||
_RS0 = 00D3 G
|
||||
_RS1 = 00D4 G
|
||||
_SBUF0 = 0099 G
|
||||
_SBUF1 = 00C1 G
|
||||
_SCON0 = 0098 G
|
||||
_SCON1 = 00C0 G
|
||||
_SEL = 0086 G
|
||||
_SETUPDAT = E6B8 G
|
||||
_SM0 = 009F G
|
||||
_SM01 = 00C7 G
|
||||
_SM1 = 009E G
|
||||
_SM11 = 00C6 G
|
||||
_SM2 = 009D G
|
||||
_SM21 = 00C5 G
|
||||
_SMOD1 = 00DF G
|
||||
_SP = 0081 G
|
||||
_SUDPTRCTL = E6B5 G
|
||||
_SUDPTRH = E6B3 G
|
||||
_SUDPTRL = E6B4 G
|
||||
_SUSPEND = E681 G
|
||||
_T2CON = 00C8 G
|
||||
_TB8 = 009B G
|
||||
_TB81 = 00C3 G
|
||||
_TCLK = 00CC G
|
||||
_TCON = 0088 G
|
||||
_TESTCFG = E6F9 G
|
||||
_TF0 = 008D G
|
||||
_TF1 = 008F G
|
||||
_TF2 = 00CF G
|
||||
_TH0 = 008C G
|
||||
_TH1 = 008D G
|
||||
_TH2 = 00CD G
|
||||
_TI = 0099 G
|
||||
_TI1 = 00C1 G
|
||||
_TL0 = 008A G
|
||||
_TL1 = 008B G
|
||||
_TL2 = 00CC G
|
||||
_TMOD = 0089 G
|
||||
_TOGCTL = E683 G
|
||||
_TR0 = 008C G
|
||||
_TR1 = 008E G
|
||||
_TR2 = 00CA G
|
||||
_UART230 = E608 G
|
||||
_UDMACRCH = E67D G
|
||||
_UDMACRCL = E67E G
|
||||
_UDMACRCQUAL = E67F G
|
||||
_USBCS = E680 G
|
||||
_USBERRIE = E662 G
|
||||
_USBERRIRQ = E663 G
|
||||
_USBFRAMEH = E684 G
|
||||
_USBFRAMEL = E685 G
|
||||
_USBIE = E65C G
|
||||
_USBIRQ = E65D G
|
||||
_USBTEST = E6FA G
|
||||
_WAKEUPCS = E682 G
|
||||
_XAUTODAT1 = E67B G
|
||||
_XAUTODAT2 = E67C G
|
||||
_XGPIFSGLDATH = E6F0 G
|
||||
_XGPIFSGLDATLNOX = E6F2 G
|
||||
_XGPIFSGLDATLX = E6F1 G
|
||||
__fifo_gpif_autovector **** GX
|
||||
__standard_interrupt_vector **** GX
|
||||
__usb_autovector **** GX
|
||||
14 _hook_fgv 00B4 GR
|
||||
4 _hook_fgv_PARM_2 0000 GR
|
||||
7 _hook_fgv_t_1_1 0002 R
|
||||
14 _hook_sv 0000 GR
|
||||
4 _hook_sv_PARM_2 0000 GR
|
||||
7 _hook_sv_t_1_1 0000 R
|
||||
14 _hook_uv 0063 GR
|
||||
4 _hook_uv_PARM_2 0000 GR
|
||||
7 _hook_uv_t_1_1 0001 R
|
||||
14 _setup_autovectors 010A GR
|
||||
a 00D6
|
||||
ac 00D6
|
||||
acc 00E0
|
||||
acc.0 00E0
|
||||
acc.1 00E1
|
||||
acc.2 00E2
|
||||
acc.3 00E3
|
||||
acc.4 00E4
|
||||
acc.5 00E5
|
||||
acc.6 00E6
|
||||
acc.7 00E7
|
||||
ar0 = 0000
|
||||
ar1 = 0001
|
||||
ar2 = 0002
|
||||
ar3 = 0003
|
||||
ar4 = 0004
|
||||
ar5 = 0005
|
||||
ar6 = 0006
|
||||
ar7 = 0007
|
||||
b 00F0
|
||||
b.0 00F0
|
||||
b.1 00F1
|
||||
b.2 00F2
|
||||
b.3 00F3
|
||||
b.4 00F4
|
||||
b.5 00F5
|
||||
b.6 00F6
|
||||
b.7 00F7
|
||||
cprl2 00C8
|
||||
ct2 00C9
|
||||
cy 00D7
|
||||
dph 0083
|
||||
dpl 0082
|
||||
ea 00AF
|
||||
es 00AC
|
||||
et0 00A9
|
||||
et1 00AB
|
||||
et2 00AD
|
||||
ex0 00A8
|
||||
ex1 00AA
|
||||
exen2 00CB
|
||||
exf2 00CE
|
||||
f0 00D5
|
||||
ie 00A8
|
||||
ie.0 00A8
|
||||
ie.1 00A9
|
||||
ie.2 00AA
|
||||
ie.3 00AB
|
||||
ie.4 00AC
|
||||
ie.5 00AD
|
||||
ie.7 00AF
|
||||
ie0 0089
|
||||
ie1 008B
|
||||
int0 00B2
|
||||
int1 00B3
|
||||
ip 00B8
|
||||
ip.0 00B8
|
||||
ip.1 00B9
|
||||
ip.2 00BA
|
||||
ip.3 00BB
|
||||
ip.4 00BC
|
||||
ip.5 00BD
|
||||
it0 0088
|
||||
it1 008A
|
||||
ov 00D2
|
||||
p 00D0
|
||||
p0 0080
|
||||
p0.0 0080
|
||||
p0.1 0081
|
||||
p0.2 0082
|
||||
p0.3 0083
|
||||
p0.4 0084
|
||||
p0.5 0085
|
||||
p0.6 0086
|
||||
p0.7 0087
|
||||
p1 0090
|
||||
p1.0 0090
|
||||
p1.1 0091
|
||||
p1.2 0092
|
||||
p1.3 0093
|
||||
p1.4 0094
|
||||
p1.5 0095
|
||||
p1.6 0096
|
||||
p1.7 0097
|
||||
p2 00A0
|
||||
p2.0 00A0
|
||||
p2.1 00A1
|
||||
p2.2 00A2
|
||||
p2.3 00A3
|
||||
p2.4 00A4
|
||||
p2.5 00A5
|
||||
p2.6 00A6
|
||||
p2.7 00A7
|
||||
p3 00B0
|
||||
p3.0 00B0
|
||||
p3.1 00B1
|
||||
p3.2 00B2
|
||||
p3.3 00B3
|
||||
p3.4 00B4
|
||||
p3.5 00B5
|
||||
p3.6 00B6
|
||||
p3.7 00B7
|
||||
pcon 0087
|
||||
ps 00BC
|
||||
psw 00D0
|
||||
psw.0 00D0
|
||||
psw.1 00D1
|
||||
psw.2 00D2
|
||||
psw.3 00D3
|
||||
psw.4 00D4
|
||||
psw.5 00D5
|
||||
psw.6 00D6
|
||||
psw.7 00D7
|
||||
pt0 00B9
|
||||
pt1 00BB
|
||||
pt2 00BD
|
||||
px0 00B8
|
||||
px1 00BA
|
||||
rb8 009A
|
||||
rcap2h 00CB
|
||||
rcap2l 00CA
|
||||
rclk 00CD
|
||||
ren 009C
|
||||
ri 0098
|
||||
rs0 00D3
|
||||
rs1 00D4
|
||||
rxd 00B0
|
||||
sbuf 0099
|
||||
scon 0098
|
||||
scon.0 0098
|
||||
scon.1 0099
|
||||
scon.2 009A
|
||||
scon.3 009B
|
||||
scon.4 009C
|
||||
scon.5 009D
|
||||
scon.6 009E
|
||||
scon.7 009F
|
||||
sm0 009F
|
||||
sm1 009E
|
||||
sm2 009D
|
||||
sp 0081
|
||||
t2con 00C8
|
||||
t2con.0 00C8
|
||||
t2con.1 00C9
|
||||
t2con.2 00CA
|
||||
t2con.3 00CB
|
||||
t2con.4 00CC
|
||||
t2con.5 00CD
|
||||
t2con.6 00CE
|
||||
t2con.7 00CF
|
||||
tb8 009B
|
||||
tclk 00CC
|
||||
tcon 0088
|
||||
tcon.0 0088
|
||||
tcon.1 0089
|
||||
tcon.2 008A
|
||||
tcon.3 008B
|
||||
tcon.4 008C
|
||||
tcon.5 008D
|
||||
tcon.6 008E
|
||||
tcon.7 008F
|
||||
tf0 008D
|
||||
tf1 008F
|
||||
tf2 00CF
|
||||
th0 008C
|
||||
th1 008D
|
||||
th2 00CD
|
||||
ti 0099
|
||||
tl0 008A
|
||||
tl1 008B
|
||||
tl2 00CC
|
||||
tmod 0089
|
||||
tr0 008C
|
||||
tr1 008E
|
||||
tr2 00CA
|
||||
txd 00B1
|
||||
|
||||
ASxxxx Assembler V01.70 + NoICE + SDCC mods + Flat24 Feb-1999 (Intel 8051), page 2.
|
||||
|
||||
Area Table
|
||||
|
||||
0 _CODE size 0 flags 0
|
||||
1 RSEG size 0 flags 0
|
||||
2 REG_BANK_0 size 8 flags 4
|
||||
3 DSEG size 0 flags 0
|
||||
4 OSEG size 2 flags 4
|
||||
5 ISEG size 0 flags 0
|
||||
6 IABS size 0 flags 8
|
||||
7 BSEG size 3 flags 80
|
||||
8 PSEG size 0 flags 50
|
||||
9 XSEG size 0 flags 40
|
||||
A XABS size 0 flags 48
|
||||
B HOME size 0 flags 20
|
||||
C GSINIT0 size 0 flags 20
|
||||
D GSINIT1 size 0 flags 20
|
||||
E GSINIT2 size 0 flags 20
|
||||
F GSINIT3 size 0 flags 20
|
||||
10 GSINIT4 size 0 flags 20
|
||||
11 GSINIT5 size 0 flags 20
|
||||
12 GSINIT size 0 flags 20
|
||||
13 GSFINAL size 0 flags 20
|
||||
14 CSEG size 1B2 flags 20
|
||||
15 CONST size 0 flags 20
|
||||
16 CABS size 0 flags 28
|
||||
5
firmware/GN3S_v2/lib/libfx2.lib
Normal file
5
firmware/GN3S_v2/lib/libfx2.lib
Normal file
@@ -0,0 +1,5 @@
|
||||
delay
|
||||
fx2utils
|
||||
isr
|
||||
timer
|
||||
usb_common
|
||||
770
firmware/GN3S_v2/lib/timer.asm
Normal file
770
firmware/GN3S_v2/lib/timer.asm
Normal file
@@ -0,0 +1,770 @@
|
||||
;--------------------------------------------------------
|
||||
; File Created by SDCC : free open source ANSI-C Compiler
|
||||
; Version 2.9.0 #5416 (Feb 3 2010) (UNIX)
|
||||
; This file was generated Mon Jul 30 11:40:53 2012
|
||||
;--------------------------------------------------------
|
||||
.module timer
|
||||
.optsdcc -mmcs51 --model-small
|
||||
|
||||
;--------------------------------------------------------
|
||||
; Public variables in this module
|
||||
;--------------------------------------------------------
|
||||
.globl _EIPX6
|
||||
.globl _EIPX5
|
||||
.globl _EIPX4
|
||||
.globl _PI2C
|
||||
.globl _PUSB
|
||||
.globl _EIEX6
|
||||
.globl _EIEX5
|
||||
.globl _EIEX4
|
||||
.globl _EI2C
|
||||
.globl _EIUSB
|
||||
.globl _SMOD1
|
||||
.globl _ERESI
|
||||
.globl _RESI
|
||||
.globl _INT6
|
||||
.globl _CY
|
||||
.globl _AC
|
||||
.globl _F0
|
||||
.globl _RS1
|
||||
.globl _RS0
|
||||
.globl _OV
|
||||
.globl _FL
|
||||
.globl _P
|
||||
.globl _TF2
|
||||
.globl _EXF2
|
||||
.globl _RCLK
|
||||
.globl _TCLK
|
||||
.globl _EXEN2
|
||||
.globl _TR2
|
||||
.globl _C_T2
|
||||
.globl _CP_RL2
|
||||
.globl _SM01
|
||||
.globl _SM11
|
||||
.globl _SM21
|
||||
.globl _REN1
|
||||
.globl _TB81
|
||||
.globl _RB81
|
||||
.globl _TI1
|
||||
.globl _RI1
|
||||
.globl _PS1
|
||||
.globl _PT2
|
||||
.globl _PS0
|
||||
.globl _PT1
|
||||
.globl _PX1
|
||||
.globl _PT0
|
||||
.globl _PX0
|
||||
.globl _D7
|
||||
.globl _D6
|
||||
.globl _D5
|
||||
.globl _D4
|
||||
.globl _D3
|
||||
.globl _D2
|
||||
.globl _D1
|
||||
.globl _D0
|
||||
.globl _EA
|
||||
.globl _ES1
|
||||
.globl _ET2
|
||||
.globl _ES0
|
||||
.globl _ET1
|
||||
.globl _EX1
|
||||
.globl _ET0
|
||||
.globl _EX0
|
||||
.globl _SM0
|
||||
.globl _SM1
|
||||
.globl _SM2
|
||||
.globl _REN
|
||||
.globl _TB8
|
||||
.globl _RB8
|
||||
.globl _TI
|
||||
.globl _RI
|
||||
.globl _TF1
|
||||
.globl _TR1
|
||||
.globl _TF0
|
||||
.globl _TR0
|
||||
.globl _IE1
|
||||
.globl _IT1
|
||||
.globl _IE0
|
||||
.globl _IT0
|
||||
.globl _SEL
|
||||
.globl _A7
|
||||
.globl _A6
|
||||
.globl _A5
|
||||
.globl _A4
|
||||
.globl _A3
|
||||
.globl _A2
|
||||
.globl _A1
|
||||
.globl _A0
|
||||
.globl _EIP
|
||||
.globl _B
|
||||
.globl _EIE
|
||||
.globl _ACC
|
||||
.globl _EICON
|
||||
.globl _PSW
|
||||
.globl _TH2
|
||||
.globl _TL2
|
||||
.globl _RCAP2H
|
||||
.globl _RCAP2L
|
||||
.globl _T2CON
|
||||
.globl _SBUF1
|
||||
.globl _SCON1
|
||||
.globl _GPIFSGLDATLNOX
|
||||
.globl _GPIFSGLDATLX
|
||||
.globl _GPIFSGLDATH
|
||||
.globl _GPIFTRIG
|
||||
.globl _EP01STAT
|
||||
.globl _IP
|
||||
.globl _OEE
|
||||
.globl _OED
|
||||
.globl _OEC
|
||||
.globl _OEB
|
||||
.globl _OEA
|
||||
.globl _IOE
|
||||
.globl _IOD
|
||||
.globl _AUTOPTRSETUP
|
||||
.globl _EP68FIFOFLGS
|
||||
.globl _EP24FIFOFLGS
|
||||
.globl _EP2468STAT
|
||||
.globl _IE
|
||||
.globl _INT4CLR
|
||||
.globl _INT2CLR
|
||||
.globl _IOC
|
||||
.globl _AUTODAT2
|
||||
.globl _AUTOPTRL2
|
||||
.globl _AUTOPTRH2
|
||||
.globl _AUTODAT1
|
||||
.globl _APTR1L
|
||||
.globl _APTR1H
|
||||
.globl _SBUF0
|
||||
.globl _SCON0
|
||||
.globl _MPAGE
|
||||
.globl _EXIF
|
||||
.globl _IOB
|
||||
.globl _CKCON
|
||||
.globl _TH1
|
||||
.globl _TH0
|
||||
.globl _TL1
|
||||
.globl _TL0
|
||||
.globl _TMOD
|
||||
.globl _TCON
|
||||
.globl _PCON
|
||||
.globl _DPS
|
||||
.globl _DPH1
|
||||
.globl _DPL1
|
||||
.globl _DPH
|
||||
.globl _DPL
|
||||
.globl _SP
|
||||
.globl _IOA
|
||||
.globl _EP8FIFOBUF
|
||||
.globl _EP6FIFOBUF
|
||||
.globl _EP4FIFOBUF
|
||||
.globl _EP2FIFOBUF
|
||||
.globl _EP1INBUF
|
||||
.globl _EP1OUTBUF
|
||||
.globl _EP0BUF
|
||||
.globl _CT4
|
||||
.globl _CT3
|
||||
.globl _CT2
|
||||
.globl _CT1
|
||||
.globl _USBTEST
|
||||
.globl _TESTCFG
|
||||
.globl _DBUG
|
||||
.globl _UDMACRCQUAL
|
||||
.globl _UDMACRCL
|
||||
.globl _UDMACRCH
|
||||
.globl _GPIFHOLDAMOUNT
|
||||
.globl _FLOWSTBHPERIOD
|
||||
.globl _FLOWSTBEDGE
|
||||
.globl _FLOWSTB
|
||||
.globl _FLOWHOLDOFF
|
||||
.globl _FLOWEQ1CTL
|
||||
.globl _FLOWEQ0CTL
|
||||
.globl _FLOWLOGIC
|
||||
.globl _FLOWSTATE
|
||||
.globl _GPIFABORT
|
||||
.globl _GPIFREADYSTAT
|
||||
.globl _GPIFREADYCFG
|
||||
.globl _XGPIFSGLDATLNOX
|
||||
.globl _XGPIFSGLDATLX
|
||||
.globl _XGPIFSGLDATH
|
||||
.globl _EP8GPIFTRIG
|
||||
.globl _EP8GPIFPFSTOP
|
||||
.globl _EP8GPIFFLGSEL
|
||||
.globl _EP6GPIFTRIG
|
||||
.globl _EP6GPIFPFSTOP
|
||||
.globl _EP6GPIFFLGSEL
|
||||
.globl _EP4GPIFTRIG
|
||||
.globl _EP4GPIFPFSTOP
|
||||
.globl _EP4GPIFFLGSEL
|
||||
.globl _EP2GPIFTRIG
|
||||
.globl _EP2GPIFPFSTOP
|
||||
.globl _EP2GPIFFLGSEL
|
||||
.globl _GPIFTCB0
|
||||
.globl _GPIFTCB1
|
||||
.globl _GPIFTCB2
|
||||
.globl _GPIFTCB3
|
||||
.globl _GPIFADRL
|
||||
.globl _GPIFADRH
|
||||
.globl _GPIFCTLCFG
|
||||
.globl _GPIFIDLECTL
|
||||
.globl _GPIFIDLECS
|
||||
.globl _GPIFWFSELECT
|
||||
.globl _SETUPDAT
|
||||
.globl _SUDPTRCTL
|
||||
.globl _SUDPTRL
|
||||
.globl _SUDPTRH
|
||||
.globl _EP8FIFOBCL
|
||||
.globl _EP8FIFOBCH
|
||||
.globl _EP6FIFOBCL
|
||||
.globl _EP6FIFOBCH
|
||||
.globl _EP4FIFOBCL
|
||||
.globl _EP4FIFOBCH
|
||||
.globl _EP2FIFOBCL
|
||||
.globl _EP2FIFOBCH
|
||||
.globl _EP8FIFOFLGS
|
||||
.globl _EP6FIFOFLGS
|
||||
.globl _EP4FIFOFLGS
|
||||
.globl _EP2FIFOFLGS
|
||||
.globl _EP8CS
|
||||
.globl _EP6CS
|
||||
.globl _EP4CS
|
||||
.globl _EP2CS
|
||||
.globl _EP1INCS
|
||||
.globl _EP1OUTCS
|
||||
.globl _EP0CS
|
||||
.globl _EP8BCL
|
||||
.globl _EP8BCH
|
||||
.globl _EP6BCL
|
||||
.globl _EP6BCH
|
||||
.globl _EP4BCL
|
||||
.globl _EP4BCH
|
||||
.globl _EP2BCL
|
||||
.globl _EP2BCH
|
||||
.globl _EP1INBC
|
||||
.globl _EP1OUTBC
|
||||
.globl _EP0BCL
|
||||
.globl _EP0BCH
|
||||
.globl _FNADDR
|
||||
.globl _MICROFRAME
|
||||
.globl _USBFRAMEL
|
||||
.globl _USBFRAMEH
|
||||
.globl _TOGCTL
|
||||
.globl _WAKEUPCS
|
||||
.globl _SUSPEND
|
||||
.globl _USBCS
|
||||
.globl _XAUTODAT2
|
||||
.globl _XAUTODAT1
|
||||
.globl _I2CTL
|
||||
.globl _I2DAT
|
||||
.globl _I2CS
|
||||
.globl _PORTECFG
|
||||
.globl _PORTCCFG
|
||||
.globl _PORTACFG
|
||||
.globl _INTSETUP
|
||||
.globl _INT4IVEC
|
||||
.globl _INT2IVEC
|
||||
.globl _CLRERRCNT
|
||||
.globl _ERRCNTLIM
|
||||
.globl _USBERRIRQ
|
||||
.globl _USBERRIE
|
||||
.globl _GPIFIRQ
|
||||
.globl _GPIFIE
|
||||
.globl _EPIRQ
|
||||
.globl _EPIE
|
||||
.globl _USBIRQ
|
||||
.globl _USBIE
|
||||
.globl _NAKIRQ
|
||||
.globl _NAKIE
|
||||
.globl _IBNIRQ
|
||||
.globl _IBNIE
|
||||
.globl _EP8FIFOIRQ
|
||||
.globl _EP8FIFOIE
|
||||
.globl _EP6FIFOIRQ
|
||||
.globl _EP6FIFOIE
|
||||
.globl _EP4FIFOIRQ
|
||||
.globl _EP4FIFOIE
|
||||
.globl _EP2FIFOIRQ
|
||||
.globl _EP2FIFOIE
|
||||
.globl _OUTPKTEND
|
||||
.globl _INPKTEND
|
||||
.globl _EP8ISOINPKTS
|
||||
.globl _EP6ISOINPKTS
|
||||
.globl _EP4ISOINPKTS
|
||||
.globl _EP2ISOINPKTS
|
||||
.globl _EP8FIFOPFL
|
||||
.globl _EP8FIFOPFH
|
||||
.globl _EP6FIFOPFL
|
||||
.globl _EP6FIFOPFH
|
||||
.globl _EP4FIFOPFL
|
||||
.globl _EP4FIFOPFH
|
||||
.globl _EP2FIFOPFL
|
||||
.globl _EP2FIFOPFH
|
||||
.globl _EP8AUTOINLENL
|
||||
.globl _EP8AUTOINLENH
|
||||
.globl _EP6AUTOINLENL
|
||||
.globl _EP6AUTOINLENH
|
||||
.globl _EP4AUTOINLENL
|
||||
.globl _EP4AUTOINLENH
|
||||
.globl _EP2AUTOINLENL
|
||||
.globl _EP2AUTOINLENH
|
||||
.globl _EP8FIFOCFG
|
||||
.globl _EP6FIFOCFG
|
||||
.globl _EP4FIFOCFG
|
||||
.globl _EP2FIFOCFG
|
||||
.globl _EP8CFG
|
||||
.globl _EP6CFG
|
||||
.globl _EP4CFG
|
||||
.globl _EP2CFG
|
||||
.globl _EP1INCFG
|
||||
.globl _EP1OUTCFG
|
||||
.globl _REVCTL
|
||||
.globl _REVID
|
||||
.globl _FIFOPINPOLAR
|
||||
.globl _UART230
|
||||
.globl _BPADDRL
|
||||
.globl _BPADDRH
|
||||
.globl _BREAKPT
|
||||
.globl _FIFORESET
|
||||
.globl _PINFLAGSCD
|
||||
.globl _PINFLAGSAB
|
||||
.globl _IFCONFIG
|
||||
.globl _CPUCS
|
||||
.globl _RES_WAVEDATA_END
|
||||
.globl _GPIF_WAVE_DATA
|
||||
.globl _hook_timer_tick
|
||||
;--------------------------------------------------------
|
||||
; special function registers
|
||||
;--------------------------------------------------------
|
||||
.area RSEG (DATA)
|
||||
_IOA = 0x0080
|
||||
_SP = 0x0081
|
||||
_DPL = 0x0082
|
||||
_DPH = 0x0083
|
||||
_DPL1 = 0x0084
|
||||
_DPH1 = 0x0085
|
||||
_DPS = 0x0086
|
||||
_PCON = 0x0087
|
||||
_TCON = 0x0088
|
||||
_TMOD = 0x0089
|
||||
_TL0 = 0x008a
|
||||
_TL1 = 0x008b
|
||||
_TH0 = 0x008c
|
||||
_TH1 = 0x008d
|
||||
_CKCON = 0x008e
|
||||
_IOB = 0x0090
|
||||
_EXIF = 0x0091
|
||||
_MPAGE = 0x0092
|
||||
_SCON0 = 0x0098
|
||||
_SBUF0 = 0x0099
|
||||
_APTR1H = 0x009a
|
||||
_APTR1L = 0x009b
|
||||
_AUTODAT1 = 0x009c
|
||||
_AUTOPTRH2 = 0x009d
|
||||
_AUTOPTRL2 = 0x009e
|
||||
_AUTODAT2 = 0x009f
|
||||
_IOC = 0x00a0
|
||||
_INT2CLR = 0x00a1
|
||||
_INT4CLR = 0x00a2
|
||||
_IE = 0x00a8
|
||||
_EP2468STAT = 0x00aa
|
||||
_EP24FIFOFLGS = 0x00ab
|
||||
_EP68FIFOFLGS = 0x00ac
|
||||
_AUTOPTRSETUP = 0x00af
|
||||
_IOD = 0x00b0
|
||||
_IOE = 0x00b1
|
||||
_OEA = 0x00b2
|
||||
_OEB = 0x00b3
|
||||
_OEC = 0x00b4
|
||||
_OED = 0x00b5
|
||||
_OEE = 0x00b6
|
||||
_IP = 0x00b8
|
||||
_EP01STAT = 0x00ba
|
||||
_GPIFTRIG = 0x00bb
|
||||
_GPIFSGLDATH = 0x00bd
|
||||
_GPIFSGLDATLX = 0x00be
|
||||
_GPIFSGLDATLNOX = 0x00bf
|
||||
_SCON1 = 0x00c0
|
||||
_SBUF1 = 0x00c1
|
||||
_T2CON = 0x00c8
|
||||
_RCAP2L = 0x00ca
|
||||
_RCAP2H = 0x00cb
|
||||
_TL2 = 0x00cc
|
||||
_TH2 = 0x00cd
|
||||
_PSW = 0x00d0
|
||||
_EICON = 0x00d8
|
||||
_ACC = 0x00e0
|
||||
_EIE = 0x00e8
|
||||
_B = 0x00f0
|
||||
_EIP = 0x00f8
|
||||
;--------------------------------------------------------
|
||||
; special function bits
|
||||
;--------------------------------------------------------
|
||||
.area RSEG (DATA)
|
||||
_A0 = 0x0080
|
||||
_A1 = 0x0081
|
||||
_A2 = 0x0082
|
||||
_A3 = 0x0083
|
||||
_A4 = 0x0084
|
||||
_A5 = 0x0085
|
||||
_A6 = 0x0086
|
||||
_A7 = 0x0087
|
||||
_SEL = 0x0086
|
||||
_IT0 = 0x0088
|
||||
_IE0 = 0x0089
|
||||
_IT1 = 0x008a
|
||||
_IE1 = 0x008b
|
||||
_TR0 = 0x008c
|
||||
_TF0 = 0x008d
|
||||
_TR1 = 0x008e
|
||||
_TF1 = 0x008f
|
||||
_RI = 0x0098
|
||||
_TI = 0x0099
|
||||
_RB8 = 0x009a
|
||||
_TB8 = 0x009b
|
||||
_REN = 0x009c
|
||||
_SM2 = 0x009d
|
||||
_SM1 = 0x009e
|
||||
_SM0 = 0x009f
|
||||
_EX0 = 0x00a8
|
||||
_ET0 = 0x00a9
|
||||
_EX1 = 0x00aa
|
||||
_ET1 = 0x00ab
|
||||
_ES0 = 0x00ac
|
||||
_ET2 = 0x00ad
|
||||
_ES1 = 0x00ae
|
||||
_EA = 0x00af
|
||||
_D0 = 0x00b0
|
||||
_D1 = 0x00b1
|
||||
_D2 = 0x00b2
|
||||
_D3 = 0x00b3
|
||||
_D4 = 0x00b4
|
||||
_D5 = 0x00b5
|
||||
_D6 = 0x00b6
|
||||
_D7 = 0x00b7
|
||||
_PX0 = 0x00b8
|
||||
_PT0 = 0x00b9
|
||||
_PX1 = 0x00ba
|
||||
_PT1 = 0x00bb
|
||||
_PS0 = 0x00bc
|
||||
_PT2 = 0x00bd
|
||||
_PS1 = 0x00be
|
||||
_RI1 = 0x00c0
|
||||
_TI1 = 0x00c1
|
||||
_RB81 = 0x00c2
|
||||
_TB81 = 0x00c3
|
||||
_REN1 = 0x00c4
|
||||
_SM21 = 0x00c5
|
||||
_SM11 = 0x00c6
|
||||
_SM01 = 0x00c7
|
||||
_CP_RL2 = 0x00c8
|
||||
_C_T2 = 0x00c9
|
||||
_TR2 = 0x00ca
|
||||
_EXEN2 = 0x00cb
|
||||
_TCLK = 0x00cc
|
||||
_RCLK = 0x00cd
|
||||
_EXF2 = 0x00ce
|
||||
_TF2 = 0x00cf
|
||||
_P = 0x00d0
|
||||
_FL = 0x00d1
|
||||
_OV = 0x00d2
|
||||
_RS0 = 0x00d3
|
||||
_RS1 = 0x00d4
|
||||
_F0 = 0x00d5
|
||||
_AC = 0x00d6
|
||||
_CY = 0x00d7
|
||||
_INT6 = 0x00db
|
||||
_RESI = 0x00dc
|
||||
_ERESI = 0x00dd
|
||||
_SMOD1 = 0x00df
|
||||
_EIUSB = 0x00e8
|
||||
_EI2C = 0x00e9
|
||||
_EIEX4 = 0x00ea
|
||||
_EIEX5 = 0x00eb
|
||||
_EIEX6 = 0x00ec
|
||||
_PUSB = 0x00f8
|
||||
_PI2C = 0x00f9
|
||||
_EIPX4 = 0x00fa
|
||||
_EIPX5 = 0x00fb
|
||||
_EIPX6 = 0x00fc
|
||||
;--------------------------------------------------------
|
||||
; overlayable register banks
|
||||
;--------------------------------------------------------
|
||||
.area REG_BANK_0 (REL,OVR,DATA)
|
||||
.ds 8
|
||||
;--------------------------------------------------------
|
||||
; internal ram data
|
||||
;--------------------------------------------------------
|
||||
.area DSEG (DATA)
|
||||
;--------------------------------------------------------
|
||||
; overlayable items in internal ram
|
||||
;--------------------------------------------------------
|
||||
.area OSEG (OVR,DATA)
|
||||
;--------------------------------------------------------
|
||||
; indirectly addressable internal ram data
|
||||
;--------------------------------------------------------
|
||||
.area ISEG (DATA)
|
||||
;--------------------------------------------------------
|
||||
; absolute internal ram data
|
||||
;--------------------------------------------------------
|
||||
.area IABS (ABS,DATA)
|
||||
.area IABS (ABS,DATA)
|
||||
;--------------------------------------------------------
|
||||
; bit data
|
||||
;--------------------------------------------------------
|
||||
.area BSEG (BIT)
|
||||
;--------------------------------------------------------
|
||||
; paged external ram data
|
||||
;--------------------------------------------------------
|
||||
.area PSEG (PAG,XDATA)
|
||||
;--------------------------------------------------------
|
||||
; external ram data
|
||||
;--------------------------------------------------------
|
||||
.area XSEG (XDATA)
|
||||
_GPIF_WAVE_DATA = 0xe400
|
||||
_RES_WAVEDATA_END = 0xe480
|
||||
_CPUCS = 0xe600
|
||||
_IFCONFIG = 0xe601
|
||||
_PINFLAGSAB = 0xe602
|
||||
_PINFLAGSCD = 0xe603
|
||||
_FIFORESET = 0xe604
|
||||
_BREAKPT = 0xe605
|
||||
_BPADDRH = 0xe606
|
||||
_BPADDRL = 0xe607
|
||||
_UART230 = 0xe608
|
||||
_FIFOPINPOLAR = 0xe609
|
||||
_REVID = 0xe60a
|
||||
_REVCTL = 0xe60b
|
||||
_EP1OUTCFG = 0xe610
|
||||
_EP1INCFG = 0xe611
|
||||
_EP2CFG = 0xe612
|
||||
_EP4CFG = 0xe613
|
||||
_EP6CFG = 0xe614
|
||||
_EP8CFG = 0xe615
|
||||
_EP2FIFOCFG = 0xe618
|
||||
_EP4FIFOCFG = 0xe619
|
||||
_EP6FIFOCFG = 0xe61a
|
||||
_EP8FIFOCFG = 0xe61b
|
||||
_EP2AUTOINLENH = 0xe620
|
||||
_EP2AUTOINLENL = 0xe621
|
||||
_EP4AUTOINLENH = 0xe622
|
||||
_EP4AUTOINLENL = 0xe623
|
||||
_EP6AUTOINLENH = 0xe624
|
||||
_EP6AUTOINLENL = 0xe625
|
||||
_EP8AUTOINLENH = 0xe626
|
||||
_EP8AUTOINLENL = 0xe627
|
||||
_EP2FIFOPFH = 0xe630
|
||||
_EP2FIFOPFL = 0xe631
|
||||
_EP4FIFOPFH = 0xe632
|
||||
_EP4FIFOPFL = 0xe633
|
||||
_EP6FIFOPFH = 0xe634
|
||||
_EP6FIFOPFL = 0xe635
|
||||
_EP8FIFOPFH = 0xe636
|
||||
_EP8FIFOPFL = 0xe637
|
||||
_EP2ISOINPKTS = 0xe640
|
||||
_EP4ISOINPKTS = 0xe641
|
||||
_EP6ISOINPKTS = 0xe642
|
||||
_EP8ISOINPKTS = 0xe643
|
||||
_INPKTEND = 0xe648
|
||||
_OUTPKTEND = 0xe649
|
||||
_EP2FIFOIE = 0xe650
|
||||
_EP2FIFOIRQ = 0xe651
|
||||
_EP4FIFOIE = 0xe652
|
||||
_EP4FIFOIRQ = 0xe653
|
||||
_EP6FIFOIE = 0xe654
|
||||
_EP6FIFOIRQ = 0xe655
|
||||
_EP8FIFOIE = 0xe656
|
||||
_EP8FIFOIRQ = 0xe657
|
||||
_IBNIE = 0xe658
|
||||
_IBNIRQ = 0xe659
|
||||
_NAKIE = 0xe65a
|
||||
_NAKIRQ = 0xe65b
|
||||
_USBIE = 0xe65c
|
||||
_USBIRQ = 0xe65d
|
||||
_EPIE = 0xe65e
|
||||
_EPIRQ = 0xe65f
|
||||
_GPIFIE = 0xe660
|
||||
_GPIFIRQ = 0xe661
|
||||
_USBERRIE = 0xe662
|
||||
_USBERRIRQ = 0xe663
|
||||
_ERRCNTLIM = 0xe664
|
||||
_CLRERRCNT = 0xe665
|
||||
_INT2IVEC = 0xe666
|
||||
_INT4IVEC = 0xe667
|
||||
_INTSETUP = 0xe668
|
||||
_PORTACFG = 0xe670
|
||||
_PORTCCFG = 0xe671
|
||||
_PORTECFG = 0xe672
|
||||
_I2CS = 0xe678
|
||||
_I2DAT = 0xe679
|
||||
_I2CTL = 0xe67a
|
||||
_XAUTODAT1 = 0xe67b
|
||||
_XAUTODAT2 = 0xe67c
|
||||
_USBCS = 0xe680
|
||||
_SUSPEND = 0xe681
|
||||
_WAKEUPCS = 0xe682
|
||||
_TOGCTL = 0xe683
|
||||
_USBFRAMEH = 0xe684
|
||||
_USBFRAMEL = 0xe685
|
||||
_MICROFRAME = 0xe686
|
||||
_FNADDR = 0xe687
|
||||
_EP0BCH = 0xe68a
|
||||
_EP0BCL = 0xe68b
|
||||
_EP1OUTBC = 0xe68d
|
||||
_EP1INBC = 0xe68f
|
||||
_EP2BCH = 0xe690
|
||||
_EP2BCL = 0xe691
|
||||
_EP4BCH = 0xe694
|
||||
_EP4BCL = 0xe695
|
||||
_EP6BCH = 0xe698
|
||||
_EP6BCL = 0xe699
|
||||
_EP8BCH = 0xe69c
|
||||
_EP8BCL = 0xe69d
|
||||
_EP0CS = 0xe6a0
|
||||
_EP1OUTCS = 0xe6a1
|
||||
_EP1INCS = 0xe6a2
|
||||
_EP2CS = 0xe6a3
|
||||
_EP4CS = 0xe6a4
|
||||
_EP6CS = 0xe6a5
|
||||
_EP8CS = 0xe6a6
|
||||
_EP2FIFOFLGS = 0xe6a7
|
||||
_EP4FIFOFLGS = 0xe6a8
|
||||
_EP6FIFOFLGS = 0xe6a9
|
||||
_EP8FIFOFLGS = 0xe6aa
|
||||
_EP2FIFOBCH = 0xe6ab
|
||||
_EP2FIFOBCL = 0xe6ac
|
||||
_EP4FIFOBCH = 0xe6ad
|
||||
_EP4FIFOBCL = 0xe6ae
|
||||
_EP6FIFOBCH = 0xe6af
|
||||
_EP6FIFOBCL = 0xe6b0
|
||||
_EP8FIFOBCH = 0xe6b1
|
||||
_EP8FIFOBCL = 0xe6b2
|
||||
_SUDPTRH = 0xe6b3
|
||||
_SUDPTRL = 0xe6b4
|
||||
_SUDPTRCTL = 0xe6b5
|
||||
_SETUPDAT = 0xe6b8
|
||||
_GPIFWFSELECT = 0xe6c0
|
||||
_GPIFIDLECS = 0xe6c1
|
||||
_GPIFIDLECTL = 0xe6c2
|
||||
_GPIFCTLCFG = 0xe6c3
|
||||
_GPIFADRH = 0xe6c4
|
||||
_GPIFADRL = 0xe6c5
|
||||
_GPIFTCB3 = 0xe6ce
|
||||
_GPIFTCB2 = 0xe6cf
|
||||
_GPIFTCB1 = 0xe6d0
|
||||
_GPIFTCB0 = 0xe6d1
|
||||
_EP2GPIFFLGSEL = 0xe6d2
|
||||
_EP2GPIFPFSTOP = 0xe6d3
|
||||
_EP2GPIFTRIG = 0xe6d4
|
||||
_EP4GPIFFLGSEL = 0xe6da
|
||||
_EP4GPIFPFSTOP = 0xe6db
|
||||
_EP4GPIFTRIG = 0xe6dc
|
||||
_EP6GPIFFLGSEL = 0xe6e2
|
||||
_EP6GPIFPFSTOP = 0xe6e3
|
||||
_EP6GPIFTRIG = 0xe6e4
|
||||
_EP8GPIFFLGSEL = 0xe6ea
|
||||
_EP8GPIFPFSTOP = 0xe6eb
|
||||
_EP8GPIFTRIG = 0xe6ec
|
||||
_XGPIFSGLDATH = 0xe6f0
|
||||
_XGPIFSGLDATLX = 0xe6f1
|
||||
_XGPIFSGLDATLNOX = 0xe6f2
|
||||
_GPIFREADYCFG = 0xe6f3
|
||||
_GPIFREADYSTAT = 0xe6f4
|
||||
_GPIFABORT = 0xe6f5
|
||||
_FLOWSTATE = 0xe6c6
|
||||
_FLOWLOGIC = 0xe6c7
|
||||
_FLOWEQ0CTL = 0xe6c8
|
||||
_FLOWEQ1CTL = 0xe6c9
|
||||
_FLOWHOLDOFF = 0xe6ca
|
||||
_FLOWSTB = 0xe6cb
|
||||
_FLOWSTBEDGE = 0xe6cc
|
||||
_FLOWSTBHPERIOD = 0xe6cd
|
||||
_GPIFHOLDAMOUNT = 0xe60c
|
||||
_UDMACRCH = 0xe67d
|
||||
_UDMACRCL = 0xe67e
|
||||
_UDMACRCQUAL = 0xe67f
|
||||
_DBUG = 0xe6f8
|
||||
_TESTCFG = 0xe6f9
|
||||
_USBTEST = 0xe6fa
|
||||
_CT1 = 0xe6fb
|
||||
_CT2 = 0xe6fc
|
||||
_CT3 = 0xe6fd
|
||||
_CT4 = 0xe6fe
|
||||
_EP0BUF = 0xe740
|
||||
_EP1OUTBUF = 0xe780
|
||||
_EP1INBUF = 0xe7c0
|
||||
_EP2FIFOBUF = 0xf000
|
||||
_EP4FIFOBUF = 0xf400
|
||||
_EP6FIFOBUF = 0xf800
|
||||
_EP8FIFOBUF = 0xfc00
|
||||
;--------------------------------------------------------
|
||||
; absolute external ram data
|
||||
;--------------------------------------------------------
|
||||
.area XABS (ABS,XDATA)
|
||||
;--------------------------------------------------------
|
||||
; external initialized ram data
|
||||
;--------------------------------------------------------
|
||||
.area HOME (CODE)
|
||||
.area GSINIT0 (CODE)
|
||||
.area GSINIT1 (CODE)
|
||||
.area GSINIT2 (CODE)
|
||||
.area GSINIT3 (CODE)
|
||||
.area GSINIT4 (CODE)
|
||||
.area GSINIT5 (CODE)
|
||||
.area GSINIT (CODE)
|
||||
.area GSFINAL (CODE)
|
||||
.area CSEG (CODE)
|
||||
;--------------------------------------------------------
|
||||
; global & static initialisations
|
||||
;--------------------------------------------------------
|
||||
.area HOME (CODE)
|
||||
.area GSINIT (CODE)
|
||||
.area GSFINAL (CODE)
|
||||
.area GSINIT (CODE)
|
||||
;--------------------------------------------------------
|
||||
; Home
|
||||
;--------------------------------------------------------
|
||||
.area HOME (CODE)
|
||||
.area HOME (CODE)
|
||||
;--------------------------------------------------------
|
||||
; code
|
||||
;--------------------------------------------------------
|
||||
.area CSEG (CODE)
|
||||
;------------------------------------------------------------
|
||||
;Allocation info for local variables in function 'hook_timer_tick'
|
||||
;------------------------------------------------------------
|
||||
;isr_tick_handler Allocated to registers r2 r3
|
||||
;------------------------------------------------------------
|
||||
; timer.c:39: hook_timer_tick (unsigned short isr_tick_handler)
|
||||
; -----------------------------------------
|
||||
; function hook_timer_tick
|
||||
; -----------------------------------------
|
||||
_hook_timer_tick:
|
||||
ar2 = 0x02
|
||||
ar3 = 0x03
|
||||
ar4 = 0x04
|
||||
ar5 = 0x05
|
||||
ar6 = 0x06
|
||||
ar7 = 0x07
|
||||
ar0 = 0x00
|
||||
ar1 = 0x01
|
||||
mov r2,dpl
|
||||
mov r3,dph
|
||||
; timer.c:41: ET2 = 0; // disable timer 2 interrupts
|
||||
clr _ET2
|
||||
; timer.c:42: hook_sv (SV_TIMER_2, isr_tick_handler);
|
||||
mov _hook_sv_PARM_2,r2
|
||||
mov (_hook_sv_PARM_2 + 1),r3
|
||||
mov dpl,#0x2B
|
||||
lcall _hook_sv
|
||||
; timer.c:44: RCAP2H = RELOAD_VALUE >> 8; // setup the auto reload value
|
||||
mov _RCAP2H,#0x63
|
||||
; timer.c:45: RCAP2L = RELOAD_VALUE;
|
||||
mov _RCAP2L,#0xC0
|
||||
; timer.c:47: T2CON = 0x04; // interrupt on overflow; reload; run
|
||||
mov _T2CON,#0x04
|
||||
; timer.c:48: ET2 = 1; // enable timer 2 interrupts
|
||||
setb _ET2
|
||||
ret
|
||||
.area CSEG (CODE)
|
||||
.area CONST (CODE)
|
||||
.area CABS (ABS,CODE)
|
||||
49
firmware/GN3S_v2/lib/timer.c
Normal file
49
firmware/GN3S_v2/lib/timer.c
Normal file
@@ -0,0 +1,49 @@
|
||||
/* -*- c++ -*- */
|
||||
/*
|
||||
* Copyright 2003 Free Software Foundation, Inc.
|
||||
*
|
||||
* This file is part of GNU Radio
|
||||
*
|
||||
* GNU Radio is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* GNU Radio is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with GNU Radio; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
|
||||
* Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#include "timer.h"
|
||||
#include "fx2regs.h"
|
||||
#include "isr.h"
|
||||
|
||||
/*
|
||||
* Arrange to have isr_tick_handler called at 100 Hz.
|
||||
*
|
||||
* The cpu clock is running at 48e6. The input to the timer
|
||||
* is 48e6 / 12 = 4e6.
|
||||
*
|
||||
* We arrange to have the timer overflow every 40000 clocks == 100 Hz
|
||||
*/
|
||||
|
||||
#define RELOAD_VALUE ((unsigned short) -40000)
|
||||
|
||||
void
|
||||
hook_timer_tick (unsigned short isr_tick_handler)
|
||||
{
|
||||
ET2 = 0; // disable timer 2 interrupts
|
||||
hook_sv (SV_TIMER_2, isr_tick_handler);
|
||||
|
||||
RCAP2H = RELOAD_VALUE >> 8; // setup the auto reload value
|
||||
RCAP2L = RELOAD_VALUE;
|
||||
|
||||
T2CON = 0x04; // interrupt on overflow; reload; run
|
||||
ET2 = 1; // enable timer 2 interrupts
|
||||
}
|
||||
770
firmware/GN3S_v2/lib/timer.lst
Normal file
770
firmware/GN3S_v2/lib/timer.lst
Normal file
@@ -0,0 +1,770 @@
|
||||
1 ;--------------------------------------------------------
|
||||
2 ; File Created by SDCC : free open source ANSI-C Compiler
|
||||
3 ; Version 2.9.0 #5416 (Feb 3 2010) (UNIX)
|
||||
4 ; This file was generated Mon Jul 30 11:40:53 2012
|
||||
5 ;--------------------------------------------------------
|
||||
6 .module timer
|
||||
7 .optsdcc -mmcs51 --model-small
|
||||
8
|
||||
9 ;--------------------------------------------------------
|
||||
10 ; Public variables in this module
|
||||
11 ;--------------------------------------------------------
|
||||
12 .globl _EIPX6
|
||||
13 .globl _EIPX5
|
||||
14 .globl _EIPX4
|
||||
15 .globl _PI2C
|
||||
16 .globl _PUSB
|
||||
17 .globl _EIEX6
|
||||
18 .globl _EIEX5
|
||||
19 .globl _EIEX4
|
||||
20 .globl _EI2C
|
||||
21 .globl _EIUSB
|
||||
22 .globl _SMOD1
|
||||
23 .globl _ERESI
|
||||
24 .globl _RESI
|
||||
25 .globl _INT6
|
||||
26 .globl _CY
|
||||
27 .globl _AC
|
||||
28 .globl _F0
|
||||
29 .globl _RS1
|
||||
30 .globl _RS0
|
||||
31 .globl _OV
|
||||
32 .globl _FL
|
||||
33 .globl _P
|
||||
34 .globl _TF2
|
||||
35 .globl _EXF2
|
||||
36 .globl _RCLK
|
||||
37 .globl _TCLK
|
||||
38 .globl _EXEN2
|
||||
39 .globl _TR2
|
||||
40 .globl _C_T2
|
||||
41 .globl _CP_RL2
|
||||
42 .globl _SM01
|
||||
43 .globl _SM11
|
||||
44 .globl _SM21
|
||||
45 .globl _REN1
|
||||
46 .globl _TB81
|
||||
47 .globl _RB81
|
||||
48 .globl _TI1
|
||||
49 .globl _RI1
|
||||
50 .globl _PS1
|
||||
51 .globl _PT2
|
||||
52 .globl _PS0
|
||||
53 .globl _PT1
|
||||
54 .globl _PX1
|
||||
55 .globl _PT0
|
||||
56 .globl _PX0
|
||||
57 .globl _D7
|
||||
58 .globl _D6
|
||||
59 .globl _D5
|
||||
60 .globl _D4
|
||||
61 .globl _D3
|
||||
62 .globl _D2
|
||||
63 .globl _D1
|
||||
64 .globl _D0
|
||||
65 .globl _EA
|
||||
66 .globl _ES1
|
||||
67 .globl _ET2
|
||||
68 .globl _ES0
|
||||
69 .globl _ET1
|
||||
70 .globl _EX1
|
||||
71 .globl _ET0
|
||||
72 .globl _EX0
|
||||
73 .globl _SM0
|
||||
74 .globl _SM1
|
||||
75 .globl _SM2
|
||||
76 .globl _REN
|
||||
77 .globl _TB8
|
||||
78 .globl _RB8
|
||||
79 .globl _TI
|
||||
80 .globl _RI
|
||||
81 .globl _TF1
|
||||
82 .globl _TR1
|
||||
83 .globl _TF0
|
||||
84 .globl _TR0
|
||||
85 .globl _IE1
|
||||
86 .globl _IT1
|
||||
87 .globl _IE0
|
||||
88 .globl _IT0
|
||||
89 .globl _SEL
|
||||
90 .globl _A7
|
||||
91 .globl _A6
|
||||
92 .globl _A5
|
||||
93 .globl _A4
|
||||
94 .globl _A3
|
||||
95 .globl _A2
|
||||
96 .globl _A1
|
||||
97 .globl _A0
|
||||
98 .globl _EIP
|
||||
99 .globl _B
|
||||
100 .globl _EIE
|
||||
101 .globl _ACC
|
||||
102 .globl _EICON
|
||||
103 .globl _PSW
|
||||
104 .globl _TH2
|
||||
105 .globl _TL2
|
||||
106 .globl _RCAP2H
|
||||
107 .globl _RCAP2L
|
||||
108 .globl _T2CON
|
||||
109 .globl _SBUF1
|
||||
110 .globl _SCON1
|
||||
111 .globl _GPIFSGLDATLNOX
|
||||
112 .globl _GPIFSGLDATLX
|
||||
113 .globl _GPIFSGLDATH
|
||||
114 .globl _GPIFTRIG
|
||||
115 .globl _EP01STAT
|
||||
116 .globl _IP
|
||||
117 .globl _OEE
|
||||
118 .globl _OED
|
||||
119 .globl _OEC
|
||||
120 .globl _OEB
|
||||
121 .globl _OEA
|
||||
122 .globl _IOE
|
||||
123 .globl _IOD
|
||||
124 .globl _AUTOPTRSETUP
|
||||
125 .globl _EP68FIFOFLGS
|
||||
126 .globl _EP24FIFOFLGS
|
||||
127 .globl _EP2468STAT
|
||||
128 .globl _IE
|
||||
129 .globl _INT4CLR
|
||||
130 .globl _INT2CLR
|
||||
131 .globl _IOC
|
||||
132 .globl _AUTODAT2
|
||||
133 .globl _AUTOPTRL2
|
||||
134 .globl _AUTOPTRH2
|
||||
135 .globl _AUTODAT1
|
||||
136 .globl _APTR1L
|
||||
137 .globl _APTR1H
|
||||
138 .globl _SBUF0
|
||||
139 .globl _SCON0
|
||||
140 .globl _MPAGE
|
||||
141 .globl _EXIF
|
||||
142 .globl _IOB
|
||||
143 .globl _CKCON
|
||||
144 .globl _TH1
|
||||
145 .globl _TH0
|
||||
146 .globl _TL1
|
||||
147 .globl _TL0
|
||||
148 .globl _TMOD
|
||||
149 .globl _TCON
|
||||
150 .globl _PCON
|
||||
151 .globl _DPS
|
||||
152 .globl _DPH1
|
||||
153 .globl _DPL1
|
||||
154 .globl _DPH
|
||||
155 .globl _DPL
|
||||
156 .globl _SP
|
||||
157 .globl _IOA
|
||||
158 .globl _EP8FIFOBUF
|
||||
159 .globl _EP6FIFOBUF
|
||||
160 .globl _EP4FIFOBUF
|
||||
161 .globl _EP2FIFOBUF
|
||||
162 .globl _EP1INBUF
|
||||
163 .globl _EP1OUTBUF
|
||||
164 .globl _EP0BUF
|
||||
165 .globl _CT4
|
||||
166 .globl _CT3
|
||||
167 .globl _CT2
|
||||
168 .globl _CT1
|
||||
169 .globl _USBTEST
|
||||
170 .globl _TESTCFG
|
||||
171 .globl _DBUG
|
||||
172 .globl _UDMACRCQUAL
|
||||
173 .globl _UDMACRCL
|
||||
174 .globl _UDMACRCH
|
||||
175 .globl _GPIFHOLDAMOUNT
|
||||
176 .globl _FLOWSTBHPERIOD
|
||||
177 .globl _FLOWSTBEDGE
|
||||
178 .globl _FLOWSTB
|
||||
179 .globl _FLOWHOLDOFF
|
||||
180 .globl _FLOWEQ1CTL
|
||||
181 .globl _FLOWEQ0CTL
|
||||
182 .globl _FLOWLOGIC
|
||||
183 .globl _FLOWSTATE
|
||||
184 .globl _GPIFABORT
|
||||
185 .globl _GPIFREADYSTAT
|
||||
186 .globl _GPIFREADYCFG
|
||||
187 .globl _XGPIFSGLDATLNOX
|
||||
188 .globl _XGPIFSGLDATLX
|
||||
189 .globl _XGPIFSGLDATH
|
||||
190 .globl _EP8GPIFTRIG
|
||||
191 .globl _EP8GPIFPFSTOP
|
||||
192 .globl _EP8GPIFFLGSEL
|
||||
193 .globl _EP6GPIFTRIG
|
||||
194 .globl _EP6GPIFPFSTOP
|
||||
195 .globl _EP6GPIFFLGSEL
|
||||
196 .globl _EP4GPIFTRIG
|
||||
197 .globl _EP4GPIFPFSTOP
|
||||
198 .globl _EP4GPIFFLGSEL
|
||||
199 .globl _EP2GPIFTRIG
|
||||
200 .globl _EP2GPIFPFSTOP
|
||||
201 .globl _EP2GPIFFLGSEL
|
||||
202 .globl _GPIFTCB0
|
||||
203 .globl _GPIFTCB1
|
||||
204 .globl _GPIFTCB2
|
||||
205 .globl _GPIFTCB3
|
||||
206 .globl _GPIFADRL
|
||||
207 .globl _GPIFADRH
|
||||
208 .globl _GPIFCTLCFG
|
||||
209 .globl _GPIFIDLECTL
|
||||
210 .globl _GPIFIDLECS
|
||||
211 .globl _GPIFWFSELECT
|
||||
212 .globl _SETUPDAT
|
||||
213 .globl _SUDPTRCTL
|
||||
214 .globl _SUDPTRL
|
||||
215 .globl _SUDPTRH
|
||||
216 .globl _EP8FIFOBCL
|
||||
217 .globl _EP8FIFOBCH
|
||||
218 .globl _EP6FIFOBCL
|
||||
219 .globl _EP6FIFOBCH
|
||||
220 .globl _EP4FIFOBCL
|
||||
221 .globl _EP4FIFOBCH
|
||||
222 .globl _EP2FIFOBCL
|
||||
223 .globl _EP2FIFOBCH
|
||||
224 .globl _EP8FIFOFLGS
|
||||
225 .globl _EP6FIFOFLGS
|
||||
226 .globl _EP4FIFOFLGS
|
||||
227 .globl _EP2FIFOFLGS
|
||||
228 .globl _EP8CS
|
||||
229 .globl _EP6CS
|
||||
230 .globl _EP4CS
|
||||
231 .globl _EP2CS
|
||||
232 .globl _EP1INCS
|
||||
233 .globl _EP1OUTCS
|
||||
234 .globl _EP0CS
|
||||
235 .globl _EP8BCL
|
||||
236 .globl _EP8BCH
|
||||
237 .globl _EP6BCL
|
||||
238 .globl _EP6BCH
|
||||
239 .globl _EP4BCL
|
||||
240 .globl _EP4BCH
|
||||
241 .globl _EP2BCL
|
||||
242 .globl _EP2BCH
|
||||
243 .globl _EP1INBC
|
||||
244 .globl _EP1OUTBC
|
||||
245 .globl _EP0BCL
|
||||
246 .globl _EP0BCH
|
||||
247 .globl _FNADDR
|
||||
248 .globl _MICROFRAME
|
||||
249 .globl _USBFRAMEL
|
||||
250 .globl _USBFRAMEH
|
||||
251 .globl _TOGCTL
|
||||
252 .globl _WAKEUPCS
|
||||
253 .globl _SUSPEND
|
||||
254 .globl _USBCS
|
||||
255 .globl _XAUTODAT2
|
||||
256 .globl _XAUTODAT1
|
||||
257 .globl _I2CTL
|
||||
258 .globl _I2DAT
|
||||
259 .globl _I2CS
|
||||
260 .globl _PORTECFG
|
||||
261 .globl _PORTCCFG
|
||||
262 .globl _PORTACFG
|
||||
263 .globl _INTSETUP
|
||||
264 .globl _INT4IVEC
|
||||
265 .globl _INT2IVEC
|
||||
266 .globl _CLRERRCNT
|
||||
267 .globl _ERRCNTLIM
|
||||
268 .globl _USBERRIRQ
|
||||
269 .globl _USBERRIE
|
||||
270 .globl _GPIFIRQ
|
||||
271 .globl _GPIFIE
|
||||
272 .globl _EPIRQ
|
||||
273 .globl _EPIE
|
||||
274 .globl _USBIRQ
|
||||
275 .globl _USBIE
|
||||
276 .globl _NAKIRQ
|
||||
277 .globl _NAKIE
|
||||
278 .globl _IBNIRQ
|
||||
279 .globl _IBNIE
|
||||
280 .globl _EP8FIFOIRQ
|
||||
281 .globl _EP8FIFOIE
|
||||
282 .globl _EP6FIFOIRQ
|
||||
283 .globl _EP6FIFOIE
|
||||
284 .globl _EP4FIFOIRQ
|
||||
285 .globl _EP4FIFOIE
|
||||
286 .globl _EP2FIFOIRQ
|
||||
287 .globl _EP2FIFOIE
|
||||
288 .globl _OUTPKTEND
|
||||
289 .globl _INPKTEND
|
||||
290 .globl _EP8ISOINPKTS
|
||||
291 .globl _EP6ISOINPKTS
|
||||
292 .globl _EP4ISOINPKTS
|
||||
293 .globl _EP2ISOINPKTS
|
||||
294 .globl _EP8FIFOPFL
|
||||
295 .globl _EP8FIFOPFH
|
||||
296 .globl _EP6FIFOPFL
|
||||
297 .globl _EP6FIFOPFH
|
||||
298 .globl _EP4FIFOPFL
|
||||
299 .globl _EP4FIFOPFH
|
||||
300 .globl _EP2FIFOPFL
|
||||
301 .globl _EP2FIFOPFH
|
||||
302 .globl _EP8AUTOINLENL
|
||||
303 .globl _EP8AUTOINLENH
|
||||
304 .globl _EP6AUTOINLENL
|
||||
305 .globl _EP6AUTOINLENH
|
||||
306 .globl _EP4AUTOINLENL
|
||||
307 .globl _EP4AUTOINLENH
|
||||
308 .globl _EP2AUTOINLENL
|
||||
309 .globl _EP2AUTOINLENH
|
||||
310 .globl _EP8FIFOCFG
|
||||
311 .globl _EP6FIFOCFG
|
||||
312 .globl _EP4FIFOCFG
|
||||
313 .globl _EP2FIFOCFG
|
||||
314 .globl _EP8CFG
|
||||
315 .globl _EP6CFG
|
||||
316 .globl _EP4CFG
|
||||
317 .globl _EP2CFG
|
||||
318 .globl _EP1INCFG
|
||||
319 .globl _EP1OUTCFG
|
||||
320 .globl _REVCTL
|
||||
321 .globl _REVID
|
||||
322 .globl _FIFOPINPOLAR
|
||||
323 .globl _UART230
|
||||
324 .globl _BPADDRL
|
||||
325 .globl _BPADDRH
|
||||
326 .globl _BREAKPT
|
||||
327 .globl _FIFORESET
|
||||
328 .globl _PINFLAGSCD
|
||||
329 .globl _PINFLAGSAB
|
||||
330 .globl _IFCONFIG
|
||||
331 .globl _CPUCS
|
||||
332 .globl _RES_WAVEDATA_END
|
||||
333 .globl _GPIF_WAVE_DATA
|
||||
334 .globl _hook_timer_tick
|
||||
335 ;--------------------------------------------------------
|
||||
336 ; special function registers
|
||||
337 ;--------------------------------------------------------
|
||||
338 .area RSEG (DATA)
|
||||
0080 339 _IOA = 0x0080
|
||||
0081 340 _SP = 0x0081
|
||||
0082 341 _DPL = 0x0082
|
||||
0083 342 _DPH = 0x0083
|
||||
0084 343 _DPL1 = 0x0084
|
||||
0085 344 _DPH1 = 0x0085
|
||||
0086 345 _DPS = 0x0086
|
||||
0087 346 _PCON = 0x0087
|
||||
0088 347 _TCON = 0x0088
|
||||
0089 348 _TMOD = 0x0089
|
||||
008A 349 _TL0 = 0x008a
|
||||
008B 350 _TL1 = 0x008b
|
||||
008C 351 _TH0 = 0x008c
|
||||
008D 352 _TH1 = 0x008d
|
||||
008E 353 _CKCON = 0x008e
|
||||
0090 354 _IOB = 0x0090
|
||||
0091 355 _EXIF = 0x0091
|
||||
0092 356 _MPAGE = 0x0092
|
||||
0098 357 _SCON0 = 0x0098
|
||||
0099 358 _SBUF0 = 0x0099
|
||||
009A 359 _APTR1H = 0x009a
|
||||
009B 360 _APTR1L = 0x009b
|
||||
009C 361 _AUTODAT1 = 0x009c
|
||||
009D 362 _AUTOPTRH2 = 0x009d
|
||||
009E 363 _AUTOPTRL2 = 0x009e
|
||||
009F 364 _AUTODAT2 = 0x009f
|
||||
00A0 365 _IOC = 0x00a0
|
||||
00A1 366 _INT2CLR = 0x00a1
|
||||
00A2 367 _INT4CLR = 0x00a2
|
||||
00A8 368 _IE = 0x00a8
|
||||
00AA 369 _EP2468STAT = 0x00aa
|
||||
00AB 370 _EP24FIFOFLGS = 0x00ab
|
||||
00AC 371 _EP68FIFOFLGS = 0x00ac
|
||||
00AF 372 _AUTOPTRSETUP = 0x00af
|
||||
00B0 373 _IOD = 0x00b0
|
||||
00B1 374 _IOE = 0x00b1
|
||||
00B2 375 _OEA = 0x00b2
|
||||
00B3 376 _OEB = 0x00b3
|
||||
00B4 377 _OEC = 0x00b4
|
||||
00B5 378 _OED = 0x00b5
|
||||
00B6 379 _OEE = 0x00b6
|
||||
00B8 380 _IP = 0x00b8
|
||||
00BA 381 _EP01STAT = 0x00ba
|
||||
00BB 382 _GPIFTRIG = 0x00bb
|
||||
00BD 383 _GPIFSGLDATH = 0x00bd
|
||||
00BE 384 _GPIFSGLDATLX = 0x00be
|
||||
00BF 385 _GPIFSGLDATLNOX = 0x00bf
|
||||
00C0 386 _SCON1 = 0x00c0
|
||||
00C1 387 _SBUF1 = 0x00c1
|
||||
00C8 388 _T2CON = 0x00c8
|
||||
00CA 389 _RCAP2L = 0x00ca
|
||||
00CB 390 _RCAP2H = 0x00cb
|
||||
00CC 391 _TL2 = 0x00cc
|
||||
00CD 392 _TH2 = 0x00cd
|
||||
00D0 393 _PSW = 0x00d0
|
||||
00D8 394 _EICON = 0x00d8
|
||||
00E0 395 _ACC = 0x00e0
|
||||
00E8 396 _EIE = 0x00e8
|
||||
00F0 397 _B = 0x00f0
|
||||
00F8 398 _EIP = 0x00f8
|
||||
399 ;--------------------------------------------------------
|
||||
400 ; special function bits
|
||||
401 ;--------------------------------------------------------
|
||||
402 .area RSEG (DATA)
|
||||
0080 403 _A0 = 0x0080
|
||||
0081 404 _A1 = 0x0081
|
||||
0082 405 _A2 = 0x0082
|
||||
0083 406 _A3 = 0x0083
|
||||
0084 407 _A4 = 0x0084
|
||||
0085 408 _A5 = 0x0085
|
||||
0086 409 _A6 = 0x0086
|
||||
0087 410 _A7 = 0x0087
|
||||
0086 411 _SEL = 0x0086
|
||||
0088 412 _IT0 = 0x0088
|
||||
0089 413 _IE0 = 0x0089
|
||||
008A 414 _IT1 = 0x008a
|
||||
008B 415 _IE1 = 0x008b
|
||||
008C 416 _TR0 = 0x008c
|
||||
008D 417 _TF0 = 0x008d
|
||||
008E 418 _TR1 = 0x008e
|
||||
008F 419 _TF1 = 0x008f
|
||||
0098 420 _RI = 0x0098
|
||||
0099 421 _TI = 0x0099
|
||||
009A 422 _RB8 = 0x009a
|
||||
009B 423 _TB8 = 0x009b
|
||||
009C 424 _REN = 0x009c
|
||||
009D 425 _SM2 = 0x009d
|
||||
009E 426 _SM1 = 0x009e
|
||||
009F 427 _SM0 = 0x009f
|
||||
00A8 428 _EX0 = 0x00a8
|
||||
00A9 429 _ET0 = 0x00a9
|
||||
00AA 430 _EX1 = 0x00aa
|
||||
00AB 431 _ET1 = 0x00ab
|
||||
00AC 432 _ES0 = 0x00ac
|
||||
00AD 433 _ET2 = 0x00ad
|
||||
00AE 434 _ES1 = 0x00ae
|
||||
00AF 435 _EA = 0x00af
|
||||
00B0 436 _D0 = 0x00b0
|
||||
00B1 437 _D1 = 0x00b1
|
||||
00B2 438 _D2 = 0x00b2
|
||||
00B3 439 _D3 = 0x00b3
|
||||
00B4 440 _D4 = 0x00b4
|
||||
00B5 441 _D5 = 0x00b5
|
||||
00B6 442 _D6 = 0x00b6
|
||||
00B7 443 _D7 = 0x00b7
|
||||
00B8 444 _PX0 = 0x00b8
|
||||
00B9 445 _PT0 = 0x00b9
|
||||
00BA 446 _PX1 = 0x00ba
|
||||
00BB 447 _PT1 = 0x00bb
|
||||
00BC 448 _PS0 = 0x00bc
|
||||
00BD 449 _PT2 = 0x00bd
|
||||
00BE 450 _PS1 = 0x00be
|
||||
00C0 451 _RI1 = 0x00c0
|
||||
00C1 452 _TI1 = 0x00c1
|
||||
00C2 453 _RB81 = 0x00c2
|
||||
00C3 454 _TB81 = 0x00c3
|
||||
00C4 455 _REN1 = 0x00c4
|
||||
00C5 456 _SM21 = 0x00c5
|
||||
00C6 457 _SM11 = 0x00c6
|
||||
00C7 458 _SM01 = 0x00c7
|
||||
00C8 459 _CP_RL2 = 0x00c8
|
||||
00C9 460 _C_T2 = 0x00c9
|
||||
00CA 461 _TR2 = 0x00ca
|
||||
00CB 462 _EXEN2 = 0x00cb
|
||||
00CC 463 _TCLK = 0x00cc
|
||||
00CD 464 _RCLK = 0x00cd
|
||||
00CE 465 _EXF2 = 0x00ce
|
||||
00CF 466 _TF2 = 0x00cf
|
||||
00D0 467 _P = 0x00d0
|
||||
00D1 468 _FL = 0x00d1
|
||||
00D2 469 _OV = 0x00d2
|
||||
00D3 470 _RS0 = 0x00d3
|
||||
00D4 471 _RS1 = 0x00d4
|
||||
00D5 472 _F0 = 0x00d5
|
||||
00D6 473 _AC = 0x00d6
|
||||
00D7 474 _CY = 0x00d7
|
||||
00DB 475 _INT6 = 0x00db
|
||||
00DC 476 _RESI = 0x00dc
|
||||
00DD 477 _ERESI = 0x00dd
|
||||
00DF 478 _SMOD1 = 0x00df
|
||||
00E8 479 _EIUSB = 0x00e8
|
||||
00E9 480 _EI2C = 0x00e9
|
||||
00EA 481 _EIEX4 = 0x00ea
|
||||
00EB 482 _EIEX5 = 0x00eb
|
||||
00EC 483 _EIEX6 = 0x00ec
|
||||
00F8 484 _PUSB = 0x00f8
|
||||
00F9 485 _PI2C = 0x00f9
|
||||
00FA 486 _EIPX4 = 0x00fa
|
||||
00FB 487 _EIPX5 = 0x00fb
|
||||
00FC 488 _EIPX6 = 0x00fc
|
||||
489 ;--------------------------------------------------------
|
||||
490 ; overlayable register banks
|
||||
491 ;--------------------------------------------------------
|
||||
492 .area REG_BANK_0 (REL,OVR,DATA)
|
||||
0000 493 .ds 8
|
||||
494 ;--------------------------------------------------------
|
||||
495 ; internal ram data
|
||||
496 ;--------------------------------------------------------
|
||||
497 .area DSEG (DATA)
|
||||
498 ;--------------------------------------------------------
|
||||
499 ; overlayable items in internal ram
|
||||
500 ;--------------------------------------------------------
|
||||
501 .area OSEG (OVR,DATA)
|
||||
502 ;--------------------------------------------------------
|
||||
503 ; indirectly addressable internal ram data
|
||||
504 ;--------------------------------------------------------
|
||||
505 .area ISEG (DATA)
|
||||
506 ;--------------------------------------------------------
|
||||
507 ; absolute internal ram data
|
||||
508 ;--------------------------------------------------------
|
||||
509 .area IABS (ABS,DATA)
|
||||
510 .area IABS (ABS,DATA)
|
||||
511 ;--------------------------------------------------------
|
||||
512 ; bit data
|
||||
513 ;--------------------------------------------------------
|
||||
514 .area BSEG (BIT)
|
||||
515 ;--------------------------------------------------------
|
||||
516 ; paged external ram data
|
||||
517 ;--------------------------------------------------------
|
||||
518 .area PSEG (PAG,XDATA)
|
||||
519 ;--------------------------------------------------------
|
||||
520 ; external ram data
|
||||
521 ;--------------------------------------------------------
|
||||
522 .area XSEG (XDATA)
|
||||
E400 523 _GPIF_WAVE_DATA = 0xe400
|
||||
E480 524 _RES_WAVEDATA_END = 0xe480
|
||||
E600 525 _CPUCS = 0xe600
|
||||
E601 526 _IFCONFIG = 0xe601
|
||||
E602 527 _PINFLAGSAB = 0xe602
|
||||
E603 528 _PINFLAGSCD = 0xe603
|
||||
E604 529 _FIFORESET = 0xe604
|
||||
E605 530 _BREAKPT = 0xe605
|
||||
E606 531 _BPADDRH = 0xe606
|
||||
E607 532 _BPADDRL = 0xe607
|
||||
E608 533 _UART230 = 0xe608
|
||||
E609 534 _FIFOPINPOLAR = 0xe609
|
||||
E60A 535 _REVID = 0xe60a
|
||||
E60B 536 _REVCTL = 0xe60b
|
||||
E610 537 _EP1OUTCFG = 0xe610
|
||||
E611 538 _EP1INCFG = 0xe611
|
||||
E612 539 _EP2CFG = 0xe612
|
||||
E613 540 _EP4CFG = 0xe613
|
||||
E614 541 _EP6CFG = 0xe614
|
||||
E615 542 _EP8CFG = 0xe615
|
||||
E618 543 _EP2FIFOCFG = 0xe618
|
||||
E619 544 _EP4FIFOCFG = 0xe619
|
||||
E61A 545 _EP6FIFOCFG = 0xe61a
|
||||
E61B 546 _EP8FIFOCFG = 0xe61b
|
||||
E620 547 _EP2AUTOINLENH = 0xe620
|
||||
E621 548 _EP2AUTOINLENL = 0xe621
|
||||
E622 549 _EP4AUTOINLENH = 0xe622
|
||||
E623 550 _EP4AUTOINLENL = 0xe623
|
||||
E624 551 _EP6AUTOINLENH = 0xe624
|
||||
E625 552 _EP6AUTOINLENL = 0xe625
|
||||
E626 553 _EP8AUTOINLENH = 0xe626
|
||||
E627 554 _EP8AUTOINLENL = 0xe627
|
||||
E630 555 _EP2FIFOPFH = 0xe630
|
||||
E631 556 _EP2FIFOPFL = 0xe631
|
||||
E632 557 _EP4FIFOPFH = 0xe632
|
||||
E633 558 _EP4FIFOPFL = 0xe633
|
||||
E634 559 _EP6FIFOPFH = 0xe634
|
||||
E635 560 _EP6FIFOPFL = 0xe635
|
||||
E636 561 _EP8FIFOPFH = 0xe636
|
||||
E637 562 _EP8FIFOPFL = 0xe637
|
||||
E640 563 _EP2ISOINPKTS = 0xe640
|
||||
E641 564 _EP4ISOINPKTS = 0xe641
|
||||
E642 565 _EP6ISOINPKTS = 0xe642
|
||||
E643 566 _EP8ISOINPKTS = 0xe643
|
||||
E648 567 _INPKTEND = 0xe648
|
||||
E649 568 _OUTPKTEND = 0xe649
|
||||
E650 569 _EP2FIFOIE = 0xe650
|
||||
E651 570 _EP2FIFOIRQ = 0xe651
|
||||
E652 571 _EP4FIFOIE = 0xe652
|
||||
E653 572 _EP4FIFOIRQ = 0xe653
|
||||
E654 573 _EP6FIFOIE = 0xe654
|
||||
E655 574 _EP6FIFOIRQ = 0xe655
|
||||
E656 575 _EP8FIFOIE = 0xe656
|
||||
E657 576 _EP8FIFOIRQ = 0xe657
|
||||
E658 577 _IBNIE = 0xe658
|
||||
E659 578 _IBNIRQ = 0xe659
|
||||
E65A 579 _NAKIE = 0xe65a
|
||||
E65B 580 _NAKIRQ = 0xe65b
|
||||
E65C 581 _USBIE = 0xe65c
|
||||
E65D 582 _USBIRQ = 0xe65d
|
||||
E65E 583 _EPIE = 0xe65e
|
||||
E65F 584 _EPIRQ = 0xe65f
|
||||
E660 585 _GPIFIE = 0xe660
|
||||
E661 586 _GPIFIRQ = 0xe661
|
||||
E662 587 _USBERRIE = 0xe662
|
||||
E663 588 _USBERRIRQ = 0xe663
|
||||
E664 589 _ERRCNTLIM = 0xe664
|
||||
E665 590 _CLRERRCNT = 0xe665
|
||||
E666 591 _INT2IVEC = 0xe666
|
||||
E667 592 _INT4IVEC = 0xe667
|
||||
E668 593 _INTSETUP = 0xe668
|
||||
E670 594 _PORTACFG = 0xe670
|
||||
E671 595 _PORTCCFG = 0xe671
|
||||
E672 596 _PORTECFG = 0xe672
|
||||
E678 597 _I2CS = 0xe678
|
||||
E679 598 _I2DAT = 0xe679
|
||||
E67A 599 _I2CTL = 0xe67a
|
||||
E67B 600 _XAUTODAT1 = 0xe67b
|
||||
E67C 601 _XAUTODAT2 = 0xe67c
|
||||
E680 602 _USBCS = 0xe680
|
||||
E681 603 _SUSPEND = 0xe681
|
||||
E682 604 _WAKEUPCS = 0xe682
|
||||
E683 605 _TOGCTL = 0xe683
|
||||
E684 606 _USBFRAMEH = 0xe684
|
||||
E685 607 _USBFRAMEL = 0xe685
|
||||
E686 608 _MICROFRAME = 0xe686
|
||||
E687 609 _FNADDR = 0xe687
|
||||
E68A 610 _EP0BCH = 0xe68a
|
||||
E68B 611 _EP0BCL = 0xe68b
|
||||
E68D 612 _EP1OUTBC = 0xe68d
|
||||
E68F 613 _EP1INBC = 0xe68f
|
||||
E690 614 _EP2BCH = 0xe690
|
||||
E691 615 _EP2BCL = 0xe691
|
||||
E694 616 _EP4BCH = 0xe694
|
||||
E695 617 _EP4BCL = 0xe695
|
||||
E698 618 _EP6BCH = 0xe698
|
||||
E699 619 _EP6BCL = 0xe699
|
||||
E69C 620 _EP8BCH = 0xe69c
|
||||
E69D 621 _EP8BCL = 0xe69d
|
||||
E6A0 622 _EP0CS = 0xe6a0
|
||||
E6A1 623 _EP1OUTCS = 0xe6a1
|
||||
E6A2 624 _EP1INCS = 0xe6a2
|
||||
E6A3 625 _EP2CS = 0xe6a3
|
||||
E6A4 626 _EP4CS = 0xe6a4
|
||||
E6A5 627 _EP6CS = 0xe6a5
|
||||
E6A6 628 _EP8CS = 0xe6a6
|
||||
E6A7 629 _EP2FIFOFLGS = 0xe6a7
|
||||
E6A8 630 _EP4FIFOFLGS = 0xe6a8
|
||||
E6A9 631 _EP6FIFOFLGS = 0xe6a9
|
||||
E6AA 632 _EP8FIFOFLGS = 0xe6aa
|
||||
E6AB 633 _EP2FIFOBCH = 0xe6ab
|
||||
E6AC 634 _EP2FIFOBCL = 0xe6ac
|
||||
E6AD 635 _EP4FIFOBCH = 0xe6ad
|
||||
E6AE 636 _EP4FIFOBCL = 0xe6ae
|
||||
E6AF 637 _EP6FIFOBCH = 0xe6af
|
||||
E6B0 638 _EP6FIFOBCL = 0xe6b0
|
||||
E6B1 639 _EP8FIFOBCH = 0xe6b1
|
||||
E6B2 640 _EP8FIFOBCL = 0xe6b2
|
||||
E6B3 641 _SUDPTRH = 0xe6b3
|
||||
E6B4 642 _SUDPTRL = 0xe6b4
|
||||
E6B5 643 _SUDPTRCTL = 0xe6b5
|
||||
E6B8 644 _SETUPDAT = 0xe6b8
|
||||
E6C0 645 _GPIFWFSELECT = 0xe6c0
|
||||
E6C1 646 _GPIFIDLECS = 0xe6c1
|
||||
E6C2 647 _GPIFIDLECTL = 0xe6c2
|
||||
E6C3 648 _GPIFCTLCFG = 0xe6c3
|
||||
E6C4 649 _GPIFADRH = 0xe6c4
|
||||
E6C5 650 _GPIFADRL = 0xe6c5
|
||||
E6CE 651 _GPIFTCB3 = 0xe6ce
|
||||
E6CF 652 _GPIFTCB2 = 0xe6cf
|
||||
E6D0 653 _GPIFTCB1 = 0xe6d0
|
||||
E6D1 654 _GPIFTCB0 = 0xe6d1
|
||||
E6D2 655 _EP2GPIFFLGSEL = 0xe6d2
|
||||
E6D3 656 _EP2GPIFPFSTOP = 0xe6d3
|
||||
E6D4 657 _EP2GPIFTRIG = 0xe6d4
|
||||
E6DA 658 _EP4GPIFFLGSEL = 0xe6da
|
||||
E6DB 659 _EP4GPIFPFSTOP = 0xe6db
|
||||
E6DC 660 _EP4GPIFTRIG = 0xe6dc
|
||||
E6E2 661 _EP6GPIFFLGSEL = 0xe6e2
|
||||
E6E3 662 _EP6GPIFPFSTOP = 0xe6e3
|
||||
E6E4 663 _EP6GPIFTRIG = 0xe6e4
|
||||
E6EA 664 _EP8GPIFFLGSEL = 0xe6ea
|
||||
E6EB 665 _EP8GPIFPFSTOP = 0xe6eb
|
||||
E6EC 666 _EP8GPIFTRIG = 0xe6ec
|
||||
E6F0 667 _XGPIFSGLDATH = 0xe6f0
|
||||
E6F1 668 _XGPIFSGLDATLX = 0xe6f1
|
||||
E6F2 669 _XGPIFSGLDATLNOX = 0xe6f2
|
||||
E6F3 670 _GPIFREADYCFG = 0xe6f3
|
||||
E6F4 671 _GPIFREADYSTAT = 0xe6f4
|
||||
E6F5 672 _GPIFABORT = 0xe6f5
|
||||
E6C6 673 _FLOWSTATE = 0xe6c6
|
||||
E6C7 674 _FLOWLOGIC = 0xe6c7
|
||||
E6C8 675 _FLOWEQ0CTL = 0xe6c8
|
||||
E6C9 676 _FLOWEQ1CTL = 0xe6c9
|
||||
E6CA 677 _FLOWHOLDOFF = 0xe6ca
|
||||
E6CB 678 _FLOWSTB = 0xe6cb
|
||||
E6CC 679 _FLOWSTBEDGE = 0xe6cc
|
||||
E6CD 680 _FLOWSTBHPERIOD = 0xe6cd
|
||||
E60C 681 _GPIFHOLDAMOUNT = 0xe60c
|
||||
E67D 682 _UDMACRCH = 0xe67d
|
||||
E67E 683 _UDMACRCL = 0xe67e
|
||||
E67F 684 _UDMACRCQUAL = 0xe67f
|
||||
E6F8 685 _DBUG = 0xe6f8
|
||||
E6F9 686 _TESTCFG = 0xe6f9
|
||||
E6FA 687 _USBTEST = 0xe6fa
|
||||
E6FB 688 _CT1 = 0xe6fb
|
||||
E6FC 689 _CT2 = 0xe6fc
|
||||
E6FD 690 _CT3 = 0xe6fd
|
||||
E6FE 691 _CT4 = 0xe6fe
|
||||
E740 692 _EP0BUF = 0xe740
|
||||
E780 693 _EP1OUTBUF = 0xe780
|
||||
E7C0 694 _EP1INBUF = 0xe7c0
|
||||
F000 695 _EP2FIFOBUF = 0xf000
|
||||
F400 696 _EP4FIFOBUF = 0xf400
|
||||
F800 697 _EP6FIFOBUF = 0xf800
|
||||
FC00 698 _EP8FIFOBUF = 0xfc00
|
||||
699 ;--------------------------------------------------------
|
||||
700 ; absolute external ram data
|
||||
701 ;--------------------------------------------------------
|
||||
702 .area XABS (ABS,XDATA)
|
||||
703 ;--------------------------------------------------------
|
||||
704 ; external initialized ram data
|
||||
705 ;--------------------------------------------------------
|
||||
706 .area HOME (CODE)
|
||||
707 .area GSINIT0 (CODE)
|
||||
708 .area GSINIT1 (CODE)
|
||||
709 .area GSINIT2 (CODE)
|
||||
710 .area GSINIT3 (CODE)
|
||||
711 .area GSINIT4 (CODE)
|
||||
712 .area GSINIT5 (CODE)
|
||||
713 .area GSINIT (CODE)
|
||||
714 .area GSFINAL (CODE)
|
||||
715 .area CSEG (CODE)
|
||||
716 ;--------------------------------------------------------
|
||||
717 ; global & static initialisations
|
||||
718 ;--------------------------------------------------------
|
||||
719 .area HOME (CODE)
|
||||
720 .area GSINIT (CODE)
|
||||
721 .area GSFINAL (CODE)
|
||||
722 .area GSINIT (CODE)
|
||||
723 ;--------------------------------------------------------
|
||||
724 ; Home
|
||||
725 ;--------------------------------------------------------
|
||||
726 .area HOME (CODE)
|
||||
727 .area HOME (CODE)
|
||||
728 ;--------------------------------------------------------
|
||||
729 ; code
|
||||
730 ;--------------------------------------------------------
|
||||
731 .area CSEG (CODE)
|
||||
732 ;------------------------------------------------------------
|
||||
733 ;Allocation info for local variables in function 'hook_timer_tick'
|
||||
734 ;------------------------------------------------------------
|
||||
735 ;isr_tick_handler Allocated to registers r2 r3
|
||||
736 ;------------------------------------------------------------
|
||||
737 ; timer.c:39: hook_timer_tick (unsigned short isr_tick_handler)
|
||||
738 ; -----------------------------------------
|
||||
739 ; function hook_timer_tick
|
||||
740 ; -----------------------------------------
|
||||
0000 741 _hook_timer_tick:
|
||||
0002 742 ar2 = 0x02
|
||||
0003 743 ar3 = 0x03
|
||||
0004 744 ar4 = 0x04
|
||||
0005 745 ar5 = 0x05
|
||||
0006 746 ar6 = 0x06
|
||||
0007 747 ar7 = 0x07
|
||||
0000 748 ar0 = 0x00
|
||||
0001 749 ar1 = 0x01
|
||||
0000 AA 82 750 mov r2,dpl
|
||||
0002 AB 83 751 mov r3,dph
|
||||
752 ; timer.c:41: ET2 = 0; // disable timer 2 interrupts
|
||||
0004 C2 AD 753 clr _ET2
|
||||
754 ; timer.c:42: hook_sv (SV_TIMER_2, isr_tick_handler);
|
||||
0006 8A*00 755 mov _hook_sv_PARM_2,r2
|
||||
0008 8B*01 756 mov (_hook_sv_PARM_2 + 1),r3
|
||||
000A 75 82 2B 757 mov dpl,#0x2B
|
||||
000D 12s00r00 758 lcall _hook_sv
|
||||
759 ; timer.c:44: RCAP2H = RELOAD_VALUE >> 8; // setup the auto reload value
|
||||
0010 75 CB 63 760 mov _RCAP2H,#0x63
|
||||
761 ; timer.c:45: RCAP2L = RELOAD_VALUE;
|
||||
0013 75 CA C0 762 mov _RCAP2L,#0xC0
|
||||
763 ; timer.c:47: T2CON = 0x04; // interrupt on overflow; reload; run
|
||||
0016 75 C8 04 764 mov _T2CON,#0x04
|
||||
765 ; timer.c:48: ET2 = 1; // enable timer 2 interrupts
|
||||
0019 D2 AD 766 setb _ET2
|
||||
001B 22 767 ret
|
||||
768 .area CSEG (CODE)
|
||||
769 .area CONST (CODE)
|
||||
770 .area CABS (ABS,CODE)
|
||||
362
firmware/GN3S_v2/lib/timer.rel
Normal file
362
firmware/GN3S_v2/lib/timer.rel
Normal file
@@ -0,0 +1,362 @@
|
||||
XH
|
||||
H 17 areas 145 global symbols
|
||||
M timer
|
||||
O -mmcs51 --model-small
|
||||
S _EP8FIFOCFG DefE61B
|
||||
S _EPIRQ DefE65F
|
||||
S _USBERRIE DefE662
|
||||
S _EP6CS DefE6A5
|
||||
S _GPIFHOLDAMOUNT DefE60C
|
||||
S _SBUF1 Def00C1
|
||||
S _EIEX6 Def00EC
|
||||
S _EP1INBC DefE68F
|
||||
S _EP8FIFOBCL DefE6B2
|
||||
S _DBUG DefE6F8
|
||||
S _B Def00F0
|
||||
S _EXEN2 Def00CB
|
||||
S _EPIE DefE65E
|
||||
S _WAKEUPCS DefE682
|
||||
S _EP1OUTBC DefE68D
|
||||
S _EP8CS DefE6A6
|
||||
S _EP2GPIFTRIG DefE6D4
|
||||
S _SP Def0081
|
||||
S _SCON0 Def0098
|
||||
S _AUTODAT1 Def009C
|
||||
S _EI2C Def00E9
|
||||
S _INT2IVEC DefE666
|
||||
S _AUTODAT2 Def009F
|
||||
S _SCON1 Def00C0
|
||||
S _SMOD1 Def00DF
|
||||
S _MICROFRAME DefE686
|
||||
S _SUDPTRCTL DefE6B5
|
||||
S _EP4GPIFTRIG DefE6DC
|
||||
S _EP2468STAT Def00AA
|
||||
S _OV Def00D2
|
||||
S _INT4IVEC DefE667
|
||||
S _GPIFSGLDATLNOX Def00BF
|
||||
S _T2CON Def00C8
|
||||
S _EP6GPIFTRIG DefE6E4
|
||||
S _ACC Def00E0
|
||||
S _EP2FIFOBUF DefF000
|
||||
S _C_T2 Def00C9
|
||||
S _BREAKPT DefE605
|
||||
S _EP2FIFOPFH DefE630
|
||||
S _EP8GPIFTRIG DefE6EC
|
||||
S _AUTOPTRH2 Def009D
|
||||
S _SETUPDAT DefE6B8
|
||||
S _EP2GPIFFLGSEL DefE6D2
|
||||
S _EP4FIFOBUF DefF400
|
||||
S _EIPX4 Def00FA
|
||||
S _EP4FIFOPFH DefE632
|
||||
S _EP2ISOINPKTS DefE640
|
||||
S _GPIFREADYCFG DefE6F3
|
||||
S _EIPX5 Def00FB
|
||||
S _EP4GPIFFLGSEL DefE6DA
|
||||
S _FLOWSTBHPERIOD DefE6CD
|
||||
S _EP6FIFOBUF DefF800
|
||||
S _EXIF Def0091
|
||||
S _RCLK Def00CD
|
||||
S _EIPX6 Def00FC
|
||||
S _EP2FIFOPFL DefE631
|
||||
S _EP6FIFOPFH DefE634
|
||||
S _EP4ISOINPKTS DefE641
|
||||
S _DPH1 Def0085
|
||||
S _AUTOPTRL2 Def009E
|
||||
S _EP6GPIFFLGSEL DefE6E2
|
||||
S _EP8FIFOBUF DefFC00
|
||||
S _TCLK Def00CC
|
||||
S _PI2C Def00F9
|
||||
S _EP4FIFOPFL DefE633
|
||||
S _EP8FIFOPFH DefE636
|
||||
S _EP6ISOINPKTS DefE642
|
||||
S _FNADDR DefE687
|
||||
S _EP8GPIFFLGSEL DefE6EA
|
||||
S _TESTCFG DefE6F9
|
||||
S _PCON Def0087
|
||||
S _P Def00D0
|
||||
S _GPIF_WAVE_DATA DefE400
|
||||
S _EP6FIFOPFL DefE635
|
||||
S _EP8ISOINPKTS DefE643
|
||||
S _I2CS DefE678
|
||||
S _DPL1 Def0084
|
||||
S _GPIFIRQ DefE661
|
||||
S _EP0BCH DefE68A
|
||||
S _EP01STAT Def00BA
|
||||
S _EP8FIFOPFL DefE637
|
||||
S _EP1INCS DefE6A2
|
||||
S _EIE Def00E8
|
||||
S _RESI Def00DC
|
||||
S _GPIFIE DefE660
|
||||
S _EP2BCH DefE690
|
||||
S _EP1OUTCS DefE6A1
|
||||
S _TCON Def0088
|
||||
S _TMOD Def0089
|
||||
S _OEA Def00B2
|
||||
S _EXF2 Def00CE
|
||||
S _EP0BCL DefE68B
|
||||
S _EP4BCH DefE694
|
||||
S _OEB Def00B3
|
||||
S _REN1 Def00C4
|
||||
S _EP2CFG DefE612
|
||||
S _EP2FIFOIRQ DefE651
|
||||
S _GPIFREADYSTAT DefE6F4
|
||||
S _OEC Def00B4
|
||||
S _EP2BCL DefE691
|
||||
S _EP6BCH DefE698
|
||||
S _OED Def00B5
|
||||
S _hook_sv Ref0000
|
||||
S _EP4CFG DefE613
|
||||
S _EP2FIFOIE DefE650
|
||||
S _EP4FIFOIRQ DefE653
|
||||
S _IOA Def0080
|
||||
S _OEE Def00B6
|
||||
S _EP4BCL DefE695
|
||||
S _EP8BCH DefE69C
|
||||
S _IOB Def0090
|
||||
S _PUSB Def00F8
|
||||
S _EP6CFG DefE614
|
||||
S _EP4FIFOIE DefE652
|
||||
S _EP6FIFOIRQ DefE655
|
||||
S _IOC Def00A0
|
||||
S _INTSETUP DefE668
|
||||
S _EP6BCL DefE699
|
||||
S _DPH Def0083
|
||||
S _IOD Def00B0
|
||||
S _EP8CFG DefE615
|
||||
S _EP6FIFOIE DefE654
|
||||
S _EP8FIFOIRQ DefE657
|
||||
S _USBFRAMEH DefE684
|
||||
S _IOE Def00B1
|
||||
S _RB81 Def00C2
|
||||
S _EP2AUTOINLENH DefE620
|
||||
S _EP8BCL DefE69D
|
||||
S _GPIFABORT DefE6F5
|
||||
S _INT2CLR Def00A1
|
||||
S _EIP Def00F8
|
||||
S _IE0 Def0089
|
||||
S _EP8FIFOIE DefE656
|
||||
S _IE1 Def008B
|
||||
S _TB81 Def00C3
|
||||
S _EP4AUTOINLENH DefE622
|
||||
S _DPL Def0082
|
||||
S _INT4CLR Def00A2
|
||||
S _AUTOPTRSETUP Def00AF
|
||||
S _RCAP2H Def00CB
|
||||
S _USBFRAMEL DefE685
|
||||
S _XGPIFSGLDATLX DefE6F1
|
||||
S _FLOWEQ0CTL DefE6C8
|
||||
S _FLOWSTB DefE6CB
|
||||
S _SM01 Def00C7
|
||||
S _INT6 Def00DB
|
||||
S _EP2AUTOINLENL DefE621
|
||||
S _EP6AUTOINLENH DefE624
|
||||
S _SUSPEND DefE681
|
||||
S _FLOWEQ1CTL DefE6C9
|
||||
S _EP0BUF DefE740
|
||||
S _SM11 Def00C6
|
||||
S _CP_RL2 Def00C8
|
||||
S _GPIFWFSELECT DefE6C0
|
||||
S _SM21 Def00C5
|
||||
S _EP4AUTOINLENL DefE623
|
||||
S _EP8AUTOINLENH DefE626
|
||||
S _RCAP2L Def00CA
|
||||
S _SEL Def0086
|
||||
S _AC Def00D6
|
||||
S _IFCONFIG DefE601
|
||||
S _IBNIRQ DefE659
|
||||
S _GPIFADRH DefE6C4
|
||||
S _XGPIFSGLDATH DefE6F0
|
||||
S _REN Def009C
|
||||
S _EP6AUTOINLENL DefE625
|
||||
S _NAKIRQ DefE65B
|
||||
S _FLOWLOGIC DefE6C7
|
||||
S _EA Def00AF
|
||||
S _FIFORESET DefE604
|
||||
S _IBNIE DefE658
|
||||
S _GPIFIDLECTL DefE6C2
|
||||
S _UDMACRCH DefE67D
|
||||
S _DPS Def0086
|
||||
S _EP8AUTOINLENL DefE627
|
||||
S _NAKIE DefE65A
|
||||
S _CT1 DefE6FB
|
||||
S _ES0 Def00AC
|
||||
S _FIFOPINPOLAR DefE609
|
||||
S _GPIFADRL DefE6C5
|
||||
S _EP2GPIFPFSTOP DefE6D3
|
||||
S _CT2 DefE6FC
|
||||
S _GPIFSGLDATLX Def00BE
|
||||
S _ET0 Def00A9
|
||||
S _ES1 Def00AE
|
||||
S _SUDPTRH DefE6B3
|
||||
S _USBTEST DefE6FA
|
||||
S _CT3 DefE6FD
|
||||
S _MPAGE Def0092
|
||||
S _TF0 Def008D
|
||||
S _ET1 Def00AB
|
||||
S _EP4GPIFPFSTOP DefE6DB
|
||||
S _UDMACRCL DefE67E
|
||||
S _CT4 DefE6FE
|
||||
S _EP24FIFOFLGS Def00AB
|
||||
S _TF1 Def008F
|
||||
S _ET2 Def00AD
|
||||
S _RES_WAVEDATA_END DefE480
|
||||
S _TH0 Def008C
|
||||
S _RB8 Def009A
|
||||
S _RI1 Def00C0
|
||||
S _TF2 Def00CF
|
||||
S _EP1INCFG DefE611
|
||||
S _TOGCTL DefE683
|
||||
S _EP6GPIFPFSTOP DefE6E3
|
||||
S _TH1 Def008D
|
||||
S _GPIFSGLDATH Def00BD
|
||||
S _IT0 Def0088
|
||||
S _EX0 Def00A8
|
||||
S _EP1OUTCFG DefE610
|
||||
S _SUDPTRL DefE6B4
|
||||
S _CKCON Def008E
|
||||
S _IE Def00A8
|
||||
S _TH2 Def00CD
|
||||
S _EICON Def00D8
|
||||
S _IT1 Def008A
|
||||
S _TB8 Def009B
|
||||
S _EX1 Def00AA
|
||||
S _TI1 Def00C1
|
||||
S _CLRERRCNT DefE665
|
||||
S _GPIFTCB0 DefE6D1
|
||||
S _EP8GPIFPFSTOP DefE6EB
|
||||
S _REVCTL DefE60B
|
||||
S _ERRCNTLIM DefE664
|
||||
S _GPIFTCB1 DefE6D0
|
||||
S _TL0 Def008A
|
||||
S _APTR1H Def009A
|
||||
S _SM0 Def009F
|
||||
S _UART230 DefE608
|
||||
S _GPIFTCB2 DefE6CF
|
||||
S _TL1 Def008B
|
||||
S _A0 Def0080
|
||||
S _SM1 Def009E
|
||||
S _GPIFTCB3 DefE6CE
|
||||
S _UDMACRCQUAL DefE67F
|
||||
S _TL2 Def00CC
|
||||
S _A1 Def0081
|
||||
S _SM2 Def009D
|
||||
S _FL Def00D1
|
||||
S _EP68FIFOFLGS Def00AC
|
||||
S _A2 Def0082
|
||||
S _PS0 Def00BC
|
||||
S _I2DAT DefE679
|
||||
S _APTR1L Def009B
|
||||
S _A3 Def0083
|
||||
S _D0 Def00B0
|
||||
S _PT0 Def00B9
|
||||
S _PS1 Def00BE
|
||||
S _BPADDRH DefE606
|
||||
S _A4 Def0084
|
||||
S _D1 Def00B1
|
||||
S _PT1 Def00BB
|
||||
S _RS0 Def00D3
|
||||
S _USBIRQ DefE65D
|
||||
S _PORTACFG DefE670
|
||||
S _FLOWSTBEDGE DefE6CC
|
||||
S _A5 Def0085
|
||||
S _TR0 Def008C
|
||||
S _D2 Def00B2
|
||||
S _PT2 Def00BD
|
||||
S _RS1 Def00D4
|
||||
S _F0 Def00D5
|
||||
S _PINFLAGSAB DefE602
|
||||
S _EP2FIFOFLGS DefE6A7
|
||||
S _A6 Def0086
|
||||
S _TR1 Def008E
|
||||
S _D3 Def00B3
|
||||
S _USBIE DefE65C
|
||||
S _PORTCCFG DefE671
|
||||
S _EP2FIFOBCH DefE6AB
|
||||
S _A7 Def0087
|
||||
S _D4 Def00B4
|
||||
S _PX0 Def00B8
|
||||
S _TR2 Def00CA
|
||||
S _ERESI Def00DD
|
||||
S _EIUSB Def00E8
|
||||
S _hook_sv_PARM_2 Ref0000
|
||||
S _BPADDRL DefE607
|
||||
S _EP4FIFOFLGS DefE6A8
|
||||
S _GPIFCTLCFG DefE6C3
|
||||
S _FLOWSTATE DefE6C6
|
||||
S _IP Def00B8
|
||||
S _D5 Def00B5
|
||||
S _PX1 Def00BA
|
||||
S _REVID DefE60A
|
||||
S _PORTECFG DefE672
|
||||
S _EP4FIFOBCH DefE6AD
|
||||
S _GPIFIDLECS DefE6C1
|
||||
S _FLOWHOLDOFF DefE6CA
|
||||
S _EP1INBUF DefE7C0
|
||||
S _PSW Def00D0
|
||||
S _D6 Def00B6
|
||||
S _PINFLAGSCD DefE603
|
||||
S _EP2FIFOCFG DefE618
|
||||
S _XAUTODAT1 DefE67B
|
||||
S _EP0CS DefE6A0
|
||||
S _EP6FIFOFLGS DefE6A9
|
||||
S _EP1OUTBUF DefE780
|
||||
S _RI Def0098
|
||||
S _D7 Def00B7
|
||||
S _XAUTODAT2 DefE67C
|
||||
S _EP2FIFOBCL DefE6AC
|
||||
S _EP6FIFOBCH DefE6AF
|
||||
S _GPIFTRIG Def00BB
|
||||
S _CY Def00D7
|
||||
S _EP4FIFOCFG DefE619
|
||||
S _INPKTEND DefE648
|
||||
S _EP2CS DefE6A3
|
||||
S _EP8FIFOFLGS DefE6AA
|
||||
S _TI Def0099
|
||||
S _CPUCS DefE600
|
||||
S _OUTPKTEND DefE649
|
||||
S _I2CTL DefE67A
|
||||
S _EP4FIFOBCL DefE6AE
|
||||
S _EP8FIFOBCH DefE6B1
|
||||
S _XGPIFSGLDATLNOX DefE6F2
|
||||
S _EP6FIFOCFG DefE61A
|
||||
S _USBERRIRQ DefE663
|
||||
S _EP4CS DefE6A4
|
||||
S _EIEX4 Def00EA
|
||||
S _USBCS DefE680
|
||||
S _EP6FIFOBCL DefE6B0
|
||||
S _SBUF0 Def0099
|
||||
S _EIEX5 Def00EB
|
||||
A _CODE size 0 flags 0 addr 0
|
||||
A RSEG size 0 flags 0 addr 0
|
||||
A REG_BANK_0 size 8 flags 4 addr 0
|
||||
A DSEG size 0 flags 0 addr 0
|
||||
A OSEG size 0 flags 4 addr 0
|
||||
A ISEG size 0 flags 0 addr 0
|
||||
A IABS size 0 flags 8 addr 0
|
||||
A BSEG size 0 flags 80 addr 0
|
||||
A PSEG size 0 flags 50 addr 0
|
||||
A XSEG size 0 flags 40 addr 0
|
||||
A XABS size 0 flags 48 addr 0
|
||||
A HOME size 0 flags 20 addr 0
|
||||
A GSINIT0 size 0 flags 20 addr 0
|
||||
A GSINIT1 size 0 flags 20 addr 0
|
||||
A GSINIT2 size 0 flags 20 addr 0
|
||||
A GSINIT3 size 0 flags 20 addr 0
|
||||
A GSINIT4 size 0 flags 20 addr 0
|
||||
A GSINIT5 size 0 flags 20 addr 0
|
||||
A GSINIT size 0 flags 20 addr 0
|
||||
A GSFINAL size 0 flags 20 addr 0
|
||||
A CSEG size 1C flags 20 addr 0
|
||||
S _hook_timer_tick Def0000
|
||||
A CONST size 0 flags 20 addr 0
|
||||
A CABS size 0 flags 28 addr 0
|
||||
T 00 00
|
||||
R 00 00 00 02
|
||||
T 00 00
|
||||
R 00 00 00 14
|
||||
T 00 00 AA 82 AB 83 C2 AD 8A 00 00 00 8B 00 00 01
|
||||
R 00 00 00 14 F1 23 09 01 14 F1 23 0D 01 14
|
||||
T 00 0A 75 82 2B 12 00 00 75 CB 63 75 CA C0 75 C8
|
||||
R 00 00 00 14 02 06 00 66
|
||||
T 00 18 04 D2 AD 22
|
||||
R 00 00 00 14
|
||||
701
firmware/GN3S_v2/lib/timer.sym
Normal file
701
firmware/GN3S_v2/lib/timer.sym
Normal file
@@ -0,0 +1,701 @@
|
||||
ASxxxx Assembler V01.70 + NoICE + SDCC mods + Flat24 Feb-1999 (Intel 8051), page 1.
|
||||
|
||||
Symbol Table
|
||||
|
||||
A 00D6
|
||||
AC 00D6
|
||||
ACC 00E0
|
||||
ACC.0 00E0
|
||||
ACC.1 00E1
|
||||
ACC.2 00E2
|
||||
ACC.3 00E3
|
||||
ACC.4 00E4
|
||||
ACC.5 00E5
|
||||
ACC.6 00E6
|
||||
ACC.7 00E7
|
||||
B 00F0
|
||||
B.0 00F0
|
||||
B.1 00F1
|
||||
B.2 00F2
|
||||
B.3 00F3
|
||||
B.4 00F4
|
||||
B.5 00F5
|
||||
B.6 00F6
|
||||
B.7 00F7
|
||||
CPRL2 00C8
|
||||
CT2 00C9
|
||||
CY 00D7
|
||||
DPH 0083
|
||||
DPL 0082
|
||||
EA 00AF
|
||||
ES 00AC
|
||||
ET0 00A9
|
||||
ET1 00AB
|
||||
ET2 00AD
|
||||
EX0 00A8
|
||||
EX1 00AA
|
||||
EXEN2 00CB
|
||||
EXF2 00CE
|
||||
F0 00D5
|
||||
IE 00A8
|
||||
IE.0 00A8
|
||||
IE.1 00A9
|
||||
IE.2 00AA
|
||||
IE.3 00AB
|
||||
IE.4 00AC
|
||||
IE.5 00AD
|
||||
IE.7 00AF
|
||||
IE0 0089
|
||||
IE1 008B
|
||||
INT0 00B2
|
||||
INT1 00B3
|
||||
IP 00B8
|
||||
IP.0 00B8
|
||||
IP.1 00B9
|
||||
IP.2 00BA
|
||||
IP.3 00BB
|
||||
IP.4 00BC
|
||||
IP.5 00BD
|
||||
IT0 0088
|
||||
IT1 008A
|
||||
OV 00D2
|
||||
P 00D0
|
||||
P0 0080
|
||||
P0.0 0080
|
||||
P0.1 0081
|
||||
P0.2 0082
|
||||
P0.3 0083
|
||||
P0.4 0084
|
||||
P0.5 0085
|
||||
P0.6 0086
|
||||
P0.7 0087
|
||||
P1 0090
|
||||
P1.0 0090
|
||||
P1.1 0091
|
||||
P1.2 0092
|
||||
P1.3 0093
|
||||
P1.4 0094
|
||||
P1.5 0095
|
||||
P1.6 0096
|
||||
P1.7 0097
|
||||
P2 00A0
|
||||
P2.0 00A0
|
||||
P2.1 00A1
|
||||
P2.2 00A2
|
||||
P2.3 00A3
|
||||
P2.4 00A4
|
||||
P2.5 00A5
|
||||
P2.6 00A6
|
||||
P2.7 00A7
|
||||
P3 00B0
|
||||
P3.0 00B0
|
||||
P3.1 00B1
|
||||
P3.2 00B2
|
||||
P3.3 00B3
|
||||
P3.4 00B4
|
||||
P3.5 00B5
|
||||
P3.6 00B6
|
||||
P3.7 00B7
|
||||
PCON 0087
|
||||
PS 00BC
|
||||
PSW 00D0
|
||||
PSW.0 00D0
|
||||
PSW.1 00D1
|
||||
PSW.2 00D2
|
||||
PSW.3 00D3
|
||||
PSW.4 00D4
|
||||
PSW.5 00D5
|
||||
PSW.6 00D6
|
||||
PSW.7 00D7
|
||||
PT0 00B9
|
||||
PT1 00BB
|
||||
PT2 00BD
|
||||
PX0 00B8
|
||||
PX1 00BA
|
||||
RB8 009A
|
||||
RCAP2H 00CB
|
||||
RCAP2L 00CA
|
||||
RCLK 00CD
|
||||
REN 009C
|
||||
RI 0098
|
||||
RS0 00D3
|
||||
RS1 00D4
|
||||
RXD 00B0
|
||||
SBUF 0099
|
||||
SCON 0098
|
||||
SCON.0 0098
|
||||
SCON.1 0099
|
||||
SCON.2 009A
|
||||
SCON.3 009B
|
||||
SCON.4 009C
|
||||
SCON.5 009D
|
||||
SCON.6 009E
|
||||
SCON.7 009F
|
||||
SM0 009F
|
||||
SM1 009E
|
||||
SM2 009D
|
||||
SP 0081
|
||||
T2CON 00C8
|
||||
T2CON.0 00C8
|
||||
T2CON.1 00C9
|
||||
T2CON.2 00CA
|
||||
T2CON.3 00CB
|
||||
T2CON.4 00CC
|
||||
T2CON.5 00CD
|
||||
T2CON.6 00CE
|
||||
T2CON.7 00CF
|
||||
TB8 009B
|
||||
TCLK 00CC
|
||||
TCON 0088
|
||||
TCON.0 0088
|
||||
TCON.1 0089
|
||||
TCON.2 008A
|
||||
TCON.3 008B
|
||||
TCON.4 008C
|
||||
TCON.5 008D
|
||||
TCON.6 008E
|
||||
TCON.7 008F
|
||||
TF0 008D
|
||||
TF1 008F
|
||||
TF2 00CF
|
||||
TH0 008C
|
||||
TH1 008D
|
||||
TH2 00CD
|
||||
TI 0099
|
||||
TL0 008A
|
||||
TL1 008B
|
||||
TL2 00CC
|
||||
TMOD 0089
|
||||
TR0 008C
|
||||
TR1 008E
|
||||
TR2 00CA
|
||||
TXD 00B1
|
||||
_A0 = 0080 G
|
||||
_A1 = 0081 G
|
||||
_A2 = 0082 G
|
||||
_A3 = 0083 G
|
||||
_A4 = 0084 G
|
||||
_A5 = 0085 G
|
||||
_A6 = 0086 G
|
||||
_A7 = 0087 G
|
||||
_AC = 00D6 G
|
||||
_ACC = 00E0 G
|
||||
_APTR1H = 009A G
|
||||
_APTR1L = 009B G
|
||||
_AUTODAT1 = 009C G
|
||||
_AUTODAT2 = 009F G
|
||||
_AUTOPTRH2 = 009D G
|
||||
_AUTOPTRL2 = 009E G
|
||||
_AUTOPTRSETUP = 00AF G
|
||||
_B = 00F0 G
|
||||
_BPADDRH = E606 G
|
||||
_BPADDRL = E607 G
|
||||
_BREAKPT = E605 G
|
||||
_CKCON = 008E G
|
||||
_CLRERRCNT = E665 G
|
||||
_CPUCS = E600 G
|
||||
_CP_RL2 = 00C8 G
|
||||
_CT1 = E6FB G
|
||||
_CT2 = E6FC G
|
||||
_CT3 = E6FD G
|
||||
_CT4 = E6FE G
|
||||
_CY = 00D7 G
|
||||
_C_T2 = 00C9 G
|
||||
_D0 = 00B0 G
|
||||
_D1 = 00B1 G
|
||||
_D2 = 00B2 G
|
||||
_D3 = 00B3 G
|
||||
_D4 = 00B4 G
|
||||
_D5 = 00B5 G
|
||||
_D6 = 00B6 G
|
||||
_D7 = 00B7 G
|
||||
_DBUG = E6F8 G
|
||||
_DPH = 0083 G
|
||||
_DPH1 = 0085 G
|
||||
_DPL = 0082 G
|
||||
_DPL1 = 0084 G
|
||||
_DPS = 0086 G
|
||||
_EA = 00AF G
|
||||
_EI2C = 00E9 G
|
||||
_EICON = 00D8 G
|
||||
_EIE = 00E8 G
|
||||
_EIEX4 = 00EA G
|
||||
_EIEX5 = 00EB G
|
||||
_EIEX6 = 00EC G
|
||||
_EIP = 00F8 G
|
||||
_EIPX4 = 00FA G
|
||||
_EIPX5 = 00FB G
|
||||
_EIPX6 = 00FC G
|
||||
_EIUSB = 00E8 G
|
||||
_EP01STAT = 00BA G
|
||||
_EP0BCH = E68A G
|
||||
_EP0BCL = E68B G
|
||||
_EP0BUF = E740 G
|
||||
_EP0CS = E6A0 G
|
||||
_EP1INBC = E68F G
|
||||
_EP1INBUF = E7C0 G
|
||||
_EP1INCFG = E611 G
|
||||
_EP1INCS = E6A2 G
|
||||
_EP1OUTBC = E68D G
|
||||
_EP1OUTBUF = E780 G
|
||||
_EP1OUTCFG = E610 G
|
||||
_EP1OUTCS = E6A1 G
|
||||
_EP2468STAT = 00AA G
|
||||
_EP24FIFOFLGS = 00AB G
|
||||
_EP2AUTOINLENH = E620 G
|
||||
_EP2AUTOINLENL = E621 G
|
||||
_EP2BCH = E690 G
|
||||
_EP2BCL = E691 G
|
||||
_EP2CFG = E612 G
|
||||
_EP2CS = E6A3 G
|
||||
_EP2FIFOBCH = E6AB G
|
||||
_EP2FIFOBCL = E6AC G
|
||||
_EP2FIFOBUF = F000 G
|
||||
_EP2FIFOCFG = E618 G
|
||||
_EP2FIFOFLGS = E6A7 G
|
||||
_EP2FIFOIE = E650 G
|
||||
_EP2FIFOIRQ = E651 G
|
||||
_EP2FIFOPFH = E630 G
|
||||
_EP2FIFOPFL = E631 G
|
||||
_EP2GPIFFLGSEL = E6D2 G
|
||||
_EP2GPIFPFSTOP = E6D3 G
|
||||
_EP2GPIFTRIG = E6D4 G
|
||||
_EP2ISOINPKTS = E640 G
|
||||
_EP4AUTOINLENH = E622 G
|
||||
_EP4AUTOINLENL = E623 G
|
||||
_EP4BCH = E694 G
|
||||
_EP4BCL = E695 G
|
||||
_EP4CFG = E613 G
|
||||
_EP4CS = E6A4 G
|
||||
_EP4FIFOBCH = E6AD G
|
||||
_EP4FIFOBCL = E6AE G
|
||||
_EP4FIFOBUF = F400 G
|
||||
_EP4FIFOCFG = E619 G
|
||||
_EP4FIFOFLGS = E6A8 G
|
||||
_EP4FIFOIE = E652 G
|
||||
_EP4FIFOIRQ = E653 G
|
||||
_EP4FIFOPFH = E632 G
|
||||
_EP4FIFOPFL = E633 G
|
||||
_EP4GPIFFLGSEL = E6DA G
|
||||
_EP4GPIFPFSTOP = E6DB G
|
||||
_EP4GPIFTRIG = E6DC G
|
||||
_EP4ISOINPKTS = E641 G
|
||||
_EP68FIFOFLGS = 00AC G
|
||||
_EP6AUTOINLENH = E624 G
|
||||
_EP6AUTOINLENL = E625 G
|
||||
_EP6BCH = E698 G
|
||||
_EP6BCL = E699 G
|
||||
_EP6CFG = E614 G
|
||||
_EP6CS = E6A5 G
|
||||
_EP6FIFOBCH = E6AF G
|
||||
_EP6FIFOBCL = E6B0 G
|
||||
_EP6FIFOBUF = F800 G
|
||||
_EP6FIFOCFG = E61A G
|
||||
_EP6FIFOFLGS = E6A9 G
|
||||
_EP6FIFOIE = E654 G
|
||||
_EP6FIFOIRQ = E655 G
|
||||
_EP6FIFOPFH = E634 G
|
||||
_EP6FIFOPFL = E635 G
|
||||
_EP6GPIFFLGSEL = E6E2 G
|
||||
_EP6GPIFPFSTOP = E6E3 G
|
||||
_EP6GPIFTRIG = E6E4 G
|
||||
_EP6ISOINPKTS = E642 G
|
||||
_EP8AUTOINLENH = E626 G
|
||||
_EP8AUTOINLENL = E627 G
|
||||
_EP8BCH = E69C G
|
||||
_EP8BCL = E69D G
|
||||
_EP8CFG = E615 G
|
||||
_EP8CS = E6A6 G
|
||||
_EP8FIFOBCH = E6B1 G
|
||||
_EP8FIFOBCL = E6B2 G
|
||||
_EP8FIFOBUF = FC00 G
|
||||
_EP8FIFOCFG = E61B G
|
||||
_EP8FIFOFLGS = E6AA G
|
||||
_EP8FIFOIE = E656 G
|
||||
_EP8FIFOIRQ = E657 G
|
||||
_EP8FIFOPFH = E636 G
|
||||
_EP8FIFOPFL = E637 G
|
||||
_EP8GPIFFLGSEL = E6EA G
|
||||
_EP8GPIFPFSTOP = E6EB G
|
||||
_EP8GPIFTRIG = E6EC G
|
||||
_EP8ISOINPKTS = E643 G
|
||||
_EPIE = E65E G
|
||||
_EPIRQ = E65F G
|
||||
_ERESI = 00DD G
|
||||
_ERRCNTLIM = E664 G
|
||||
_ES0 = 00AC G
|
||||
_ES1 = 00AE G
|
||||
_ET0 = 00A9 G
|
||||
_ET1 = 00AB G
|
||||
_ET2 = 00AD G
|
||||
_EX0 = 00A8 G
|
||||
_EX1 = 00AA G
|
||||
_EXEN2 = 00CB G
|
||||
_EXF2 = 00CE G
|
||||
_EXIF = 0091 G
|
||||
_F0 = 00D5 G
|
||||
_FIFOPINPOLAR = E609 G
|
||||
_FIFORESET = E604 G
|
||||
_FL = 00D1 G
|
||||
_FLOWEQ0CTL = E6C8 G
|
||||
_FLOWEQ1CTL = E6C9 G
|
||||
_FLOWHOLDOFF = E6CA G
|
||||
_FLOWLOGIC = E6C7 G
|
||||
_FLOWSTATE = E6C6 G
|
||||
_FLOWSTB = E6CB G
|
||||
_FLOWSTBEDGE = E6CC G
|
||||
_FLOWSTBHPERIOD = E6CD G
|
||||
_FNADDR = E687 G
|
||||
_GPIFABORT = E6F5 G
|
||||
_GPIFADRH = E6C4 G
|
||||
_GPIFADRL = E6C5 G
|
||||
_GPIFCTLCFG = E6C3 G
|
||||
_GPIFHOLDAMOUNT = E60C G
|
||||
_GPIFIDLECS = E6C1 G
|
||||
_GPIFIDLECTL = E6C2 G
|
||||
_GPIFIE = E660 G
|
||||
_GPIFIRQ = E661 G
|
||||
_GPIFREADYCFG = E6F3 G
|
||||
_GPIFREADYSTAT = E6F4 G
|
||||
_GPIFSGLDATH = 00BD G
|
||||
_GPIFSGLDATLNOX = 00BF G
|
||||
_GPIFSGLDATLX = 00BE G
|
||||
_GPIFTCB0 = E6D1 G
|
||||
_GPIFTCB1 = E6D0 G
|
||||
_GPIFTCB2 = E6CF G
|
||||
_GPIFTCB3 = E6CE G
|
||||
_GPIFTRIG = 00BB G
|
||||
_GPIFWFSELECT = E6C0 G
|
||||
_GPIF_WAVE_DATA = E400 G
|
||||
_I2CS = E678 G
|
||||
_I2CTL = E67A G
|
||||
_I2DAT = E679 G
|
||||
_IBNIE = E658 G
|
||||
_IBNIRQ = E659 G
|
||||
_IE = 00A8 G
|
||||
_IE0 = 0089 G
|
||||
_IE1 = 008B G
|
||||
_IFCONFIG = E601 G
|
||||
_INPKTEND = E648 G
|
||||
_INT2CLR = 00A1 G
|
||||
_INT2IVEC = E666 G
|
||||
_INT4CLR = 00A2 G
|
||||
_INT4IVEC = E667 G
|
||||
_INT6 = 00DB G
|
||||
_INTSETUP = E668 G
|
||||
_IOA = 0080 G
|
||||
_IOB = 0090 G
|
||||
_IOC = 00A0 G
|
||||
_IOD = 00B0 G
|
||||
_IOE = 00B1 G
|
||||
_IP = 00B8 G
|
||||
_IT0 = 0088 G
|
||||
_IT1 = 008A G
|
||||
_MICROFRAME = E686 G
|
||||
_MPAGE = 0092 G
|
||||
_NAKIE = E65A G
|
||||
_NAKIRQ = E65B G
|
||||
_OEA = 00B2 G
|
||||
_OEB = 00B3 G
|
||||
_OEC = 00B4 G
|
||||
_OED = 00B5 G
|
||||
_OEE = 00B6 G
|
||||
_OUTPKTEND = E649 G
|
||||
_OV = 00D2 G
|
||||
_P = 00D0 G
|
||||
_PCON = 0087 G
|
||||
_PI2C = 00F9 G
|
||||
_PINFLAGSAB = E602 G
|
||||
_PINFLAGSCD = E603 G
|
||||
_PORTACFG = E670 G
|
||||
_PORTCCFG = E671 G
|
||||
_PORTECFG = E672 G
|
||||
_PS0 = 00BC G
|
||||
_PS1 = 00BE G
|
||||
_PSW = 00D0 G
|
||||
_PT0 = 00B9 G
|
||||
_PT1 = 00BB G
|
||||
_PT2 = 00BD G
|
||||
_PUSB = 00F8 G
|
||||
_PX0 = 00B8 G
|
||||
_PX1 = 00BA G
|
||||
_RB8 = 009A G
|
||||
_RB81 = 00C2 G
|
||||
_RCAP2H = 00CB G
|
||||
_RCAP2L = 00CA G
|
||||
_RCLK = 00CD G
|
||||
_REN = 009C G
|
||||
_REN1 = 00C4 G
|
||||
_RESI = 00DC G
|
||||
_RES_WAVEDATA_END = E480 G
|
||||
_REVCTL = E60B G
|
||||
_REVID = E60A G
|
||||
_RI = 0098 G
|
||||
_RI1 = 00C0 G
|
||||
_RS0 = 00D3 G
|
||||
_RS1 = 00D4 G
|
||||
_SBUF0 = 0099 G
|
||||
_SBUF1 = 00C1 G
|
||||
_SCON0 = 0098 G
|
||||
_SCON1 = 00C0 G
|
||||
_SEL = 0086 G
|
||||
_SETUPDAT = E6B8 G
|
||||
_SM0 = 009F G
|
||||
_SM01 = 00C7 G
|
||||
_SM1 = 009E G
|
||||
_SM11 = 00C6 G
|
||||
_SM2 = 009D G
|
||||
_SM21 = 00C5 G
|
||||
_SMOD1 = 00DF G
|
||||
_SP = 0081 G
|
||||
_SUDPTRCTL = E6B5 G
|
||||
_SUDPTRH = E6B3 G
|
||||
_SUDPTRL = E6B4 G
|
||||
_SUSPEND = E681 G
|
||||
_T2CON = 00C8 G
|
||||
_TB8 = 009B G
|
||||
_TB81 = 00C3 G
|
||||
_TCLK = 00CC G
|
||||
_TCON = 0088 G
|
||||
_TESTCFG = E6F9 G
|
||||
_TF0 = 008D G
|
||||
_TF1 = 008F G
|
||||
_TF2 = 00CF G
|
||||
_TH0 = 008C G
|
||||
_TH1 = 008D G
|
||||
_TH2 = 00CD G
|
||||
_TI = 0099 G
|
||||
_TI1 = 00C1 G
|
||||
_TL0 = 008A G
|
||||
_TL1 = 008B G
|
||||
_TL2 = 00CC G
|
||||
_TMOD = 0089 G
|
||||
_TOGCTL = E683 G
|
||||
_TR0 = 008C G
|
||||
_TR1 = 008E G
|
||||
_TR2 = 00CA G
|
||||
_UART230 = E608 G
|
||||
_UDMACRCH = E67D G
|
||||
_UDMACRCL = E67E G
|
||||
_UDMACRCQUAL = E67F G
|
||||
_USBCS = E680 G
|
||||
_USBERRIE = E662 G
|
||||
_USBERRIRQ = E663 G
|
||||
_USBFRAMEH = E684 G
|
||||
_USBFRAMEL = E685 G
|
||||
_USBIE = E65C G
|
||||
_USBIRQ = E65D G
|
||||
_USBTEST = E6FA G
|
||||
_WAKEUPCS = E682 G
|
||||
_XAUTODAT1 = E67B G
|
||||
_XAUTODAT2 = E67C G
|
||||
_XGPIFSGLDATH = E6F0 G
|
||||
_XGPIFSGLDATLNOX = E6F2 G
|
||||
_XGPIFSGLDATLX = E6F1 G
|
||||
_hook_sv **** GX
|
||||
_hook_sv_PARM_2 **** GX
|
||||
14 _hook_timer_tick 0000 GR
|
||||
a 00D6
|
||||
ac 00D6
|
||||
acc 00E0
|
||||
acc.0 00E0
|
||||
acc.1 00E1
|
||||
acc.2 00E2
|
||||
acc.3 00E3
|
||||
acc.4 00E4
|
||||
acc.5 00E5
|
||||
acc.6 00E6
|
||||
acc.7 00E7
|
||||
ar0 = 0000
|
||||
ar1 = 0001
|
||||
ar2 = 0002
|
||||
ar3 = 0003
|
||||
ar4 = 0004
|
||||
ar5 = 0005
|
||||
ar6 = 0006
|
||||
ar7 = 0007
|
||||
b 00F0
|
||||
b.0 00F0
|
||||
b.1 00F1
|
||||
b.2 00F2
|
||||
b.3 00F3
|
||||
b.4 00F4
|
||||
b.5 00F5
|
||||
b.6 00F6
|
||||
b.7 00F7
|
||||
cprl2 00C8
|
||||
ct2 00C9
|
||||
cy 00D7
|
||||
dph 0083
|
||||
dpl 0082
|
||||
ea 00AF
|
||||
es 00AC
|
||||
et0 00A9
|
||||
et1 00AB
|
||||
et2 00AD
|
||||
ex0 00A8
|
||||
ex1 00AA
|
||||
exen2 00CB
|
||||
exf2 00CE
|
||||
f0 00D5
|
||||
ie 00A8
|
||||
ie.0 00A8
|
||||
ie.1 00A9
|
||||
ie.2 00AA
|
||||
ie.3 00AB
|
||||
ie.4 00AC
|
||||
ie.5 00AD
|
||||
ie.7 00AF
|
||||
ie0 0089
|
||||
ie1 008B
|
||||
int0 00B2
|
||||
int1 00B3
|
||||
ip 00B8
|
||||
ip.0 00B8
|
||||
ip.1 00B9
|
||||
ip.2 00BA
|
||||
ip.3 00BB
|
||||
ip.4 00BC
|
||||
ip.5 00BD
|
||||
it0 0088
|
||||
it1 008A
|
||||
ov 00D2
|
||||
p 00D0
|
||||
p0 0080
|
||||
p0.0 0080
|
||||
p0.1 0081
|
||||
p0.2 0082
|
||||
p0.3 0083
|
||||
p0.4 0084
|
||||
p0.5 0085
|
||||
p0.6 0086
|
||||
p0.7 0087
|
||||
p1 0090
|
||||
p1.0 0090
|
||||
p1.1 0091
|
||||
p1.2 0092
|
||||
p1.3 0093
|
||||
p1.4 0094
|
||||
p1.5 0095
|
||||
p1.6 0096
|
||||
p1.7 0097
|
||||
p2 00A0
|
||||
p2.0 00A0
|
||||
p2.1 00A1
|
||||
p2.2 00A2
|
||||
p2.3 00A3
|
||||
p2.4 00A4
|
||||
p2.5 00A5
|
||||
p2.6 00A6
|
||||
p2.7 00A7
|
||||
p3 00B0
|
||||
p3.0 00B0
|
||||
p3.1 00B1
|
||||
p3.2 00B2
|
||||
p3.3 00B3
|
||||
p3.4 00B4
|
||||
p3.5 00B5
|
||||
p3.6 00B6
|
||||
p3.7 00B7
|
||||
pcon 0087
|
||||
ps 00BC
|
||||
psw 00D0
|
||||
psw.0 00D0
|
||||
psw.1 00D1
|
||||
psw.2 00D2
|
||||
psw.3 00D3
|
||||
psw.4 00D4
|
||||
psw.5 00D5
|
||||
psw.6 00D6
|
||||
psw.7 00D7
|
||||
pt0 00B9
|
||||
pt1 00BB
|
||||
pt2 00BD
|
||||
px0 00B8
|
||||
px1 00BA
|
||||
rb8 009A
|
||||
rcap2h 00CB
|
||||
rcap2l 00CA
|
||||
rclk 00CD
|
||||
ren 009C
|
||||
ri 0098
|
||||
rs0 00D3
|
||||
rs1 00D4
|
||||
rxd 00B0
|
||||
sbuf 0099
|
||||
scon 0098
|
||||
scon.0 0098
|
||||
scon.1 0099
|
||||
scon.2 009A
|
||||
scon.3 009B
|
||||
scon.4 009C
|
||||
scon.5 009D
|
||||
scon.6 009E
|
||||
scon.7 009F
|
||||
sm0 009F
|
||||
sm1 009E
|
||||
sm2 009D
|
||||
sp 0081
|
||||
t2con 00C8
|
||||
t2con.0 00C8
|
||||
t2con.1 00C9
|
||||
t2con.2 00CA
|
||||
t2con.3 00CB
|
||||
t2con.4 00CC
|
||||
t2con.5 00CD
|
||||
t2con.6 00CE
|
||||
t2con.7 00CF
|
||||
tb8 009B
|
||||
tclk 00CC
|
||||
tcon 0088
|
||||
tcon.0 0088
|
||||
tcon.1 0089
|
||||
tcon.2 008A
|
||||
tcon.3 008B
|
||||
tcon.4 008C
|
||||
tcon.5 008D
|
||||
tcon.6 008E
|
||||
tcon.7 008F
|
||||
tf0 008D
|
||||
tf1 008F
|
||||
tf2 00CF
|
||||
th0 008C
|
||||
th1 008D
|
||||
th2 00CD
|
||||
ti 0099
|
||||
tl0 008A
|
||||
tl1 008B
|
||||
tl2 00CC
|
||||
tmod 0089
|
||||
tr0 008C
|
||||
tr1 008E
|
||||
tr2 00CA
|
||||
txd 00B1
|
||||
|
||||
ASxxxx Assembler V01.70 + NoICE + SDCC mods + Flat24 Feb-1999 (Intel 8051), page 2.
|
||||
|
||||
Area Table
|
||||
|
||||
0 _CODE size 0 flags 0
|
||||
1 RSEG size 0 flags 0
|
||||
2 REG_BANK_0 size 8 flags 4
|
||||
3 DSEG size 0 flags 0
|
||||
4 OSEG size 0 flags 4
|
||||
5 ISEG size 0 flags 0
|
||||
6 IABS size 0 flags 8
|
||||
7 BSEG size 0 flags 80
|
||||
8 PSEG size 0 flags 50
|
||||
9 XSEG size 0 flags 40
|
||||
A XABS size 0 flags 48
|
||||
B HOME size 0 flags 20
|
||||
C GSINIT0 size 0 flags 20
|
||||
D GSINIT1 size 0 flags 20
|
||||
E GSINIT2 size 0 flags 20
|
||||
F GSINIT3 size 0 flags 20
|
||||
10 GSINIT4 size 0 flags 20
|
||||
11 GSINIT5 size 0 flags 20
|
||||
12 GSINIT size 0 flags 20
|
||||
13 GSFINAL size 0 flags 20
|
||||
14 CSEG size 1C flags 20
|
||||
15 CONST size 0 flags 20
|
||||
16 CABS size 0 flags 28
|
||||
1595
firmware/GN3S_v2/lib/usb_common.asm
Normal file
1595
firmware/GN3S_v2/lib/usb_common.asm
Normal file
File diff suppressed because it is too large
Load Diff
405
firmware/GN3S_v2/lib/usb_common.c
Normal file
405
firmware/GN3S_v2/lib/usb_common.c
Normal file
@@ -0,0 +1,405 @@
|
||||
/*
|
||||
* Code from: USRP - Universal Software Radio Peripheral (GNU Radio)
|
||||
*
|
||||
* Initial modifications by:
|
||||
*
|
||||
* Stephan Esterhuizen, Aerospace Engineering Sciences
|
||||
* University of Colorado at Boulder
|
||||
* Boulder CO, USA
|
||||
*
|
||||
* Further modifications for use with the SiGe USB module to accompany
|
||||
* the textbook: "A Software-Defined GPS and Galileo Receiver: A
|
||||
* Single-Frequency Approach" by Kai Borre, Dennis Akos, et.al. by:
|
||||
*
|
||||
* Marcus Junered, GNSS Research Group
|
||||
* Lulea University of Technology
|
||||
* Lulea, Sweden
|
||||
*
|
||||
* http://ccar.colorado.edu/gnss
|
||||
*
|
||||
* ---------------------------------------------------------------------
|
||||
*
|
||||
* GN3S - GNSS IF Streamer for Windows
|
||||
* Copyright (C) 2006 Marcus Junered
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#include "usb_common.h"
|
||||
#include "fx2regs.h"
|
||||
#include "syncdelay.h"
|
||||
#include "fx2utils.h"
|
||||
#include "isr.h"
|
||||
#include "usb_descriptors.h"
|
||||
#include "usb_requests.h"
|
||||
#include "gn3s_regs.h"
|
||||
|
||||
extern xdata char str0[];
|
||||
extern xdata char str1[];
|
||||
extern xdata char str2[];
|
||||
extern xdata char str3[];
|
||||
extern xdata char str4[];
|
||||
extern xdata char str5[];
|
||||
|
||||
#define bRequestType SETUPDAT[0]
|
||||
#define bRequest SETUPDAT[1]
|
||||
#define wValueL SETUPDAT[2]
|
||||
#define wValueH SETUPDAT[3]
|
||||
#define wIndexL SETUPDAT[4]
|
||||
#define wIndexH SETUPDAT[5]
|
||||
#define wLengthL SETUPDAT[6]
|
||||
#define wLengthH SETUPDAT[7]
|
||||
|
||||
#define MSB(x) (((unsigned short) x) >> 8)
|
||||
#define LSB(x) (((unsigned short) x) & 0xff)
|
||||
|
||||
volatile bit _usb_got_SUDAV;
|
||||
volatile bit _usb_rx_overrun;
|
||||
|
||||
unsigned char _usb_config = 0;
|
||||
unsigned char _usb_alt_setting = 0; // FIXME really 1/interface
|
||||
|
||||
xdata unsigned char *current_device_descr;
|
||||
xdata unsigned char *current_devqual_descr;
|
||||
xdata unsigned char *current_config_descr;
|
||||
xdata unsigned char *other_config_descr;
|
||||
|
||||
static void
|
||||
setup_descriptors (void)
|
||||
{
|
||||
if (USBCS & bmHSM){ // high speed mode
|
||||
current_device_descr = high_speed_device_descr;
|
||||
current_devqual_descr = high_speed_devqual_descr;
|
||||
current_config_descr = high_speed_config_descr;
|
||||
other_config_descr = full_speed_config_descr;
|
||||
}
|
||||
else {
|
||||
current_device_descr = full_speed_device_descr;
|
||||
current_devqual_descr = full_speed_devqual_descr;
|
||||
current_config_descr = full_speed_config_descr;
|
||||
other_config_descr = high_speed_config_descr;
|
||||
}
|
||||
|
||||
// whack the type fields
|
||||
// FIXME, may not be required.
|
||||
// current_config_descr[1] = DT_CONFIG;
|
||||
// other_config_descr[1] = DT_OTHER_SPEED;
|
||||
}
|
||||
|
||||
static void
|
||||
isr_SUDAV (void) interrupt
|
||||
{
|
||||
clear_usb_irq ();
|
||||
_usb_got_SUDAV = 1;
|
||||
//usb_handle_setup_packet();
|
||||
}
|
||||
|
||||
static void
|
||||
isr_USBRESET (void) interrupt
|
||||
{
|
||||
clear_usb_irq ();
|
||||
setup_descriptors ();
|
||||
}
|
||||
|
||||
static void
|
||||
isr_HIGHSPEED (void) interrupt
|
||||
{
|
||||
clear_usb_irq ();
|
||||
setup_descriptors ();
|
||||
}
|
||||
|
||||
void
|
||||
usb_install_handlers (void)
|
||||
{
|
||||
setup_descriptors (); // ensure that they're set before use
|
||||
|
||||
hook_uv (UV_SUDAV, (unsigned short) isr_SUDAV);
|
||||
hook_uv (UV_USBRESET, (unsigned short) isr_USBRESET);
|
||||
hook_uv (UV_HIGHSPEED, (unsigned short) isr_HIGHSPEED);
|
||||
|
||||
USBIE = bmSUDAV | bmURES | bmHSGRANT;
|
||||
}
|
||||
|
||||
// On the FX2 the only plausible endpoints are 0, 1, 2, 4, 6, 8
|
||||
// This doesn't check to see that they're enabled
|
||||
|
||||
unsigned char
|
||||
plausible_endpoint (unsigned char ep)
|
||||
{
|
||||
ep &= ~0x80; // ignore direction bit
|
||||
|
||||
if (ep > 8)
|
||||
return 0;
|
||||
|
||||
if (ep == 1)
|
||||
return 1;
|
||||
|
||||
return (ep & 0x1) == 0; // must be even
|
||||
}
|
||||
|
||||
// return pointer to control and status register for endpoint.
|
||||
// only called with plausible_endpoints
|
||||
|
||||
xdata volatile unsigned char *
|
||||
epcs (unsigned char ep)
|
||||
{
|
||||
if (ep == 0x01) // ep1 has different in and out CS regs
|
||||
return EP1OUTCS;
|
||||
|
||||
if (ep == 0x81)
|
||||
return EP1INCS;
|
||||
|
||||
ep &= ~0x80; // ignore direction bit
|
||||
|
||||
if (ep == 0x00) // ep0
|
||||
return EP0CS;
|
||||
|
||||
return EP2CS + (ep >> 1); // 2, 4, 6, 8 are consecutive
|
||||
}
|
||||
|
||||
void
|
||||
usb_handle_setup_packet (void)
|
||||
{
|
||||
_usb_got_SUDAV = 0;
|
||||
|
||||
// handle the standard requests...
|
||||
|
||||
switch (bRequestType & bmRT_TYPE_MASK){
|
||||
|
||||
case bmRT_TYPE_CLASS:
|
||||
case bmRT_TYPE_RESERVED:
|
||||
fx2_stall_ep0 (); // we don't handle these. indicate error
|
||||
break;
|
||||
|
||||
case bmRT_TYPE_VENDOR:
|
||||
// call the application code.
|
||||
// If it handles the command it returns non-zero
|
||||
|
||||
if (!app_vendor_cmd ())
|
||||
fx2_stall_ep0 ();
|
||||
break;
|
||||
|
||||
case bmRT_TYPE_STD:
|
||||
// these are the standard requests...
|
||||
|
||||
if ((bRequestType & bmRT_DIR_MASK) == bmRT_DIR_IN){
|
||||
|
||||
////////////////////////////////////
|
||||
// handle the IN requests
|
||||
////////////////////////////////////
|
||||
|
||||
switch (bRequest){
|
||||
|
||||
case RQ_GET_CONFIG:
|
||||
EP0BUF[0] = _usb_config; // FIXME app should handle
|
||||
EP0BCH = 0;
|
||||
EP0BCL = 1;
|
||||
break;
|
||||
|
||||
// --------------------------------
|
||||
|
||||
case RQ_GET_INTERFACE:
|
||||
EP0BUF[0] = _usb_alt_setting; // FIXME app should handle
|
||||
EP0BCH = 0;
|
||||
EP0BCL = 1;
|
||||
break;
|
||||
|
||||
// --------------------------------
|
||||
|
||||
case RQ_GET_DESCR:
|
||||
switch (wValueH){
|
||||
|
||||
case DT_DEVICE:
|
||||
SUDPTRH = MSB (current_device_descr);
|
||||
SUDPTRL = LSB (current_device_descr);
|
||||
break;
|
||||
|
||||
case DT_DEVQUAL:
|
||||
SUDPTRH = MSB (current_devqual_descr);
|
||||
SUDPTRL = LSB (current_devqual_descr);
|
||||
break;
|
||||
|
||||
case DT_CONFIG:
|
||||
if (0 && wValueL != 1) // FIXME only a single configuration
|
||||
fx2_stall_ep0 ();
|
||||
else {
|
||||
SUDPTRH = MSB (current_config_descr);
|
||||
SUDPTRL = LSB (current_config_descr);
|
||||
}
|
||||
break;
|
||||
|
||||
case DT_OTHER_SPEED:
|
||||
if (0 && wValueL != 1) // FIXME only a single configuration
|
||||
fx2_stall_ep0 ();
|
||||
else {
|
||||
SUDPTRH = MSB (other_config_descr);
|
||||
SUDPTRL = LSB (other_config_descr);
|
||||
}
|
||||
break;
|
||||
|
||||
case DT_STRING:
|
||||
if (wValueL >= nstring_descriptors)
|
||||
fx2_stall_ep0 ();
|
||||
else {
|
||||
xdata char *p = string_descriptors[wValueL];
|
||||
SUDPTRH = MSB (p);
|
||||
SUDPTRL = LSB (p);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
fx2_stall_ep0 (); // invalid request
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
// --------------------------------
|
||||
|
||||
case RQ_GET_STATUS:
|
||||
switch (bRequestType & bmRT_RECIP_MASK){
|
||||
case bmRT_RECIP_DEVICE:
|
||||
EP0BUF[0] = bmGSDA_SELF_POWERED; // FIXME app should handle
|
||||
EP0BUF[1] = 0;
|
||||
EP0BCH = 0;
|
||||
EP0BCL = 2;
|
||||
break;
|
||||
|
||||
case bmRT_RECIP_INTERFACE:
|
||||
EP0BUF[0] = 0;
|
||||
EP0BUF[1] = 0;
|
||||
EP0BCH = 0;
|
||||
EP0BCL = 2;
|
||||
break;
|
||||
|
||||
case bmRT_RECIP_ENDPOINT:
|
||||
if (plausible_endpoint (wIndexL)){
|
||||
EP0BUF[0] = *epcs (wIndexL) & bmEPSTALL;
|
||||
EP0BUF[1] = 0;
|
||||
EP0BCH = 0;
|
||||
EP0BCL = 2;
|
||||
}
|
||||
else
|
||||
fx2_stall_ep0 ();
|
||||
break;
|
||||
|
||||
default:
|
||||
fx2_stall_ep0 ();
|
||||
break;
|
||||
}
|
||||
|
||||
// --------------------------------
|
||||
|
||||
case RQ_SYNCH_FRAME: // not implemented
|
||||
default:
|
||||
fx2_stall_ep0 ();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
else {
|
||||
|
||||
////////////////////////////////////
|
||||
// handle the OUT requests
|
||||
////////////////////////////////////
|
||||
|
||||
switch (bRequest){
|
||||
|
||||
case RQ_SET_CONFIG:
|
||||
_usb_config = wValueL; // FIXME app should handle
|
||||
break;
|
||||
|
||||
case RQ_SET_INTERFACE:
|
||||
_usb_alt_setting = wValueL; // FIXME app should handle
|
||||
break;
|
||||
|
||||
// --------------------------------
|
||||
|
||||
case RQ_CLEAR_FEATURE:
|
||||
switch (bRequestType & bmRT_RECIP_MASK){
|
||||
|
||||
case bmRT_RECIP_DEVICE:
|
||||
switch (wValueL){
|
||||
case FS_DEV_REMOTE_WAKEUP:
|
||||
default:
|
||||
fx2_stall_ep0 ();
|
||||
}
|
||||
break;
|
||||
|
||||
case bmRT_RECIP_ENDPOINT:
|
||||
if (wValueL == FS_ENDPOINT_HALT && plausible_endpoint (wIndexL)){
|
||||
*epcs (wIndexL) &= ~bmEPSTALL;
|
||||
fx2_reset_data_toggle (wIndexL);
|
||||
}
|
||||
else
|
||||
fx2_stall_ep0 ();
|
||||
break;
|
||||
|
||||
default:
|
||||
fx2_stall_ep0 ();
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
// --------------------------------
|
||||
|
||||
case RQ_SET_FEATURE:
|
||||
switch (bRequestType & bmRT_RECIP_MASK){
|
||||
|
||||
case bmRT_RECIP_DEVICE:
|
||||
switch (wValueL){
|
||||
case FS_TEST_MODE:
|
||||
// hardware handles this after we complete SETUP phase handshake
|
||||
break;
|
||||
|
||||
case FS_DEV_REMOTE_WAKEUP:
|
||||
default:
|
||||
fx2_stall_ep0 ();
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case bmRT_RECIP_ENDPOINT:
|
||||
switch (wValueL){
|
||||
case FS_ENDPOINT_HALT:
|
||||
if (plausible_endpoint (wIndexL))
|
||||
*epcs (wIndexL) |= bmEPSTALL;
|
||||
else
|
||||
fx2_stall_ep0 ();
|
||||
break;
|
||||
|
||||
default:
|
||||
fx2_stall_ep0 ();
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
// --------------------------------
|
||||
|
||||
case RQ_SET_ADDRESS: // handled by fx2 hardware
|
||||
case RQ_SET_DESCR: // not implemented
|
||||
default:
|
||||
fx2_stall_ep0 ();
|
||||
}
|
||||
|
||||
}
|
||||
break;
|
||||
|
||||
} // bmRT_TYPE_MASK
|
||||
|
||||
// ack handshake phase of device request
|
||||
EP0CS |= bmHSNAK;
|
||||
}
|
||||
1595
firmware/GN3S_v2/lib/usb_common.lst
Normal file
1595
firmware/GN3S_v2/lib/usb_common.lst
Normal file
File diff suppressed because it is too large
Load Diff
839
firmware/GN3S_v2/lib/usb_common.rel
Normal file
839
firmware/GN3S_v2/lib/usb_common.rel
Normal file
@@ -0,0 +1,839 @@
|
||||
XH
|
||||
H 18 areas 15B global symbols
|
||||
M usb_common
|
||||
O -mmcs51 --model-small
|
||||
S _EP8FIFOCFG DefE61B
|
||||
S _EPIRQ DefE65F
|
||||
S _USBERRIE DefE662
|
||||
S _EP6CS DefE6A5
|
||||
S _GPIFHOLDAMOUNT DefE60C
|
||||
S _SBUF1 Def00C1
|
||||
S _EIEX6 Def00EC
|
||||
S _full_speed_device_descr Ref0000
|
||||
S _EP1INBC DefE68F
|
||||
S _EP8FIFOBCL DefE6B2
|
||||
S _DBUG DefE6F8
|
||||
S _B Def00F0
|
||||
S _EXEN2 Def00CB
|
||||
S _EPIE DefE65E
|
||||
S _WAKEUPCS DefE682
|
||||
S _EP1OUTBC DefE68D
|
||||
S _EP8CS DefE6A6
|
||||
S _EP2GPIFTRIG DefE6D4
|
||||
S _SP Def0081
|
||||
S _SCON0 Def0098
|
||||
S _AUTODAT1 Def009C
|
||||
S _EI2C Def00E9
|
||||
S _full_speed_devqual_descr Ref0000
|
||||
S _INT2IVEC DefE666
|
||||
S _AUTODAT2 Def009F
|
||||
S _SCON1 Def00C0
|
||||
S _SMOD1 Def00DF
|
||||
S _MICROFRAME DefE686
|
||||
S _SUDPTRCTL DefE6B5
|
||||
S _EP4GPIFTRIG DefE6DC
|
||||
S _EP2468STAT Def00AA
|
||||
S _OV Def00D2
|
||||
S _INT4IVEC DefE667
|
||||
S _GPIFSGLDATLNOX Def00BF
|
||||
S _T2CON Def00C8
|
||||
S _EP6GPIFTRIG DefE6E4
|
||||
S _ACC Def00E0
|
||||
S _string_descriptors Ref0000
|
||||
S _full_speed_config_descr Ref0000
|
||||
S _EP2FIFOBUF DefF000
|
||||
S _C_T2 Def00C9
|
||||
S _BREAKPT DefE605
|
||||
S _EP2FIFOPFH DefE630
|
||||
S _EP8GPIFTRIG DefE6EC
|
||||
S _AUTOPTRH2 Def009D
|
||||
S _SETUPDAT DefE6B8
|
||||
S _EP2GPIFFLGSEL DefE6D2
|
||||
S _EP4FIFOBUF DefF400
|
||||
S _EIPX4 Def00FA
|
||||
S _EP4FIFOPFH DefE632
|
||||
S _EP2ISOINPKTS DefE640
|
||||
S _GPIFREADYCFG DefE6F3
|
||||
S _EIPX5 Def00FB
|
||||
S _fx2_reset_data_toggle Ref0000
|
||||
S _EP4GPIFFLGSEL DefE6DA
|
||||
S _FLOWSTBHPERIOD DefE6CD
|
||||
S _EP6FIFOBUF DefF800
|
||||
S _EXIF Def0091
|
||||
S _RCLK Def00CD
|
||||
S _EIPX6 Def00FC
|
||||
S _EP2FIFOPFL DefE631
|
||||
S _EP6FIFOPFH DefE634
|
||||
S _EP4ISOINPKTS DefE641
|
||||
S _DPH1 Def0085
|
||||
S _AUTOPTRL2 Def009E
|
||||
S _EP6GPIFFLGSEL DefE6E2
|
||||
S _EP8FIFOBUF DefFC00
|
||||
S _TCLK Def00CC
|
||||
S _PI2C Def00F9
|
||||
S _EP4FIFOPFL DefE633
|
||||
S _EP8FIFOPFH DefE636
|
||||
S _EP6ISOINPKTS DefE642
|
||||
S _FNADDR DefE687
|
||||
S _EP8GPIFFLGSEL DefE6EA
|
||||
S _TESTCFG DefE6F9
|
||||
S _PCON Def0087
|
||||
S _P Def00D0
|
||||
S _GPIF_WAVE_DATA DefE400
|
||||
S _EP6FIFOPFL DefE635
|
||||
S _EP8ISOINPKTS DefE643
|
||||
S _I2CS DefE678
|
||||
S _DPL1 Def0084
|
||||
S _GPIFIRQ DefE661
|
||||
S _EP0BCH DefE68A
|
||||
S _EP01STAT Def00BA
|
||||
S _fx2_stall_ep0 Ref0000
|
||||
S _EP8FIFOPFL DefE637
|
||||
S _EP1INCS DefE6A2
|
||||
S _EIE Def00E8
|
||||
S _RESI Def00DC
|
||||
S _GPIFIE DefE660
|
||||
S _EP2BCH DefE690
|
||||
S _EP1OUTCS DefE6A1
|
||||
S _TCON Def0088
|
||||
S _TMOD Def0089
|
||||
S _OEA Def00B2
|
||||
S _EXF2 Def00CE
|
||||
S _EP0BCL DefE68B
|
||||
S _EP4BCH DefE694
|
||||
S _OEB Def00B3
|
||||
S _REN1 Def00C4
|
||||
S _EP2CFG DefE612
|
||||
S _EP2FIFOIRQ DefE651
|
||||
S _GPIFREADYSTAT DefE6F4
|
||||
S _OEC Def00B4
|
||||
S _EP2BCL DefE691
|
||||
S _EP6BCH DefE698
|
||||
S _OED Def00B5
|
||||
S _EP4CFG DefE613
|
||||
S _EP2FIFOIE DefE650
|
||||
S _EP4FIFOIRQ DefE653
|
||||
S _IOA Def0080
|
||||
S _OEE Def00B6
|
||||
S _EP4BCL DefE695
|
||||
S _EP8BCH DefE69C
|
||||
S _IOB Def0090
|
||||
S _PUSB Def00F8
|
||||
S _hook_uv Ref0000
|
||||
S _EP6CFG DefE614
|
||||
S _EP4FIFOIE DefE652
|
||||
S _EP6FIFOIRQ DefE655
|
||||
S _IOC Def00A0
|
||||
S _INTSETUP DefE668
|
||||
S _EP6BCL DefE699
|
||||
S _DPH Def0083
|
||||
S _IOD Def00B0
|
||||
S _EP8CFG DefE615
|
||||
S _EP6FIFOIE DefE654
|
||||
S _EP8FIFOIRQ DefE657
|
||||
S _USBFRAMEH DefE684
|
||||
S _IOE Def00B1
|
||||
S _RB81 Def00C2
|
||||
S _EP2AUTOINLENH DefE620
|
||||
S _EP8BCL DefE69D
|
||||
S _GPIFABORT DefE6F5
|
||||
S _INT2CLR Def00A1
|
||||
S _EIP Def00F8
|
||||
S _IE0 Def0089
|
||||
S _EP8FIFOIE DefE656
|
||||
S _IE1 Def008B
|
||||
S _TB81 Def00C3
|
||||
S _EP4AUTOINLENH DefE622
|
||||
S _DPL Def0082
|
||||
S _INT4CLR Def00A2
|
||||
S _AUTOPTRSETUP Def00AF
|
||||
S _RCAP2H Def00CB
|
||||
S _app_vendor_cmd Ref0000
|
||||
S _USBFRAMEL DefE685
|
||||
S _XGPIFSGLDATLX DefE6F1
|
||||
S _FLOWEQ0CTL DefE6C8
|
||||
S _FLOWSTB DefE6CB
|
||||
S _SM01 Def00C7
|
||||
S _INT6 Def00DB
|
||||
S _EP2AUTOINLENL DefE621
|
||||
S _EP6AUTOINLENH DefE624
|
||||
S _SUSPEND DefE681
|
||||
S _FLOWEQ1CTL DefE6C9
|
||||
S _EP0BUF DefE740
|
||||
S _SM11 Def00C6
|
||||
S _CP_RL2 Def00C8
|
||||
S _GPIFWFSELECT DefE6C0
|
||||
S _SM21 Def00C5
|
||||
S _EP4AUTOINLENL DefE623
|
||||
S _EP8AUTOINLENH DefE626
|
||||
S _RCAP2L Def00CA
|
||||
S _SEL Def0086
|
||||
S _AC Def00D6
|
||||
S _IFCONFIG DefE601
|
||||
S _IBNIRQ DefE659
|
||||
S _GPIFADRH DefE6C4
|
||||
S _XGPIFSGLDATH DefE6F0
|
||||
S _REN Def009C
|
||||
S _EP6AUTOINLENL DefE625
|
||||
S _NAKIRQ DefE65B
|
||||
S _FLOWLOGIC DefE6C7
|
||||
S _EA Def00AF
|
||||
S _FIFORESET DefE604
|
||||
S _IBNIE DefE658
|
||||
S _GPIFIDLECTL DefE6C2
|
||||
S _UDMACRCH DefE67D
|
||||
S _DPS Def0086
|
||||
S _EP8AUTOINLENL DefE627
|
||||
S _NAKIE DefE65A
|
||||
S _CT1 DefE6FB
|
||||
S _ES0 Def00AC
|
||||
S _FIFOPINPOLAR DefE609
|
||||
S _GPIFADRL DefE6C5
|
||||
S _EP2GPIFPFSTOP DefE6D3
|
||||
S _CT2 DefE6FC
|
||||
S _GPIFSGLDATLX Def00BE
|
||||
S _ET0 Def00A9
|
||||
S _ES1 Def00AE
|
||||
S _SUDPTRH DefE6B3
|
||||
S _USBTEST DefE6FA
|
||||
S _CT3 DefE6FD
|
||||
S _MPAGE Def0092
|
||||
S _TF0 Def008D
|
||||
S _ET1 Def00AB
|
||||
S _EP4GPIFPFSTOP DefE6DB
|
||||
S _UDMACRCL DefE67E
|
||||
S _CT4 DefE6FE
|
||||
S _EP24FIFOFLGS Def00AB
|
||||
S _TF1 Def008F
|
||||
S _ET2 Def00AD
|
||||
S _RES_WAVEDATA_END DefE480
|
||||
S _TH0 Def008C
|
||||
S _RB8 Def009A
|
||||
S _RI1 Def00C0
|
||||
S _TF2 Def00CF
|
||||
S _EP1INCFG DefE611
|
||||
S _TOGCTL DefE683
|
||||
S _EP6GPIFPFSTOP DefE6E3
|
||||
S _TH1 Def008D
|
||||
S _GPIFSGLDATH Def00BD
|
||||
S _IT0 Def0088
|
||||
S _EX0 Def00A8
|
||||
S _EP1OUTCFG DefE610
|
||||
S _SUDPTRL DefE6B4
|
||||
S _CKCON Def008E
|
||||
S _IE Def00A8
|
||||
S _TH2 Def00CD
|
||||
S _EICON Def00D8
|
||||
S _IT1 Def008A
|
||||
S _TB8 Def009B
|
||||
S _EX1 Def00AA
|
||||
S _TI1 Def00C1
|
||||
S _high_speed_device_descr Ref0000
|
||||
S _CLRERRCNT DefE665
|
||||
S _GPIFTCB0 DefE6D1
|
||||
S _EP8GPIFPFSTOP DefE6EB
|
||||
S _REVCTL DefE60B
|
||||
S _ERRCNTLIM DefE664
|
||||
S _GPIFTCB1 DefE6D0
|
||||
S _TL0 Def008A
|
||||
S _APTR1H Def009A
|
||||
S _SM0 Def009F
|
||||
S _high_speed_devqual_descr Ref0000
|
||||
S _UART230 DefE608
|
||||
S _GPIFTCB2 DefE6CF
|
||||
S _TL1 Def008B
|
||||
S _A0 Def0080
|
||||
S _SM1 Def009E
|
||||
S _GPIFTCB3 DefE6CE
|
||||
S _UDMACRCQUAL DefE67F
|
||||
S _TL2 Def00CC
|
||||
S _A1 Def0081
|
||||
S _SM2 Def009D
|
||||
S _FL Def00D1
|
||||
S _EP68FIFOFLGS Def00AC
|
||||
S _A2 Def0082
|
||||
S _PS0 Def00BC
|
||||
S _I2DAT DefE679
|
||||
S _APTR1L Def009B
|
||||
S _A3 Def0083
|
||||
S _D0 Def00B0
|
||||
S _PT0 Def00B9
|
||||
S _PS1 Def00BE
|
||||
S _high_speed_config_descr Ref0000
|
||||
S _BPADDRH DefE606
|
||||
S _A4 Def0084
|
||||
S _D1 Def00B1
|
||||
S _PT1 Def00BB
|
||||
S _RS0 Def00D3
|
||||
S _nstring_descriptors Ref0000
|
||||
S _USBIRQ DefE65D
|
||||
S _PORTACFG DefE670
|
||||
S _FLOWSTBEDGE DefE6CC
|
||||
S _A5 Def0085
|
||||
S _TR0 Def008C
|
||||
S _D2 Def00B2
|
||||
S _PT2 Def00BD
|
||||
S _RS1 Def00D4
|
||||
S _F0 Def00D5
|
||||
S _PINFLAGSAB DefE602
|
||||
S _EP2FIFOFLGS DefE6A7
|
||||
S _A6 Def0086
|
||||
S _TR1 Def008E
|
||||
S _D3 Def00B3
|
||||
S _USBIE DefE65C
|
||||
S _PORTCCFG DefE671
|
||||
S _EP2FIFOBCH DefE6AB
|
||||
S _A7 Def0087
|
||||
S _D4 Def00B4
|
||||
S _PX0 Def00B8
|
||||
S _TR2 Def00CA
|
||||
S _ERESI Def00DD
|
||||
S _EIUSB Def00E8
|
||||
S _BPADDRL DefE607
|
||||
S _EP4FIFOFLGS DefE6A8
|
||||
S _GPIFCTLCFG DefE6C3
|
||||
S _FLOWSTATE DefE6C6
|
||||
S _IP Def00B8
|
||||
S _D5 Def00B5
|
||||
S _PX1 Def00BA
|
||||
S _REVID DefE60A
|
||||
S _PORTECFG DefE672
|
||||
S _EP4FIFOBCH DefE6AD
|
||||
S _GPIFIDLECS DefE6C1
|
||||
S _FLOWHOLDOFF DefE6CA
|
||||
S _EP1INBUF DefE7C0
|
||||
S _PSW Def00D0
|
||||
S _D6 Def00B6
|
||||
S _hook_uv_PARM_2 Ref0000
|
||||
S _PINFLAGSCD DefE603
|
||||
S _EP2FIFOCFG DefE618
|
||||
S _XAUTODAT1 DefE67B
|
||||
S _EP0CS DefE6A0
|
||||
S _EP6FIFOFLGS DefE6A9
|
||||
S _EP1OUTBUF DefE780
|
||||
S _RI Def0098
|
||||
S _D7 Def00B7
|
||||
S _XAUTODAT2 DefE67C
|
||||
S _EP2FIFOBCL DefE6AC
|
||||
S _EP6FIFOBCH DefE6AF
|
||||
S _GPIFTRIG Def00BB
|
||||
S _CY Def00D7
|
||||
S _EP4FIFOCFG DefE619
|
||||
S _INPKTEND DefE648
|
||||
S _EP2CS DefE6A3
|
||||
S _EP8FIFOFLGS DefE6AA
|
||||
S _TI Def0099
|
||||
S _CPUCS DefE600
|
||||
S _OUTPKTEND DefE649
|
||||
S _I2CTL DefE67A
|
||||
S _EP4FIFOBCL DefE6AE
|
||||
S _EP8FIFOBCH DefE6B1
|
||||
S _XGPIFSGLDATLNOX DefE6F2
|
||||
S _EP6FIFOCFG DefE61A
|
||||
S _USBERRIRQ DefE663
|
||||
S _EP4CS DefE6A4
|
||||
S _EIEX4 Def00EA
|
||||
S _USBCS DefE680
|
||||
S _EP6FIFOBCL DefE6B0
|
||||
S _SBUF0 Def0099
|
||||
S _EIEX5 Def00EB
|
||||
A _CODE size 0 flags 0 addr 0
|
||||
A RSEG size 0 flags 0 addr 0
|
||||
A REG_BANK_0 size 8 flags 4 addr 0
|
||||
A BIT_BANK size 1 flags 4 addr 0
|
||||
A DSEG size A flags 0 addr 0
|
||||
S __usb_alt_setting Def0001
|
||||
S _other_config_descr Def0008
|
||||
S __usb_config Def0000
|
||||
S _current_device_descr Def0002
|
||||
S _current_devqual_descr Def0004
|
||||
S _current_config_descr Def0006
|
||||
A OSEG size 0 flags 4 addr 0
|
||||
A ISEG size 0 flags 0 addr 0
|
||||
A IABS size 0 flags 8 addr 0
|
||||
A BSEG size 2 flags 80 addr 0
|
||||
S __usb_rx_overrun Def0001
|
||||
S __usb_got_SUDAV Def0000
|
||||
A PSEG size 0 flags 50 addr 0
|
||||
A XSEG size 0 flags 40 addr 0
|
||||
A XABS size 0 flags 48 addr 0
|
||||
A HOME size 0 flags 20 addr 0
|
||||
A GSINIT0 size 0 flags 20 addr 0
|
||||
A GSINIT1 size 0 flags 20 addr 0
|
||||
A GSINIT2 size 0 flags 20 addr 0
|
||||
A GSINIT3 size 0 flags 20 addr 0
|
||||
A GSINIT4 size 0 flags 20 addr 0
|
||||
A GSINIT5 size 0 flags 20 addr 0
|
||||
A GSINIT size 6 flags 20 addr 0
|
||||
A GSFINAL size 0 flags 20 addr 0
|
||||
A CSEG size 424 flags 20 addr 0
|
||||
S _epcs Def011A
|
||||
S _usb_handle_setup_packet Def0163
|
||||
S _plausible_endpoint Def00FB
|
||||
S _usb_install_handlers Def00CD
|
||||
A CONST size 0 flags 20 addr 0
|
||||
A CABS size 0 flags 28 addr 0
|
||||
T 00 00
|
||||
R 00 00 00 02
|
||||
T 00 00
|
||||
R 00 00 00 03
|
||||
T 00 00
|
||||
R 00 00 00 03
|
||||
T 00 00
|
||||
R 00 00 00 04
|
||||
T 00 00
|
||||
R 00 00 00 04
|
||||
T 00 01
|
||||
R 00 00 00 04
|
||||
T 00 01
|
||||
R 00 00 00 04
|
||||
T 00 02
|
||||
R 00 00 00 04
|
||||
T 00 02
|
||||
R 00 00 00 04
|
||||
T 00 04
|
||||
R 00 00 00 04
|
||||
T 00 04
|
||||
R 00 00 00 04
|
||||
T 00 06
|
||||
R 00 00 00 04
|
||||
T 00 06
|
||||
R 00 00 00 04
|
||||
T 00 08
|
||||
R 00 00 00 04
|
||||
T 00 08
|
||||
R 00 00 00 04
|
||||
T 00 00
|
||||
R 00 00 00 08
|
||||
T 00 00
|
||||
R 00 00 00 08
|
||||
T 00 01
|
||||
R 00 00 00 08
|
||||
T 00 01
|
||||
R 00 00 00 08
|
||||
T 00 00 75 00 00 00 00 75 00 00 01 00
|
||||
R 00 00 00 13 F1 21 03 00 04 F1 21 08 00 04
|
||||
T 00 00
|
||||
R 00 00 00 15
|
||||
T 00 00 90 E6 80 E0 FA 30 E7 19 75 00 00 02
|
||||
R 00 00 00 15 F1 21 0B 00 04
|
||||
T 00 0A 00 00 00 75 00 00 03
|
||||
R 00 00 00 15 F1 03 02 00 E2 F1 21 06 00 04
|
||||
T 00 0D 00 00 00 75 00 00 04
|
||||
R 00 00 00 15 F1 83 02 00 E2 F1 21 06 00 04
|
||||
T 00 10 00 00 00 75 00 00 05
|
||||
R 00 00 00 15 F1 03 02 00 EC F1 21 06 00 04
|
||||
T 00 13 00 00 00 75 00 00 06
|
||||
R 00 00 00 15 F1 83 02 00 EC F1 21 06 00 04
|
||||
T 00 16 00 00 00 75 00 00 07
|
||||
R 00 00 00 15 F1 03 02 01 01 F1 21 06 00 04
|
||||
T 00 19 00 00 00 75 00 00 08
|
||||
R 00 00 00 15 F1 83 02 01 01 F1 21 06 00 04
|
||||
T 00 1C 00 00 00 75 00 00 09
|
||||
R 00 00 00 15 F1 03 02 00 26 F1 21 06 00 04
|
||||
T 00 1F 00 00 00 22
|
||||
R 00 00 00 15 F1 83 02 00 26
|
||||
T 00 21
|
||||
R 00 00 00 15
|
||||
T 00 21 75 00 00 02 00 00 00 75
|
||||
R 00 00 00 15 F1 21 03 00 04 F1 03 06 00 07
|
||||
T 00 25 00 00 03 00 00 00 75
|
||||
R 00 00 00 15 F1 21 02 00 04 F1 83 05 00 07
|
||||
T 00 28 00 00 04 00 00 00 75
|
||||
R 00 00 00 15 F1 21 02 00 04 F1 03 05 00 16
|
||||
T 00 2B 00 00 05 00 00 00 75
|
||||
R 00 00 00 15 F1 21 02 00 04 F1 83 05 00 16
|
||||
T 00 2E 00 00 06 00 00 00 75
|
||||
R 00 00 00 15 F1 21 02 00 04 F1 03 05 00 26
|
||||
T 00 31 00 00 07 00 00 00 75
|
||||
R 00 00 00 15 F1 21 02 00 04 F1 83 05 00 26
|
||||
T 00 34 00 00 08 00 00 00 75
|
||||
R 00 00 00 15 F1 21 02 00 04 F1 03 05 01 01
|
||||
T 00 37 00 00 09 00 00 00 22
|
||||
R 00 00 00 15 F1 21 02 00 04 F1 83 05 01 01
|
||||
T 00 3A
|
||||
R 00 00 00 15
|
||||
T 00 3A 53 91 EF 75 A1 00 D2 00 00 00 32
|
||||
R 00 00 00 15 F1 21 09 00 08
|
||||
T 00 43
|
||||
R 00 00 00 15
|
||||
T 00 43 C0 00 00 00 C0 E0 C0 F0 C0 82 C0 83 C0 02
|
||||
R 00 00 00 15 F1 21 03 00 03
|
||||
T 00 4F C0 03 C0 04 C0 05 C0 06 C0 07 C0 00 C0 01
|
||||
R 00 00 00 15
|
||||
T 00 5D C0 D0 75 D0 00 53 91 EF 75 A1 00 12 00 00
|
||||
R 00 00 00 15 00 0E 00 15
|
||||
T 00 6B D0 D0 D0 01 D0 00 D0 07 D0 06 D0 05 D0 04
|
||||
R 00 00 00 15
|
||||
T 00 79 D0 03 D0 02 D0 83 D0 82 D0 F0 D0 E0 D0
|
||||
R 00 00 00 15
|
||||
T 00 86 00 00 00 32
|
||||
R 00 00 00 15 F1 21 02 00 03
|
||||
T 00 88
|
||||
R 00 00 00 15
|
||||
T 00 88 C0 00 00 00 C0 E0 C0 F0 C0 82 C0 83 C0 02
|
||||
R 00 00 00 15 F1 21 03 00 03
|
||||
T 00 94 C0 03 C0 04 C0 05 C0 06 C0 07 C0 00 C0 01
|
||||
R 00 00 00 15
|
||||
T 00 A2 C0 D0 75 D0 00 53 91 EF 75 A1 00 12 00 00
|
||||
R 00 00 00 15 00 0E 00 15
|
||||
T 00 B0 D0 D0 D0 01 D0 00 D0 07 D0 06 D0 05 D0 04
|
||||
R 00 00 00 15
|
||||
T 00 BE D0 03 D0 02 D0 83 D0 82 D0 F0 D0 E0 D0
|
||||
R 00 00 00 15
|
||||
T 00 CB 00 00 00 32
|
||||
R 00 00 00 15 F1 21 02 00 03
|
||||
T 00 CD
|
||||
R 00 00 00 15
|
||||
T 00 CD 12 00 00 75 00 00 00
|
||||
R 00 00 00 15 00 03 00 15 F1 23 06 01 2E
|
||||
T 00 D2 00 00 3A 75 00 00 01
|
||||
R 00 00 00 15 F1 01 02 00 15 F1 23 06 01 2E
|
||||
T 00 D5 00 00 3A 75 82 00 12 00 00 75
|
||||
R 00 00 00 15 F1 81 02 00 15 02 09 00 75
|
||||
T 00 DD 00 00 00 00 00 43 75
|
||||
R 00 00 00 15 F1 23 02 01 2E F1 01 05 00 15
|
||||
T 00 E0 00 00 01 00 00 43 75 82 10 12
|
||||
R 00 00 00 15 F1 23 02 01 2E F1 81 05 00 15
|
||||
T 00 E6 00 00 75 00 00 00
|
||||
R 00 00 00 15 02 02 00 75 F1 23 05 01 2E
|
||||
T 00 EA 00 00 88 75 00 00 01
|
||||
R 00 00 00 15 F1 01 02 00 15 F1 23 06 01 2E
|
||||
T 00 ED 00 00 88 75 82 14 12 00 00 90 E6 5C 74 31
|
||||
R 00 00 00 15 F1 81 02 00 15 02 09 00 75
|
||||
T 00 F9 F0 22
|
||||
R 00 00 00 15
|
||||
T 00 FB
|
||||
R 00 00 00 15
|
||||
T 00 FB E5 82 54 7F FA 24 F7 50 04 75 82 00 22
|
||||
R 00 00 00 15
|
||||
T 01 08
|
||||
R 00 00 00 15
|
||||
T 01 08 BA 01 04 75 82 01 22
|
||||
R 00 00 00 15
|
||||
T 01 0F
|
||||
R 00 00 00 15
|
||||
T 01 0F 53 02 01 E4 BA 00 01 04
|
||||
R 00 00 00 15
|
||||
T 01 17
|
||||
R 00 00 00 15
|
||||
T 01 17 F5 82 22
|
||||
R 00 00 00 15
|
||||
T 01 1A
|
||||
R 00 00 00 15
|
||||
T 01 1A AA 82 BA 01 0C 90 E6 A1 E0 FB 7C 00 8B 82
|
||||
R 00 00 00 15
|
||||
T 01 28 8C 83 22
|
||||
R 00 00 00 15
|
||||
T 01 2B
|
||||
R 00 00 00 15
|
||||
T 01 2B BA 81 0C 90 E6 A2 E0 FB 7C 00 8B 82 8C 83
|
||||
R 00 00 00 15
|
||||
T 01 39 22
|
||||
R 00 00 00 15
|
||||
T 01 3A
|
||||
R 00 00 00 15
|
||||
T 01 3A 53 02 7F EA 70 0C 90 E6 A0 E0 FB 7C 00 8B
|
||||
R 00 00 00 15
|
||||
T 01 48 82 8C 83 22
|
||||
R 00 00 00 15
|
||||
T 01 4C
|
||||
R 00 00 00 15
|
||||
T 01 4C 90 E6 A3 E0 FB 7C 00 EA C3 13 FA 7D 00 EA
|
||||
R 00 00 00 15
|
||||
T 01 5A 2B FB ED 3C 8B 82 F5 83 22
|
||||
R 00 00 00 15
|
||||
T 01 63
|
||||
R 00 00 00 15
|
||||
T 01 63 C2 00 00 00 90 E6 B8 E0 FA 53 02 60 BA 00
|
||||
R 00 00 00 15 F1 21 03 00 08
|
||||
T 01 6F 02 80 28
|
||||
R 00 00 00 15
|
||||
T 01 72
|
||||
R 00 00 00 15
|
||||
T 01 72 BA 20 02 80 0D
|
||||
R 00 00 00 15
|
||||
T 01 77
|
||||
R 00 00 00 15
|
||||
T 01 77 BA 40 02 80 0E
|
||||
R 00 00 00 15
|
||||
T 01 7C
|
||||
R 00 00 00 15
|
||||
T 01 7C BA 60 02 80 03
|
||||
R 00 00 00 15
|
||||
T 01 81
|
||||
R 00 00 00 15
|
||||
T 01 81 02 04 1C
|
||||
R 00 00 00 15 00 03 00 15
|
||||
T 01 84
|
||||
R 00 00 00 15
|
||||
T 01 84
|
||||
R 00 00 00 15
|
||||
T 01 84 12 00 00 02 04 1C
|
||||
R 00 00 00 15 02 03 00 55 00 06 00 15
|
||||
T 01 8A
|
||||
R 00 00 00 15
|
||||
T 01 8A 12 00 00 E5 82 60 03 02 04 1C
|
||||
R 00 00 00 15 02 03 00 92 00 0A 00 15
|
||||
T 01 94
|
||||
R 00 00 00 15
|
||||
T 01 94 12 00 00 02 04 1C
|
||||
R 00 00 00 15 02 03 00 55 00 06 00 15
|
||||
T 01 9A
|
||||
R 00 00 00 15
|
||||
T 01 9A 90 E6 B8 E0 FA 53 02 80 BA 80 02 80 03
|
||||
R 00 00 00 15
|
||||
T 01 A7
|
||||
R 00 00 00 15
|
||||
T 01 A7 02 03 1D
|
||||
R 00 00 00 15 00 03 00 15
|
||||
T 01 AA
|
||||
R 00 00 00 15
|
||||
T 01 AA 90 E6 B9 E0 FA BA 00 03 02 02 9B
|
||||
R 00 00 00 15 00 0B 00 15
|
||||
T 01 B5
|
||||
R 00 00 00 15
|
||||
T 01 B5 BA 06 02 80 35
|
||||
R 00 00 00 15
|
||||
T 01 BA
|
||||
R 00 00 00 15
|
||||
T 01 BA BA 08 02 80 08
|
||||
R 00 00 00 15
|
||||
T 01 BF
|
||||
R 00 00 00 15
|
||||
T 01 BF BA 0A 02 80 17
|
||||
R 00 00 00 15
|
||||
T 01 C4
|
||||
R 00 00 00 15
|
||||
T 01 C4 02 03 17
|
||||
R 00 00 00 15 00 03 00 15
|
||||
T 01 C7
|
||||
R 00 00 00 15
|
||||
T 01 C7 90 E7 40 E5 00 00 00 F0 90 E6 8A E4 F0 90
|
||||
R 00 00 00 15 F1 21 06 00 04
|
||||
T 01 D3 E6 8B 74 01 F0 02 04 1C
|
||||
R 00 00 00 15 00 08 00 15
|
||||
T 01 DB
|
||||
R 00 00 00 15
|
||||
T 01 DB 90 E7 40 E5 00 00 01 F0 90 E6 8A E4 F0 90
|
||||
R 00 00 00 15 F1 21 06 00 04
|
||||
T 01 E7 E6 8B 74 01 F0 02 04 1C
|
||||
R 00 00 00 15 00 08 00 15
|
||||
T 01 EF
|
||||
R 00 00 00 15
|
||||
T 01 EF 90 E6 BB E0 FA BA 01 02 80 17
|
||||
R 00 00 00 15
|
||||
T 01 F9
|
||||
R 00 00 00 15
|
||||
T 01 F9 BA 02 02 80 38
|
||||
R 00 00 00 15
|
||||
T 01 FE
|
||||
R 00 00 00 15
|
||||
T 01 FE BA 03 02 80 59
|
||||
R 00 00 00 15
|
||||
T 02 03
|
||||
R 00 00 00 15
|
||||
T 02 03 BA 06 02 80 1B
|
||||
R 00 00 00 15
|
||||
T 02 08
|
||||
R 00 00 00 15
|
||||
T 02 08 BA 07 02 80 3C
|
||||
R 00 00 00 15
|
||||
T 02 0D
|
||||
R 00 00 00 15
|
||||
T 02 0D 02 02 95
|
||||
R 00 00 00 15 00 03 00 15
|
||||
T 02 10
|
||||
R 00 00 00 15
|
||||
T 02 10 AA 00 00 02 AB 00 00 03 90 E6 B3 EB F0 7B
|
||||
R 00 00 00 15 F1 21 03 00 04 F1 21 07 00 04
|
||||
T 02 1A 00 90 E6 B4 EA F0 02 04 1C
|
||||
R 00 00 00 15 00 09 00 15
|
||||
T 02 23
|
||||
R 00 00 00 15
|
||||
T 02 23 AA 00 00 04 AB 00 00 05 90 E6 B3 EB F0 7B
|
||||
R 00 00 00 15 F1 21 03 00 04 F1 21 07 00 04
|
||||
T 02 2D 00 90 E6 B4 EA F0 02 04 1C
|
||||
R 00 00 00 15 00 09 00 15
|
||||
T 02 36
|
||||
R 00 00 00 15
|
||||
T 02 36 AA 00 00 06 AB 00 00 07 90 E6 B3 EB F0 7B
|
||||
R 00 00 00 15 F1 21 03 00 04 F1 21 07 00 04
|
||||
T 02 40 00 90 E6 B4 EA F0 02 04 1C
|
||||
R 00 00 00 15 00 09 00 15
|
||||
T 02 49
|
||||
R 00 00 00 15
|
||||
T 02 49 AA 00 00 08 AB 00 00 09 90 E6 B3 EB F0 7B
|
||||
R 00 00 00 15 F1 21 03 00 04 F1 21 07 00 04
|
||||
T 02 53 00 90 E6 B4 EA F0 02 04 1C
|
||||
R 00 00 00 15 00 09 00 15
|
||||
T 02 5C
|
||||
R 00 00 00 15
|
||||
T 02 5C 90 E6 BA E0 FA 90 00 00 E0 FB C3 EA 9B 40
|
||||
R 00 00 00 15 02 08 01 07
|
||||
T 02 6A 06 12 00 00 02 04 1C
|
||||
R 00 00 00 15 02 04 00 55 00 07 00 15
|
||||
T 02 71
|
||||
R 00 00 00 15
|
||||
T 02 71 90 E6 BA E0 75 F0 02 A4 24 00 00 00 F5 82
|
||||
R 00 00 00 15 F1 03 0B 00 25
|
||||
T 02 7D 74 00 00 00 35 F0 F5 83 E0 FA A3 E0 90
|
||||
R 00 00 00 15 F1 83 03 00 25
|
||||
T 02 88 E6 B3 F0 7B 00 90 E6 B4 EA F0 02 04 1C
|
||||
R 00 00 00 15 00 0D 00 15
|
||||
T 02 95
|
||||
R 00 00 00 15
|
||||
T 02 95 12 00 00 02 04 1C
|
||||
R 00 00 00 15 02 03 00 55 00 06 00 15
|
||||
T 02 9B
|
||||
R 00 00 00 15
|
||||
T 02 9B 90 E6 B8 E0 FA 53 02 1F BA 00 02 80 0A
|
||||
R 00 00 00 15
|
||||
T 02 A8
|
||||
R 00 00 00 15
|
||||
T 02 A8 BA 01 02 80 1C
|
||||
R 00 00 00 15
|
||||
T 02 AD
|
||||
R 00 00 00 15
|
||||
T 02 AD BA 02 64 80 2C
|
||||
R 00 00 00 15
|
||||
T 02 B2
|
||||
R 00 00 00 15
|
||||
T 02 B2 90 E7 40 74 01 F0 90 E7 41 E4 F0 90 E6 8A
|
||||
R 00 00 00 15
|
||||
T 02 C0 F0 90 E6 8B 74 02 F0 80 4E
|
||||
R 00 00 00 15
|
||||
T 02 C9
|
||||
R 00 00 00 15
|
||||
T 02 C9 90 E7 40 E4 F0 90 E7 41 F0 90 E6 8A F0 90
|
||||
R 00 00 00 15
|
||||
T 02 D7 E6 8B 74 02 F0 80 39
|
||||
R 00 00 00 15
|
||||
T 02 DE
|
||||
R 00 00 00 15
|
||||
T 02 DE 90 E6 BC E0 F5 82 12 00 FB E5 82 60 24 90
|
||||
R 00 00 00 15 00 09 00 15
|
||||
T 02 EC E6 BC E0 F5 82 12 01 1A E0 FA 53 02 01 90
|
||||
R 00 00 00 15 00 08 00 15
|
||||
T 02 FA E7 40 EA F0 90 E7 41 E4 F0 90 E6 8A F0 90
|
||||
R 00 00 00 15
|
||||
T 03 08 E6 8B 74 02 F0 80 08
|
||||
R 00 00 00 15
|
||||
T 03 0F
|
||||
R 00 00 00 15
|
||||
T 03 0F 12 00 00 80 03
|
||||
R 00 00 00 15 02 03 00 55
|
||||
T 03 14
|
||||
R 00 00 00 15
|
||||
T 03 14 12 00 00
|
||||
R 00 00 00 15 02 03 00 55
|
||||
T 03 17
|
||||
R 00 00 00 15
|
||||
T 03 17 12 00 00 02 04 1C
|
||||
R 00 00 00 15 02 03 00 55 00 06 00 15
|
||||
T 03 1D
|
||||
R 00 00 00 15
|
||||
T 03 1D 90 E6 B9 E0 FA 24 F4 50 03 02 04 19
|
||||
R 00 00 00 15 00 0C 00 15
|
||||
T 03 29
|
||||
R 00 00 00 15
|
||||
T 03 29 EA 2A 2A 90 03 30 73
|
||||
R 00 00 00 15 00 06 00 15
|
||||
T 03 30
|
||||
R 00 00 00 15
|
||||
T 03 30 02 04 19 02 03 66 02
|
||||
R 00 00 00 15 00 03 00 15 00 06 00 15
|
||||
T 03 37 03 E1 02 03 C2 02
|
||||
R 00 00 00 15 00 02 00 15 00 05 00 15
|
||||
T 03 3D 04 19 02 04 19 02
|
||||
R 00 00 00 15 00 02 00 15 00 05 00 15
|
||||
T 03 43 04 19 02 04 19 02
|
||||
R 00 00 00 15 00 02 00 15 00 05 00 15
|
||||
T 03 49 04 19 02 03 54 02
|
||||
R 00 00 00 15 00 02 00 15 00 05 00 15
|
||||
T 03 4F 04 19 02 03 5D
|
||||
R 00 00 00 15 00 02 00 15 00 05 00 15
|
||||
T 03 54
|
||||
R 00 00 00 15
|
||||
T 03 54 90 E6 BA E0 F5 00 00 00 02 04 1C
|
||||
R 00 00 00 15 F1 21 07 00 04 00 0B 00 15
|
||||
T 03 5D
|
||||
R 00 00 00 15
|
||||
T 03 5D 90 E6 BA E0 F5 00 00 01 02 04 1C
|
||||
R 00 00 00 15 F1 21 07 00 04 00 0B 00 15
|
||||
T 03 66
|
||||
R 00 00 00 15
|
||||
T 03 66 90 E6 B8 E0 FA 53 02 1F BA 00 02 80 05
|
||||
R 00 00 00 15
|
||||
T 03 73
|
||||
R 00 00 00 15
|
||||
T 03 73 BA 02 47 80 0A
|
||||
R 00 00 00 15
|
||||
T 03 78
|
||||
R 00 00 00 15
|
||||
T 03 78 90 E6 BA E0 12 00 00 02 04 1C
|
||||
R 00 00 00 15 02 07 00 55 00 0A 00 15
|
||||
T 03 82
|
||||
R 00 00 00 15
|
||||
T 03 82 90 E6 BA E0 70 30 90 E6 BC E0 F5 82 12
|
||||
R 00 00 00 15
|
||||
T 03 8F 00 FB E5 82 60 23 90 E6 BC E0 F5 82 12
|
||||
R 00 00 00 15 00 02 00 15
|
||||
T 03 9C 01 1A AA 82 AB 83 E0 FC 53 04 FE 8A 82 8B
|
||||
R 00 00 00 15 00 02 00 15
|
||||
T 03 AA 83 EC F0 90 E6 BC E0 F5 82 12 00 00 80 64
|
||||
R 00 00 00 15 02 0C 00 35
|
||||
T 03 B8
|
||||
R 00 00 00 15
|
||||
T 03 B8 12 00 00 80 5F
|
||||
R 00 00 00 15 02 03 00 55
|
||||
T 03 BD
|
||||
R 00 00 00 15
|
||||
T 03 BD 12 00 00 80 5A
|
||||
R 00 00 00 15 02 03 00 55
|
||||
T 03 C2
|
||||
R 00 00 00 15
|
||||
T 03 C2 90 E6 B8 E0 FA 53 02 1F BA 00 4F 90 E6 BA
|
||||
R 00 00 00 15
|
||||
T 03 D0 E0 FA BA 01 02 80 05
|
||||
R 00 00 00 15
|
||||
T 03 D7
|
||||
R 00 00 00 15
|
||||
T 03 D7 BA 02 02 80 40
|
||||
R 00 00 00 15
|
||||
T 03 DC
|
||||
R 00 00 00 15
|
||||
T 03 DC
|
||||
R 00 00 00 15
|
||||
T 03 DC 12 00 00 80 3B
|
||||
R 00 00 00 15 02 03 00 55
|
||||
T 03 E1
|
||||
R 00 00 00 15
|
||||
T 03 E1 90 E6 BA E0 FA 70 2C 90 E6 BC E0 F5 82 12
|
||||
R 00 00 00 15
|
||||
T 03 EF 00 FB E5 82 60 1A 90 E6 BC E0 F5 82 12
|
||||
R 00 00 00 15 00 02 00 15
|
||||
T 03 FC 01 1A AA 82 AB 83 E0 FC 43 04 01 8A 82 8B
|
||||
R 00 00 00 15 00 02 00 15
|
||||
T 04 0A 83 EC F0 80 0D
|
||||
R 00 00 00 15
|
||||
T 04 0F
|
||||
R 00 00 00 15
|
||||
T 04 0F 12 00 00 80 08
|
||||
R 00 00 00 15 02 03 00 55
|
||||
T 04 14
|
||||
R 00 00 00 15
|
||||
T 04 14 12 00 00 80 03
|
||||
R 00 00 00 15 02 03 00 55
|
||||
T 04 19
|
||||
R 00 00 00 15
|
||||
T 04 19
|
||||
R 00 00 00 15
|
||||
T 04 19
|
||||
R 00 00 00 15
|
||||
T 04 19 12 00 00
|
||||
R 00 00 00 15 02 03 00 55
|
||||
T 04 1C
|
||||
R 00 00 00 15
|
||||
T 04 1C 90 E6 A0 E0 44 80 F0 22
|
||||
R 00 00 00 15
|
||||
737
firmware/GN3S_v2/lib/usb_common.sym
Normal file
737
firmware/GN3S_v2/lib/usb_common.sym
Normal file
@@ -0,0 +1,737 @@
|
||||
ASxxxx Assembler V01.70 + NoICE + SDCC mods + Flat24 Feb-1999 (Intel 8051), page 1.
|
||||
|
||||
Symbol Table
|
||||
|
||||
A 00D6
|
||||
AC 00D6
|
||||
ACC 00E0
|
||||
ACC.0 00E0
|
||||
ACC.1 00E1
|
||||
ACC.2 00E2
|
||||
ACC.3 00E3
|
||||
ACC.4 00E4
|
||||
ACC.5 00E5
|
||||
ACC.6 00E6
|
||||
ACC.7 00E7
|
||||
B 00F0
|
||||
B.0 00F0
|
||||
B.1 00F1
|
||||
B.2 00F2
|
||||
B.3 00F3
|
||||
B.4 00F4
|
||||
B.5 00F5
|
||||
B.6 00F6
|
||||
B.7 00F7
|
||||
CPRL2 00C8
|
||||
CT2 00C9
|
||||
CY 00D7
|
||||
DPH 0083
|
||||
DPL 0082
|
||||
EA 00AF
|
||||
ES 00AC
|
||||
ET0 00A9
|
||||
ET1 00AB
|
||||
ET2 00AD
|
||||
EX0 00A8
|
||||
EX1 00AA
|
||||
EXEN2 00CB
|
||||
EXF2 00CE
|
||||
F0 00D5
|
||||
IE 00A8
|
||||
IE.0 00A8
|
||||
IE.1 00A9
|
||||
IE.2 00AA
|
||||
IE.3 00AB
|
||||
IE.4 00AC
|
||||
IE.5 00AD
|
||||
IE.7 00AF
|
||||
IE0 0089
|
||||
IE1 008B
|
||||
INT0 00B2
|
||||
INT1 00B3
|
||||
IP 00B8
|
||||
IP.0 00B8
|
||||
IP.1 00B9
|
||||
IP.2 00BA
|
||||
IP.3 00BB
|
||||
IP.4 00BC
|
||||
IP.5 00BD
|
||||
IT0 0088
|
||||
IT1 008A
|
||||
OV 00D2
|
||||
P 00D0
|
||||
P0 0080
|
||||
P0.0 0080
|
||||
P0.1 0081
|
||||
P0.2 0082
|
||||
P0.3 0083
|
||||
P0.4 0084
|
||||
P0.5 0085
|
||||
P0.6 0086
|
||||
P0.7 0087
|
||||
P1 0090
|
||||
P1.0 0090
|
||||
P1.1 0091
|
||||
P1.2 0092
|
||||
P1.3 0093
|
||||
P1.4 0094
|
||||
P1.5 0095
|
||||
P1.6 0096
|
||||
P1.7 0097
|
||||
P2 00A0
|
||||
P2.0 00A0
|
||||
P2.1 00A1
|
||||
P2.2 00A2
|
||||
P2.3 00A3
|
||||
P2.4 00A4
|
||||
P2.5 00A5
|
||||
P2.6 00A6
|
||||
P2.7 00A7
|
||||
P3 00B0
|
||||
P3.0 00B0
|
||||
P3.1 00B1
|
||||
P3.2 00B2
|
||||
P3.3 00B3
|
||||
P3.4 00B4
|
||||
P3.5 00B5
|
||||
P3.6 00B6
|
||||
P3.7 00B7
|
||||
PCON 0087
|
||||
PS 00BC
|
||||
PSW 00D0
|
||||
PSW.0 00D0
|
||||
PSW.1 00D1
|
||||
PSW.2 00D2
|
||||
PSW.3 00D3
|
||||
PSW.4 00D4
|
||||
PSW.5 00D5
|
||||
PSW.6 00D6
|
||||
PSW.7 00D7
|
||||
PT0 00B9
|
||||
PT1 00BB
|
||||
PT2 00BD
|
||||
PX0 00B8
|
||||
PX1 00BA
|
||||
RB8 009A
|
||||
RCAP2H 00CB
|
||||
RCAP2L 00CA
|
||||
RCLK 00CD
|
||||
REN 009C
|
||||
RI 0098
|
||||
RS0 00D3
|
||||
RS1 00D4
|
||||
RXD 00B0
|
||||
SBUF 0099
|
||||
SCON 0098
|
||||
SCON.0 0098
|
||||
SCON.1 0099
|
||||
SCON.2 009A
|
||||
SCON.3 009B
|
||||
SCON.4 009C
|
||||
SCON.5 009D
|
||||
SCON.6 009E
|
||||
SCON.7 009F
|
||||
SM0 009F
|
||||
SM1 009E
|
||||
SM2 009D
|
||||
SP 0081
|
||||
T2CON 00C8
|
||||
T2CON.0 00C8
|
||||
T2CON.1 00C9
|
||||
T2CON.2 00CA
|
||||
T2CON.3 00CB
|
||||
T2CON.4 00CC
|
||||
T2CON.5 00CD
|
||||
T2CON.6 00CE
|
||||
T2CON.7 00CF
|
||||
TB8 009B
|
||||
TCLK 00CC
|
||||
TCON 0088
|
||||
TCON.0 0088
|
||||
TCON.1 0089
|
||||
TCON.2 008A
|
||||
TCON.3 008B
|
||||
TCON.4 008C
|
||||
TCON.5 008D
|
||||
TCON.6 008E
|
||||
TCON.7 008F
|
||||
TF0 008D
|
||||
TF1 008F
|
||||
TF2 00CF
|
||||
TH0 008C
|
||||
TH1 008D
|
||||
TH2 00CD
|
||||
TI 0099
|
||||
TL0 008A
|
||||
TL1 008B
|
||||
TL2 00CC
|
||||
TMOD 0089
|
||||
TR0 008C
|
||||
TR1 008E
|
||||
TR2 00CA
|
||||
TXD 00B1
|
||||
_A0 = 0080 G
|
||||
_A1 = 0081 G
|
||||
_A2 = 0082 G
|
||||
_A3 = 0083 G
|
||||
_A4 = 0084 G
|
||||
_A5 = 0085 G
|
||||
_A6 = 0086 G
|
||||
_A7 = 0087 G
|
||||
_AC = 00D6 G
|
||||
_ACC = 00E0 G
|
||||
_APTR1H = 009A G
|
||||
_APTR1L = 009B G
|
||||
_AUTODAT1 = 009C G
|
||||
_AUTODAT2 = 009F G
|
||||
_AUTOPTRH2 = 009D G
|
||||
_AUTOPTRL2 = 009E G
|
||||
_AUTOPTRSETUP = 00AF G
|
||||
_B = 00F0 G
|
||||
_BPADDRH = E606 G
|
||||
_BPADDRL = E607 G
|
||||
_BREAKPT = E605 G
|
||||
_CKCON = 008E G
|
||||
_CLRERRCNT = E665 G
|
||||
_CPUCS = E600 G
|
||||
_CP_RL2 = 00C8 G
|
||||
_CT1 = E6FB G
|
||||
_CT2 = E6FC G
|
||||
_CT3 = E6FD G
|
||||
_CT4 = E6FE G
|
||||
_CY = 00D7 G
|
||||
_C_T2 = 00C9 G
|
||||
_D0 = 00B0 G
|
||||
_D1 = 00B1 G
|
||||
_D2 = 00B2 G
|
||||
_D3 = 00B3 G
|
||||
_D4 = 00B4 G
|
||||
_D5 = 00B5 G
|
||||
_D6 = 00B6 G
|
||||
_D7 = 00B7 G
|
||||
_DBUG = E6F8 G
|
||||
_DPH = 0083 G
|
||||
_DPH1 = 0085 G
|
||||
_DPL = 0082 G
|
||||
_DPL1 = 0084 G
|
||||
_DPS = 0086 G
|
||||
_EA = 00AF G
|
||||
_EI2C = 00E9 G
|
||||
_EICON = 00D8 G
|
||||
_EIE = 00E8 G
|
||||
_EIEX4 = 00EA G
|
||||
_EIEX5 = 00EB G
|
||||
_EIEX6 = 00EC G
|
||||
_EIP = 00F8 G
|
||||
_EIPX4 = 00FA G
|
||||
_EIPX5 = 00FB G
|
||||
_EIPX6 = 00FC G
|
||||
_EIUSB = 00E8 G
|
||||
_EP01STAT = 00BA G
|
||||
_EP0BCH = E68A G
|
||||
_EP0BCL = E68B G
|
||||
_EP0BUF = E740 G
|
||||
_EP0CS = E6A0 G
|
||||
_EP1INBC = E68F G
|
||||
_EP1INBUF = E7C0 G
|
||||
_EP1INCFG = E611 G
|
||||
_EP1INCS = E6A2 G
|
||||
_EP1OUTBC = E68D G
|
||||
_EP1OUTBUF = E780 G
|
||||
_EP1OUTCFG = E610 G
|
||||
_EP1OUTCS = E6A1 G
|
||||
_EP2468STAT = 00AA G
|
||||
_EP24FIFOFLGS = 00AB G
|
||||
_EP2AUTOINLENH = E620 G
|
||||
_EP2AUTOINLENL = E621 G
|
||||
_EP2BCH = E690 G
|
||||
_EP2BCL = E691 G
|
||||
_EP2CFG = E612 G
|
||||
_EP2CS = E6A3 G
|
||||
_EP2FIFOBCH = E6AB G
|
||||
_EP2FIFOBCL = E6AC G
|
||||
_EP2FIFOBUF = F000 G
|
||||
_EP2FIFOCFG = E618 G
|
||||
_EP2FIFOFLGS = E6A7 G
|
||||
_EP2FIFOIE = E650 G
|
||||
_EP2FIFOIRQ = E651 G
|
||||
_EP2FIFOPFH = E630 G
|
||||
_EP2FIFOPFL = E631 G
|
||||
_EP2GPIFFLGSEL = E6D2 G
|
||||
_EP2GPIFPFSTOP = E6D3 G
|
||||
_EP2GPIFTRIG = E6D4 G
|
||||
_EP2ISOINPKTS = E640 G
|
||||
_EP4AUTOINLENH = E622 G
|
||||
_EP4AUTOINLENL = E623 G
|
||||
_EP4BCH = E694 G
|
||||
_EP4BCL = E695 G
|
||||
_EP4CFG = E613 G
|
||||
_EP4CS = E6A4 G
|
||||
_EP4FIFOBCH = E6AD G
|
||||
_EP4FIFOBCL = E6AE G
|
||||
_EP4FIFOBUF = F400 G
|
||||
_EP4FIFOCFG = E619 G
|
||||
_EP4FIFOFLGS = E6A8 G
|
||||
_EP4FIFOIE = E652 G
|
||||
_EP4FIFOIRQ = E653 G
|
||||
_EP4FIFOPFH = E632 G
|
||||
_EP4FIFOPFL = E633 G
|
||||
_EP4GPIFFLGSEL = E6DA G
|
||||
_EP4GPIFPFSTOP = E6DB G
|
||||
_EP4GPIFTRIG = E6DC G
|
||||
_EP4ISOINPKTS = E641 G
|
||||
_EP68FIFOFLGS = 00AC G
|
||||
_EP6AUTOINLENH = E624 G
|
||||
_EP6AUTOINLENL = E625 G
|
||||
_EP6BCH = E698 G
|
||||
_EP6BCL = E699 G
|
||||
_EP6CFG = E614 G
|
||||
_EP6CS = E6A5 G
|
||||
_EP6FIFOBCH = E6AF G
|
||||
_EP6FIFOBCL = E6B0 G
|
||||
_EP6FIFOBUF = F800 G
|
||||
_EP6FIFOCFG = E61A G
|
||||
_EP6FIFOFLGS = E6A9 G
|
||||
_EP6FIFOIE = E654 G
|
||||
_EP6FIFOIRQ = E655 G
|
||||
_EP6FIFOPFH = E634 G
|
||||
_EP6FIFOPFL = E635 G
|
||||
_EP6GPIFFLGSEL = E6E2 G
|
||||
_EP6GPIFPFSTOP = E6E3 G
|
||||
_EP6GPIFTRIG = E6E4 G
|
||||
_EP6ISOINPKTS = E642 G
|
||||
_EP8AUTOINLENH = E626 G
|
||||
_EP8AUTOINLENL = E627 G
|
||||
_EP8BCH = E69C G
|
||||
_EP8BCL = E69D G
|
||||
_EP8CFG = E615 G
|
||||
_EP8CS = E6A6 G
|
||||
_EP8FIFOBCH = E6B1 G
|
||||
_EP8FIFOBCL = E6B2 G
|
||||
_EP8FIFOBUF = FC00 G
|
||||
_EP8FIFOCFG = E61B G
|
||||
_EP8FIFOFLGS = E6AA G
|
||||
_EP8FIFOIE = E656 G
|
||||
_EP8FIFOIRQ = E657 G
|
||||
_EP8FIFOPFH = E636 G
|
||||
_EP8FIFOPFL = E637 G
|
||||
_EP8GPIFFLGSEL = E6EA G
|
||||
_EP8GPIFPFSTOP = E6EB G
|
||||
_EP8GPIFTRIG = E6EC G
|
||||
_EP8ISOINPKTS = E643 G
|
||||
_EPIE = E65E G
|
||||
_EPIRQ = E65F G
|
||||
_ERESI = 00DD G
|
||||
_ERRCNTLIM = E664 G
|
||||
_ES0 = 00AC G
|
||||
_ES1 = 00AE G
|
||||
_ET0 = 00A9 G
|
||||
_ET1 = 00AB G
|
||||
_ET2 = 00AD G
|
||||
_EX0 = 00A8 G
|
||||
_EX1 = 00AA G
|
||||
_EXEN2 = 00CB G
|
||||
_EXF2 = 00CE G
|
||||
_EXIF = 0091 G
|
||||
_F0 = 00D5 G
|
||||
_FIFOPINPOLAR = E609 G
|
||||
_FIFORESET = E604 G
|
||||
_FL = 00D1 G
|
||||
_FLOWEQ0CTL = E6C8 G
|
||||
_FLOWEQ1CTL = E6C9 G
|
||||
_FLOWHOLDOFF = E6CA G
|
||||
_FLOWLOGIC = E6C7 G
|
||||
_FLOWSTATE = E6C6 G
|
||||
_FLOWSTB = E6CB G
|
||||
_FLOWSTBEDGE = E6CC G
|
||||
_FLOWSTBHPERIOD = E6CD G
|
||||
_FNADDR = E687 G
|
||||
_GPIFABORT = E6F5 G
|
||||
_GPIFADRH = E6C4 G
|
||||
_GPIFADRL = E6C5 G
|
||||
_GPIFCTLCFG = E6C3 G
|
||||
_GPIFHOLDAMOUNT = E60C G
|
||||
_GPIFIDLECS = E6C1 G
|
||||
_GPIFIDLECTL = E6C2 G
|
||||
_GPIFIE = E660 G
|
||||
_GPIFIRQ = E661 G
|
||||
_GPIFREADYCFG = E6F3 G
|
||||
_GPIFREADYSTAT = E6F4 G
|
||||
_GPIFSGLDATH = 00BD G
|
||||
_GPIFSGLDATLNOX = 00BF G
|
||||
_GPIFSGLDATLX = 00BE G
|
||||
_GPIFTCB0 = E6D1 G
|
||||
_GPIFTCB1 = E6D0 G
|
||||
_GPIFTCB2 = E6CF G
|
||||
_GPIFTCB3 = E6CE G
|
||||
_GPIFTRIG = 00BB G
|
||||
_GPIFWFSELECT = E6C0 G
|
||||
_GPIF_WAVE_DATA = E400 G
|
||||
_I2CS = E678 G
|
||||
_I2CTL = E67A G
|
||||
_I2DAT = E679 G
|
||||
_IBNIE = E658 G
|
||||
_IBNIRQ = E659 G
|
||||
_IE = 00A8 G
|
||||
_IE0 = 0089 G
|
||||
_IE1 = 008B G
|
||||
_IFCONFIG = E601 G
|
||||
_INPKTEND = E648 G
|
||||
_INT2CLR = 00A1 G
|
||||
_INT2IVEC = E666 G
|
||||
_INT4CLR = 00A2 G
|
||||
_INT4IVEC = E667 G
|
||||
_INT6 = 00DB G
|
||||
_INTSETUP = E668 G
|
||||
_IOA = 0080 G
|
||||
_IOB = 0090 G
|
||||
_IOC = 00A0 G
|
||||
_IOD = 00B0 G
|
||||
_IOE = 00B1 G
|
||||
_IP = 00B8 G
|
||||
_IT0 = 0088 G
|
||||
_IT1 = 008A G
|
||||
_MICROFRAME = E686 G
|
||||
_MPAGE = 0092 G
|
||||
_NAKIE = E65A G
|
||||
_NAKIRQ = E65B G
|
||||
_OEA = 00B2 G
|
||||
_OEB = 00B3 G
|
||||
_OEC = 00B4 G
|
||||
_OED = 00B5 G
|
||||
_OEE = 00B6 G
|
||||
_OUTPKTEND = E649 G
|
||||
_OV = 00D2 G
|
||||
_P = 00D0 G
|
||||
_PCON = 0087 G
|
||||
_PI2C = 00F9 G
|
||||
_PINFLAGSAB = E602 G
|
||||
_PINFLAGSCD = E603 G
|
||||
_PORTACFG = E670 G
|
||||
_PORTCCFG = E671 G
|
||||
_PORTECFG = E672 G
|
||||
_PS0 = 00BC G
|
||||
_PS1 = 00BE G
|
||||
_PSW = 00D0 G
|
||||
_PT0 = 00B9 G
|
||||
_PT1 = 00BB G
|
||||
_PT2 = 00BD G
|
||||
_PUSB = 00F8 G
|
||||
_PX0 = 00B8 G
|
||||
_PX1 = 00BA G
|
||||
_RB8 = 009A G
|
||||
_RB81 = 00C2 G
|
||||
_RCAP2H = 00CB G
|
||||
_RCAP2L = 00CA G
|
||||
_RCLK = 00CD G
|
||||
_REN = 009C G
|
||||
_REN1 = 00C4 G
|
||||
_RESI = 00DC G
|
||||
_RES_WAVEDATA_END = E480 G
|
||||
_REVCTL = E60B G
|
||||
_REVID = E60A G
|
||||
_RI = 0098 G
|
||||
_RI1 = 00C0 G
|
||||
_RS0 = 00D3 G
|
||||
_RS1 = 00D4 G
|
||||
_SBUF0 = 0099 G
|
||||
_SBUF1 = 00C1 G
|
||||
_SCON0 = 0098 G
|
||||
_SCON1 = 00C0 G
|
||||
_SEL = 0086 G
|
||||
_SETUPDAT = E6B8 G
|
||||
_SM0 = 009F G
|
||||
_SM01 = 00C7 G
|
||||
_SM1 = 009E G
|
||||
_SM11 = 00C6 G
|
||||
_SM2 = 009D G
|
||||
_SM21 = 00C5 G
|
||||
_SMOD1 = 00DF G
|
||||
_SP = 0081 G
|
||||
_SUDPTRCTL = E6B5 G
|
||||
_SUDPTRH = E6B3 G
|
||||
_SUDPTRL = E6B4 G
|
||||
_SUSPEND = E681 G
|
||||
_T2CON = 00C8 G
|
||||
_TB8 = 009B G
|
||||
_TB81 = 00C3 G
|
||||
_TCLK = 00CC G
|
||||
_TCON = 0088 G
|
||||
_TESTCFG = E6F9 G
|
||||
_TF0 = 008D G
|
||||
_TF1 = 008F G
|
||||
_TF2 = 00CF G
|
||||
_TH0 = 008C G
|
||||
_TH1 = 008D G
|
||||
_TH2 = 00CD G
|
||||
_TI = 0099 G
|
||||
_TI1 = 00C1 G
|
||||
_TL0 = 008A G
|
||||
_TL1 = 008B G
|
||||
_TL2 = 00CC G
|
||||
_TMOD = 0089 G
|
||||
_TOGCTL = E683 G
|
||||
_TR0 = 008C G
|
||||
_TR1 = 008E G
|
||||
_TR2 = 00CA G
|
||||
_UART230 = E608 G
|
||||
_UDMACRCH = E67D G
|
||||
_UDMACRCL = E67E G
|
||||
_UDMACRCQUAL = E67F G
|
||||
_USBCS = E680 G
|
||||
_USBERRIE = E662 G
|
||||
_USBERRIRQ = E663 G
|
||||
_USBFRAMEH = E684 G
|
||||
_USBFRAMEL = E685 G
|
||||
_USBIE = E65C G
|
||||
_USBIRQ = E65D G
|
||||
_USBTEST = E6FA G
|
||||
_WAKEUPCS = E682 G
|
||||
_XAUTODAT1 = E67B G
|
||||
_XAUTODAT2 = E67C G
|
||||
_XGPIFSGLDATH = E6F0 G
|
||||
_XGPIFSGLDATLNOX = E6F2 G
|
||||
_XGPIFSGLDATLX = E6F1 G
|
||||
4 __usb_alt_setting 0001 GR
|
||||
4 __usb_config 0000 GR
|
||||
8 __usb_got_SUDAV 0000 GR
|
||||
8 __usb_rx_overrun 0001 GR
|
||||
_app_vendor_cmd **** GX
|
||||
4 _current_config_descr 0006 GR
|
||||
4 _current_device_descr 0002 GR
|
||||
4 _current_devqual_descr 0004 GR
|
||||
15 _epcs 011A GR
|
||||
_full_speed_config_descr **** GX
|
||||
_full_speed_device_descr **** GX
|
||||
_full_speed_devqual_descr **** GX
|
||||
_fx2_reset_data_toggle **** GX
|
||||
_fx2_stall_ep0 **** GX
|
||||
_high_speed_config_descr **** GX
|
||||
_high_speed_device_descr **** GX
|
||||
_high_speed_devqual_descr **** GX
|
||||
_hook_uv **** GX
|
||||
_hook_uv_PARM_2 **** GX
|
||||
15 _isr_HIGHSPEED 0088 R
|
||||
15 _isr_SUDAV 003A R
|
||||
15 _isr_USBRESET 0043 R
|
||||
_nstring_descriptors **** GX
|
||||
4 _other_config_descr 0008 GR
|
||||
15 _plausible_endpoint 00FB GR
|
||||
15 _setup_descriptors 0000 R
|
||||
_string_descriptors **** GX
|
||||
15 _usb_handle_setup_packet 0163 GR
|
||||
15 _usb_install_handlers 00CD GR
|
||||
a 00D6
|
||||
ac 00D6
|
||||
acc 00E0
|
||||
acc.0 00E0
|
||||
acc.1 00E1
|
||||
acc.2 00E2
|
||||
acc.3 00E3
|
||||
acc.4 00E4
|
||||
acc.5 00E5
|
||||
acc.6 00E6
|
||||
acc.7 00E7
|
||||
ar0 = 0000
|
||||
ar1 = 0001
|
||||
ar2 = 0002
|
||||
ar3 = 0003
|
||||
ar4 = 0004
|
||||
ar5 = 0005
|
||||
ar6 = 0006
|
||||
ar7 = 0007
|
||||
b 00F0
|
||||
b.0 00F0
|
||||
b.1 00F1
|
||||
b.2 00F2
|
||||
b.3 00F3
|
||||
b.4 00F4
|
||||
b.5 00F5
|
||||
b.6 00F6
|
||||
b.7 00F7
|
||||
3 b0 = 8000 R
|
||||
3 b1 = 8100 R
|
||||
3 b2 = 8200 R
|
||||
3 b3 = 8300 R
|
||||
3 b4 = 8400 R
|
||||
3 b5 = 8500 R
|
||||
3 b6 = 8600 R
|
||||
3 b7 = 8700 R
|
||||
3 bits 0000 R
|
||||
cprl2 00C8
|
||||
ct2 00C9
|
||||
cy 00D7
|
||||
dph 0083
|
||||
dpl 0082
|
||||
ea 00AF
|
||||
es 00AC
|
||||
et0 00A9
|
||||
et1 00AB
|
||||
et2 00AD
|
||||
ex0 00A8
|
||||
ex1 00AA
|
||||
exen2 00CB
|
||||
exf2 00CE
|
||||
f0 00D5
|
||||
ie 00A8
|
||||
ie.0 00A8
|
||||
ie.1 00A9
|
||||
ie.2 00AA
|
||||
ie.3 00AB
|
||||
ie.4 00AC
|
||||
ie.5 00AD
|
||||
ie.7 00AF
|
||||
ie0 0089
|
||||
ie1 008B
|
||||
int0 00B2
|
||||
int1 00B3
|
||||
ip 00B8
|
||||
ip.0 00B8
|
||||
ip.1 00B9
|
||||
ip.2 00BA
|
||||
ip.3 00BB
|
||||
ip.4 00BC
|
||||
ip.5 00BD
|
||||
it0 0088
|
||||
it1 008A
|
||||
ov 00D2
|
||||
p 00D0
|
||||
p0 0080
|
||||
p0.0 0080
|
||||
p0.1 0081
|
||||
p0.2 0082
|
||||
p0.3 0083
|
||||
p0.4 0084
|
||||
p0.5 0085
|
||||
p0.6 0086
|
||||
p0.7 0087
|
||||
p1 0090
|
||||
p1.0 0090
|
||||
p1.1 0091
|
||||
p1.2 0092
|
||||
p1.3 0093
|
||||
p1.4 0094
|
||||
p1.5 0095
|
||||
p1.6 0096
|
||||
p1.7 0097
|
||||
p2 00A0
|
||||
p2.0 00A0
|
||||
p2.1 00A1
|
||||
p2.2 00A2
|
||||
p2.3 00A3
|
||||
p2.4 00A4
|
||||
p2.5 00A5
|
||||
p2.6 00A6
|
||||
p2.7 00A7
|
||||
p3 00B0
|
||||
p3.0 00B0
|
||||
p3.1 00B1
|
||||
p3.2 00B2
|
||||
p3.3 00B3
|
||||
p3.4 00B4
|
||||
p3.5 00B5
|
||||
p3.6 00B6
|
||||
p3.7 00B7
|
||||
pcon 0087
|
||||
ps 00BC
|
||||
psw 00D0
|
||||
psw.0 00D0
|
||||
psw.1 00D1
|
||||
psw.2 00D2
|
||||
psw.3 00D3
|
||||
psw.4 00D4
|
||||
psw.5 00D5
|
||||
psw.6 00D6
|
||||
psw.7 00D7
|
||||
pt0 00B9
|
||||
pt1 00BB
|
||||
pt2 00BD
|
||||
px0 00B8
|
||||
px1 00BA
|
||||
rb8 009A
|
||||
rcap2h 00CB
|
||||
rcap2l 00CA
|
||||
rclk 00CD
|
||||
ren 009C
|
||||
ri 0098
|
||||
rs0 00D3
|
||||
rs1 00D4
|
||||
rxd 00B0
|
||||
sbuf 0099
|
||||
scon 0098
|
||||
scon.0 0098
|
||||
scon.1 0099
|
||||
scon.2 009A
|
||||
scon.3 009B
|
||||
scon.4 009C
|
||||
scon.5 009D
|
||||
scon.6 009E
|
||||
scon.7 009F
|
||||
sm0 009F
|
||||
sm1 009E
|
||||
sm2 009D
|
||||
sp 0081
|
||||
t2con 00C8
|
||||
t2con.0 00C8
|
||||
t2con.1 00C9
|
||||
t2con.2 00CA
|
||||
t2con.3 00CB
|
||||
t2con.4 00CC
|
||||
t2con.5 00CD
|
||||
t2con.6 00CE
|
||||
t2con.7 00CF
|
||||
tb8 009B
|
||||
tclk 00CC
|
||||
tcon 0088
|
||||
tcon.0 0088
|
||||
tcon.1 0089
|
||||
tcon.2 008A
|
||||
tcon.3 008B
|
||||
tcon.4 008C
|
||||
tcon.5 008D
|
||||
tcon.6 008E
|
||||
tcon.7 008F
|
||||
tf0 008D
|
||||
tf1 008F
|
||||
tf2 00CF
|
||||
th0 008C
|
||||
th1 008D
|
||||
th2 00CD
|
||||
ti 0099
|
||||
tl0 008A
|
||||
tl1 008B
|
||||
tl2 00CC
|
||||
tmod 0089
|
||||
tr0 008C
|
||||
tr1 008E
|
||||
tr2 00CA
|
||||
txd 00B1
|
||||
|
||||
ASxxxx Assembler V01.70 + NoICE + SDCC mods + Flat24 Feb-1999 (Intel 8051), page 2.
|
||||
|
||||
Area Table
|
||||
|
||||
0 _CODE size 0 flags 0
|
||||
1 RSEG size 0 flags 0
|
||||
2 REG_BANK_0 size 8 flags 4
|
||||
3 BIT_BANK size 1 flags 4
|
||||
4 DSEG size A flags 0
|
||||
5 OSEG size 0 flags 4
|
||||
6 ISEG size 0 flags 0
|
||||
7 IABS size 0 flags 8
|
||||
8 BSEG size 2 flags 80
|
||||
9 PSEG size 0 flags 50
|
||||
A XSEG size 0 flags 40
|
||||
B XABS size 0 flags 48
|
||||
C HOME size 0 flags 20
|
||||
D GSINIT0 size 0 flags 20
|
||||
E GSINIT1 size 0 flags 20
|
||||
F GSINIT2 size 0 flags 20
|
||||
10 GSINIT3 size 0 flags 20
|
||||
11 GSINIT4 size 0 flags 20
|
||||
12 GSINIT5 size 0 flags 20
|
||||
13 GSINIT size 6 flags 20
|
||||
14 GSFINAL size 0 flags 20
|
||||
15 CSEG size 424 flags 20
|
||||
16 CONST size 0 flags 20
|
||||
17 CABS size 0 flags 28
|
||||
23
firmware/GN3S_v2/src/Makefile
Normal file
23
firmware/GN3S_v2/src/Makefile
Normal file
@@ -0,0 +1,23 @@
|
||||
INCLUDES=-I../include
|
||||
CC=sdcc -mmcs51 --no-xinit-opt
|
||||
|
||||
all: firmware install clean
|
||||
|
||||
firmware: gn3s_main.c usrp_common.c init_gpif.c gn3s_gpif.c gn3s_se4120.c
|
||||
$(CC) $(INCLUDES) -c gn3s_main.c -o gn3s_main.rel
|
||||
$(CC) $(INCLUDES) -c usrp_common.c -o usrp_common.rel
|
||||
$(CC) $(INCLUDES) -c init_gpif.c -o init_gpif.rel
|
||||
$(CC) $(INCLUDES) -c gn3s_gpif.c -o gn3s_gpif.rel
|
||||
$(CC) $(INCLUDES) -c gn3s_se4120.c -o gn3s_se4110.rel
|
||||
$(CC) $(INCLUDES) -c eeprom.c -o eeprom.rel
|
||||
asx8051 -plosgff vectors.a51
|
||||
asx8051 -plosgff usb_descriptors.a51
|
||||
asx8051 -plosgff _startup.a51
|
||||
$(CC) $(INCLUDES) --code-loc 0x0000 --code-size 0x1800 --xram-loc 0x1800 --xram-size 0x0800 -Wl '-b USBDESCSEG = 0xE000' -L ../lib libfx2.lib -o gn3s_firmware.ihx vectors.rel gn3s_main.rel usrp_common.rel init_gpif.rel gn3s_gpif.rel gn3s_se4110.rel eeprom.rel usb_descriptors.rel _startup.rel
|
||||
|
||||
install:
|
||||
cp gn3s_firmware.ihx ../bin/
|
||||
@rm gn3s_firmware.ihx
|
||||
|
||||
clean:
|
||||
rm -f *.ihx *.rel *.rst *.lnk *.lst *.map *.asm *.sym *.mem
|
||||
80
firmware/GN3S_v2/src/_startup.a51
Normal file
80
firmware/GN3S_v2/src/_startup.a51
Normal file
@@ -0,0 +1,80 @@
|
||||
;;; -*- asm -*-
|
||||
;;;
|
||||
;;; Copyright 2003,2004 Free Software Foundation, Inc.
|
||||
;;;
|
||||
;;; This file is part of GNU Radio
|
||||
;;;
|
||||
;;; GNU Radio is free software; you can redistribute it and/or modify
|
||||
;;; it under the terms of the GNU General Public License as published by
|
||||
;;; the Free Software Foundation; either version 2, or (at your option)
|
||||
;;; any later version.
|
||||
;;;
|
||||
;;; GNU Radio is distributed in the hope that it will be useful,
|
||||
;;; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
;;; GNU General Public License for more details.
|
||||
;;;
|
||||
;;; You should have received a copy of the GNU General Public License
|
||||
;;; along with GNU Radio; see the file COPYING. If not, write to
|
||||
;;; the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
|
||||
;;; Boston, MA 02111-1307, USA.
|
||||
|
||||
|
||||
;;; The default external memory initialization provided by sdcc is not
|
||||
;;; appropriate to the FX2. This is derived from the sdcc code, but uses
|
||||
;;; the FX2 specific _MPAGE sfr.
|
||||
|
||||
|
||||
;; .area XISEG (XDATA) ; the initialized external data area
|
||||
;; .area XINIT (CODE) ; the code space consts to init XISEG
|
||||
.area XSEG (XDATA) ; zero initialized xdata
|
||||
.area USBDESCSEG (XDATA) ; usb descriptors
|
||||
|
||||
|
||||
.area CSEG (CODE)
|
||||
|
||||
;; sfr that sets upper address byte of MOVX using @r0 or @r1
|
||||
_MPAGE = 0x0092
|
||||
|
||||
__sdcc_external_startup::
|
||||
;; This system is now compiled with the --no-xinit-opt
|
||||
;; which means that any initialized XDATA is handled
|
||||
;; inline by code in the GSINIT segs emitted for each file.
|
||||
;;
|
||||
;; We zero XSEG and all of the internal ram to ensure
|
||||
;; a known good state for uninitialized variables.
|
||||
|
||||
; _mcs51_genRAMCLEAR() start
|
||||
mov r0,#l_XSEG
|
||||
mov a,r0
|
||||
orl a,#(l_XSEG >> 8)
|
||||
jz 00002$
|
||||
mov r1,#((l_XSEG + 255) >> 8)
|
||||
mov dptr,#s_XSEG
|
||||
clr a
|
||||
|
||||
00001$: movx @dptr,a
|
||||
inc dptr
|
||||
djnz r0,00001$
|
||||
djnz r1,00001$
|
||||
|
||||
;; We're about to clear internal memory. This will overwrite
|
||||
;; the stack which contains our return address.
|
||||
;; Pop our return address into DPH, DPL
|
||||
00002$: pop dph
|
||||
pop dpl
|
||||
|
||||
;; R0 and A contain 0. This loop will execute 256 times.
|
||||
;;
|
||||
;; FWIW the first iteration writes direct address 0x00,
|
||||
;; which is the location of r0. We get lucky, we're
|
||||
;; writing the correct value (0)
|
||||
|
||||
00003$: mov @r0,a
|
||||
djnz r0,00003$
|
||||
|
||||
push dpl ; restore our return address
|
||||
push dph
|
||||
|
||||
mov dpl,#0 ; indicate that data init is still required
|
||||
ret
|
||||
114
firmware/GN3S_v2/src/edit-gpif
Normal file
114
firmware/GN3S_v2/src/edit-gpif
Normal file
@@ -0,0 +1,114 @@
|
||||
#!/usr/bin/env python
|
||||
# -*- Python -*-
|
||||
#
|
||||
# Copyright 2003 Free Software Foundation, Inc.
|
||||
#
|
||||
# This file is part of GNU Radio
|
||||
#
|
||||
# GNU Radio is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; either version 2, or (at your option)
|
||||
# any later version.
|
||||
#
|
||||
# GNU Radio is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with GNU Radio; see the file COPYING. If not, write to
|
||||
# the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
|
||||
# Boston, MA 02111-1307, USA.
|
||||
#
|
||||
|
||||
|
||||
# Edit the gpif.c file generated by the Cypress GPIF Designer Tool and
|
||||
# produce usrp_gpif.c, and usrp_gpif_inline.h, files suitable for our
|
||||
# uses.
|
||||
|
||||
import re
|
||||
import string
|
||||
import sys
|
||||
|
||||
def check_flow_state (line, flow_state_dict):
|
||||
mo = re.match (r'/\* Wave (\d) FlowStates \*/ (.*),', line)
|
||||
if mo:
|
||||
wave = int (mo.group (1))
|
||||
data = mo.group (2)
|
||||
split = data.split (',', 8)
|
||||
v = map (lambda x : int (x, 16), split)
|
||||
# print "%s, %s" % (wave, data)
|
||||
# print "split: ", split
|
||||
# print "v : ", v
|
||||
flow_state_dict[wave] = v
|
||||
|
||||
|
||||
def delta (xseq, yseq):
|
||||
# set subtraction
|
||||
z = []
|
||||
for x in xseq:
|
||||
if x not in yseq:
|
||||
z.append (x)
|
||||
return z
|
||||
|
||||
|
||||
def write_define (output, name, pairs):
|
||||
output.write ('#define %s()\t\\\n' % name)
|
||||
output.write ('do {\t\t\t\t\t\\\n')
|
||||
for reg, val in pairs:
|
||||
output.write ('%14s = 0x%02x;\t\t\t\\\n' % (reg, val))
|
||||
output.write ('} while (0)\n\n')
|
||||
|
||||
def write_inlines (output, dict):
|
||||
regs = ['FLOWSTATE', 'FLOWLOGIC', 'FLOWEQ0CTL', 'FLOWEQ1CTL', 'FLOWHOLDOFF',
|
||||
'FLOWSTB', 'FLOWSTBEDGE', 'FLOWSTBHPERIOD', 'GPIFHOLDAMOUNT']
|
||||
|
||||
READ_FLOW_STATE = 2
|
||||
WRITE_FLOW_STATE = 3
|
||||
|
||||
read_info = zip (regs, dict[READ_FLOW_STATE])
|
||||
write_info = zip (regs, dict[WRITE_FLOW_STATE])
|
||||
|
||||
output.write ('''/*
|
||||
* Machine generated by "edit-gpif". Do not edit by hand.
|
||||
*/
|
||||
|
||||
''')
|
||||
write_define (output, 'setup_flowstate_common', read_info)
|
||||
write_define (output, 'setup_flowstate_read', delta (read_info, write_info))
|
||||
write_define (output, 'setup_flowstate_write', delta (write_info, read_info))
|
||||
|
||||
|
||||
def edit_gpif (input_name, output_name, inline_name):
|
||||
input = open (input_name, 'r')
|
||||
output = open (output_name, 'w')
|
||||
inline = open (inline_name, 'w')
|
||||
flow_state_dict = {}
|
||||
|
||||
output.write ('''/*
|
||||
* Machine generated by "edit-gpif". Do not edit by hand.
|
||||
*/
|
||||
|
||||
''')
|
||||
|
||||
while 1:
|
||||
line = input.readline ()
|
||||
line = string.replace (line, '\r','')
|
||||
line = re.sub (r' *$', r'', line)
|
||||
|
||||
check_flow_state (line, flow_state_dict)
|
||||
|
||||
line = re.sub (r'#include', r'// #include', line)
|
||||
line = re.sub (r'xdata ', r'', line)
|
||||
if re.search (r'GpifInit', line):
|
||||
break
|
||||
|
||||
output.write (line)
|
||||
|
||||
output.close ()
|
||||
write_inlines (inline, flow_state_dict)
|
||||
inline.close ()
|
||||
|
||||
|
||||
# gpif.c usrp_gpif.c usrp_gpif_inline.h
|
||||
edit_gpif (sys.argv[1], sys.argv[2], sys.argv[3])
|
||||
239
firmware/GN3S_v2/src/eeprom.c
Normal file
239
firmware/GN3S_v2/src/eeprom.c
Normal file
@@ -0,0 +1,239 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// File: eeprom.c
|
||||
// Contents: EEPROM update firmware source. (Write only)
|
||||
//
|
||||
// indent 3. NO TABS!
|
||||
//
|
||||
// Copyright (c) 2002 Cypress Semiconductor
|
||||
//
|
||||
// $Workfile: eeprom.c $
|
||||
// $Date: 9/07/05 2:54p $
|
||||
// $Revision: 1 $
|
||||
//-----------------------------------------------------------------------------
|
||||
//#include "fx2.h"
|
||||
#include "fx2regs.h"
|
||||
#include "eeprom.h"
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Write up to one page of data to the EEPROM.
|
||||
// Returns 0 on success, 1 on failure
|
||||
// Normally called within a while() loop so that errors are retried:
|
||||
// while (EEPROMWritePage(....))
|
||||
// ;
|
||||
BYTE EEPROMWritePage(WORD addr, BYTE xdata * ptr, BYTE len)
|
||||
{
|
||||
BYTE i;
|
||||
BYTE retval;
|
||||
|
||||
//EEPROM_DISABLE_WRITE_PROTECT();
|
||||
|
||||
// Make sure the i2c interface is idle
|
||||
EEWaitForStop();
|
||||
|
||||
// write the START bit and i2c device address
|
||||
EEStartAndAddr();
|
||||
|
||||
if(EEWaitForAck())
|
||||
{
|
||||
retval = 1;
|
||||
goto EXIT_WP;
|
||||
}
|
||||
|
||||
// write the eeprom offset
|
||||
if (DB_Addr)
|
||||
{
|
||||
I2DAT = MSB(addr);
|
||||
if(EEWaitForAck())
|
||||
{
|
||||
retval = 1;
|
||||
goto EXIT_WP;
|
||||
}
|
||||
}
|
||||
I2DAT = LSB(addr);
|
||||
if(EEWaitForAck())
|
||||
{
|
||||
retval = 1;
|
||||
goto EXIT_WP;
|
||||
}
|
||||
|
||||
// Write the data Page
|
||||
for (i = 0; i < len; i++)
|
||||
{
|
||||
I2DAT = *ptr++;
|
||||
if(EEWaitForDone())
|
||||
{
|
||||
retval = 1;
|
||||
goto EXIT_WP;
|
||||
}
|
||||
}
|
||||
I2CS |= bmSTOP;
|
||||
WaitForEEPROMWrite();
|
||||
|
||||
retval = 0;
|
||||
|
||||
EXIT_WP:
|
||||
EEPROM_ENABLE_WRITE_PROTECT();
|
||||
return(retval);
|
||||
}
|
||||
|
||||
void EEStartAndAddr()
|
||||
{
|
||||
I2CS = bmSTART;
|
||||
I2DAT = I2C_Addr << 1;
|
||||
}
|
||||
|
||||
// 0x2e in assembly, less than 0x20 with compiler optimization!!
|
||||
void WaitForEEPROMWrite()
|
||||
{
|
||||
EEWaitForStop();
|
||||
waitForBusy:
|
||||
EEStartAndAddr();
|
||||
|
||||
EEWaitForDone();
|
||||
I2CS |= bmSTOP; // ; Set the STOP bit
|
||||
EEWaitForStop();
|
||||
|
||||
if (!(I2CS & bmACK)) // If no ACK, try again.
|
||||
goto waitForBusy;
|
||||
}
|
||||
|
||||
void EEWaitForStop()
|
||||
{
|
||||
// Data should not be written to I2CS or I2DAT until the STOP bit returns low.
|
||||
while (I2CS & bmSTOP)
|
||||
;
|
||||
}
|
||||
|
||||
// Returns 0 on success, 1 on failure
|
||||
BYTE EEPROMRead(WORD addr, BYTE length, BYTE xdata *buf)
|
||||
{
|
||||
BYTE i;
|
||||
|
||||
// Make sure the i2c interface is idle
|
||||
EEWaitForStop();
|
||||
|
||||
// write the START bit and i2c device address
|
||||
EEStartAndAddr();
|
||||
|
||||
if(EEWaitForAck())
|
||||
return(1);
|
||||
|
||||
// write the eeprom offset
|
||||
if (DB_Addr)
|
||||
{
|
||||
I2DAT = MSB(addr);
|
||||
if(EEWaitForAck())
|
||||
return(1);
|
||||
}
|
||||
I2DAT = LSB(addr);
|
||||
if(EEWaitForAck())
|
||||
return(1);
|
||||
|
||||
I2CS = bmSTART;
|
||||
|
||||
// send the read command
|
||||
I2DAT = (I2C_Addr << 1) | 1;
|
||||
if(EEWaitForDone())
|
||||
return(1);
|
||||
|
||||
// read dummy byte
|
||||
i = I2DAT;
|
||||
if(EEWaitForDone())
|
||||
return(1);
|
||||
|
||||
for (i=0; i < (length - 1); i++)
|
||||
{
|
||||
*(buf+i) = I2DAT;
|
||||
if(EEWaitForDone())
|
||||
return(1);
|
||||
}
|
||||
|
||||
I2CS = bmLASTRD;
|
||||
if(EEWaitForDone())
|
||||
return(1);
|
||||
|
||||
*(buf+i) = I2DAT;
|
||||
if(EEWaitForDone())
|
||||
return(1);
|
||||
|
||||
I2CS = bmSTOP;
|
||||
|
||||
i = I2DAT;
|
||||
return(0);
|
||||
}
|
||||
|
||||
// Return 0 for ok, 1 for error
|
||||
BYTE EEWaitForDone()
|
||||
{
|
||||
BYTE i;
|
||||
|
||||
while (!((i = I2CS) & 1)) // Poll the done bit
|
||||
;
|
||||
if (i & bmBERR)
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
// Return 0 for ok, 1 for error
|
||||
// Same as wait for done, but checks for ACK as well
|
||||
BYTE EEWaitForAck()
|
||||
{
|
||||
BYTE i;
|
||||
|
||||
while (!((i = I2CS) & 1)) // Poll the done bit
|
||||
;
|
||||
if (i & bmBERR)
|
||||
return 1;
|
||||
else if (!(i & bmACK))
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
// Determine the page size supported by the EEPROM. All of the EEPROMS we use
|
||||
// (Atmel, Xicor and Microchip) will wrap their page address pointer if the page
|
||||
// buffer is overrun. We write 128 incrementing bytes to the EEPROM. We then
|
||||
// read the block back. If location 0 is right, the page size is 128.
|
||||
// If location 0 is wrong, it directly provides a mask for the page size.
|
||||
// For example, if the page size is 4, location 0 will contain 0x7c
|
||||
BYTE EEPROMGetPageSize()
|
||||
{
|
||||
#define MAX_PAGE_SIZE 64
|
||||
BYTE xdata testData[MAX_PAGE_SIZE];
|
||||
BYTE xdata saveData[MAX_PAGE_SIZE];
|
||||
BYTE i;
|
||||
BYTE retval;
|
||||
|
||||
if (!DB_Addr)
|
||||
return(1);
|
||||
|
||||
EEPROMRead(0, MAX_PAGE_SIZE, saveData);
|
||||
for (i = 0; i < MAX_PAGE_SIZE; i++)
|
||||
{
|
||||
testData[i] = i;
|
||||
}
|
||||
EEPROMWritePage(0, testData, MAX_PAGE_SIZE);
|
||||
for (i = 0; i < MAX_PAGE_SIZE; i++)
|
||||
{
|
||||
testData[i] = ~i;
|
||||
}
|
||||
EEPROMRead(0, MAX_PAGE_SIZE, testData);
|
||||
i = testData[0];
|
||||
if (i & 1)
|
||||
retval = 1; // Couldn't read back large EEPROM. Assume page size 1.
|
||||
else
|
||||
{
|
||||
i = (MAX_PAGE_SIZE-1) ^ i;
|
||||
i++;
|
||||
retval = i;
|
||||
}
|
||||
|
||||
for (i = 0; i < MAX_PAGE_SIZE; i+= retval)
|
||||
EEPROMWritePage(i, saveData, retval);
|
||||
|
||||
return(retval);
|
||||
}
|
||||
|
||||
206
firmware/GN3S_v2/src/gn3s_gpif.c
Normal file
206
firmware/GN3S_v2/src/gn3s_gpif.c
Normal file
@@ -0,0 +1,206 @@
|
||||
/*
|
||||
* Machine generated by "edit-gpif". Do not edit by hand.
|
||||
*/
|
||||
|
||||
// This program configures the General Programmable Interface (GPIF) for FX2.
|
||||
// Please do not modify sections of text which are marked as "DO NOT EDIT ...".
|
||||
//
|
||||
// DO NOT EDIT ...
|
||||
// GPIF Initialization
|
||||
// Interface Timing Async
|
||||
// Internal Ready Init IntRdy=1
|
||||
// CTL Out Tristate-able Binary
|
||||
// SingleWrite WF Select 1
|
||||
// SingleRead WF Select 0
|
||||
// FifoWrite WF Select 3
|
||||
// FifoRead WF Select 2
|
||||
// Data Bus Idle Drive Tristate
|
||||
// END DO NOT EDIT
|
||||
|
||||
// DO NOT EDIT ...
|
||||
// GPIF Wave Names
|
||||
// Wave 0 = Single R
|
||||
// Wave 1 = Single W
|
||||
// Wave 2 = FIFO Rea
|
||||
// Wave 3 = FIFO Wri
|
||||
|
||||
// GPIF Ctrl Outputs Level
|
||||
// CTL 0 = BOGUS CMOS
|
||||
// CTL 1 = CTL1 CMOS
|
||||
// CTL 2 = CTL2 CMOS
|
||||
// CTL 3 = CTL3 CMOS
|
||||
// CTL 4 = CTL4 CMOS
|
||||
// CTL 5 = CTL5 CMOS
|
||||
|
||||
// GPIF Rdy Inputs
|
||||
// RDY0 = ADC_CLK
|
||||
// RDY1 = RDY1
|
||||
// RDY2 = RDY2
|
||||
// RDY3 = RDY3
|
||||
// RDY4 = RDY4
|
||||
// RDY5 = TCXpire
|
||||
// FIFOFlag = FIFOFlag
|
||||
// IntReady = IntReady
|
||||
// END DO NOT EDIT
|
||||
// DO NOT EDIT ...
|
||||
//
|
||||
// GPIF Waveform 0: Single R
|
||||
//
|
||||
// Interval 0 1 2 3 4 5 6 Idle (7)
|
||||
// _________ _________ _________ _________ _________ _________ _________ _________
|
||||
//
|
||||
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
|
||||
// DataMode NO Data NO Data NO Data NO Data NO Data NO Data NO Data
|
||||
// NextData SameData SameData SameData SameData SameData SameData SameData
|
||||
// Int Trig No Int No Int No Int No Int No Int No Int No Int
|
||||
// IF/Wait Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
|
||||
// Term A
|
||||
// LFunc
|
||||
// Term B
|
||||
// Branch1
|
||||
// Branch0
|
||||
// Re-Exec
|
||||
// Sngl/CRC Default Default Default Default Default Default Default
|
||||
// BOGUS 0 0 0 0 0 0 0 0
|
||||
// CTL1 0 0 0 0 0 0 0 0
|
||||
// CTL2 0 0 0 0 0 0 0 0
|
||||
// CTL3 0 0 0 0 0 0 0 0
|
||||
// CTL4 0 0 0 0 0 0 0 0
|
||||
// CTL5 0 0 0 0 0 0 0 0
|
||||
//
|
||||
// END DO NOT EDIT
|
||||
// DO NOT EDIT ...
|
||||
//
|
||||
// GPIF Waveform 1: Single W
|
||||
//
|
||||
// Interval 0 1 2 3 4 5 6 Idle (7)
|
||||
// _________ _________ _________ _________ _________ _________ _________ _________
|
||||
//
|
||||
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
|
||||
// DataMode NO Data NO Data NO Data NO Data NO Data NO Data NO Data
|
||||
// NextData SameData SameData SameData SameData SameData SameData SameData
|
||||
// Int Trig No Int No Int No Int No Int No Int No Int No Int
|
||||
// IF/Wait Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
|
||||
// Term A
|
||||
// LFunc
|
||||
// Term B
|
||||
// Branch1
|
||||
// Branch0
|
||||
// Re-Exec
|
||||
// Sngl/CRC Default Default Default Default Default Default Default
|
||||
// BOGUS 0 0 0 0 0 0 0 0
|
||||
// CTL1 0 0 0 0 0 0 0 0
|
||||
// CTL2 0 0 0 0 0 0 0 0
|
||||
// CTL3 0 0 0 0 0 0 0 0
|
||||
// CTL4 0 0 0 0 0 0 0 0
|
||||
// CTL5 0 0 0 0 0 0 0 0
|
||||
//
|
||||
// END DO NOT EDIT
|
||||
// DO NOT EDIT ...
|
||||
//
|
||||
// GPIF Waveform 2: FIFO Rea
|
||||
//
|
||||
// Interval 0 1 2 3 4 5 6 Idle (7)
|
||||
// _________ _________ _________ _________ _________ _________ _________ _________
|
||||
//
|
||||
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
|
||||
// DataMode Activate Activate Activate Activate Activate Activate Activate
|
||||
// NextData SameData SameData SameData SameData SameData SameData SameData
|
||||
// Int Trig No Int No Int No Int No Int No Int No Int No Int
|
||||
// IF/Wait IF Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
|
||||
// Term A FIFOFlag
|
||||
// LFunc AND
|
||||
// Term B FIFOFlag
|
||||
// Branch1 ThenIdle
|
||||
// Branch0 Else 0
|
||||
// Re-Exec No
|
||||
// Sngl/CRC Default Default Default Default Default Default Default
|
||||
// BOGUS 0 0 0 0 0 0 0 0
|
||||
// CTL1 0 0 0 0 0 0 0 0
|
||||
// CTL2 0 0 0 0 0 0 0 0
|
||||
// CTL3 0 0 0 0 0 0 0 0
|
||||
// CTL4 0 0 0 0 0 0 0 0
|
||||
// CTL5 0 0 0 0 0 0 0 0
|
||||
//
|
||||
// END DO NOT EDIT
|
||||
// DO NOT EDIT ...
|
||||
//
|
||||
// GPIF Waveform 3: FIFO Wri
|
||||
//
|
||||
// Interval 0 1 2 3 4 5 6 Idle (7)
|
||||
// _________ _________ _________ _________ _________ _________ _________ _________
|
||||
//
|
||||
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
|
||||
// DataMode Activate Activate Activate Activate Activate Activate Activate
|
||||
// NextData SameData SameData SameData SameData SameData SameData SameData
|
||||
// Int Trig No Int No Int No Int No Int No Int No Int No Int
|
||||
// IF/Wait IF Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
|
||||
// Term A FIFOFlag
|
||||
// LFunc AND
|
||||
// Term B FIFOFlag
|
||||
// Branch1 ThenIdle
|
||||
// Branch0 Else 0
|
||||
// Re-Exec No
|
||||
// Sngl/CRC Default Default Default Default Default Default Default
|
||||
// BOGUS 0 0 0 0 0 0 0 0
|
||||
// CTL1 0 0 0 0 0 0 0 0
|
||||
// CTL2 0 0 0 0 0 0 0 0
|
||||
// CTL3 0 0 0 0 0 0 0 0
|
||||
// CTL4 0 0 0 0 0 0 0 0
|
||||
// CTL5 0 0 0 0 0 0 0 0
|
||||
//
|
||||
// END DO NOT EDIT
|
||||
|
||||
// GPIF Program Code
|
||||
|
||||
// DO NOT EDIT ...
|
||||
// #include "fx2.h"
|
||||
// #include "fx2regs.h"
|
||||
// #include "fx2sdly.h" // SYNCDELAY macro
|
||||
// END DO NOT EDIT
|
||||
|
||||
// DO NOT EDIT ...
|
||||
const char WaveData[128] =
|
||||
{
|
||||
// Wave 0
|
||||
/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
|
||||
/* Opcode*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* Output*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
|
||||
// Wave 1
|
||||
/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
|
||||
/* Opcode*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* Output*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
|
||||
// Wave 2
|
||||
/* LenBr */ 0x38, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
|
||||
/* Opcode*/ 0x03, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00,
|
||||
/* Output*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* LFun */ 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
|
||||
// Wave 3
|
||||
/* LenBr */ 0x38, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
|
||||
/* Opcode*/ 0x03, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00,
|
||||
/* Output*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* LFun */ 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
|
||||
};
|
||||
// END DO NOT EDIT
|
||||
|
||||
// DO NOT EDIT ...
|
||||
const char FlowStates[36] =
|
||||
{
|
||||
/* Wave 0 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
/* Wave 1 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
/* Wave 2 FlowStates */ 0x80,0xED,0x00,0x00,0x00,0x00,0x03,0x02,0x00,
|
||||
/* Wave 3 FlowStates */ 0x80,0xEE,0x00,0x00,0x00,0x00,0x03,0x02,0x00,
|
||||
};
|
||||
// END DO NOT EDIT
|
||||
|
||||
// DO NOT EDIT ...
|
||||
const char InitData[7] =
|
||||
{
|
||||
/* Regs */ 0xA0,0x00,0x00,0x00,0xAE,0x4E,0x00
|
||||
};
|
||||
// END DO NOT EDIT
|
||||
|
||||
// TO DO: You may add additional code below.
|
||||
|
||||
1
firmware/GN3S_v2/src/gn3s_main.adb
Normal file
1
firmware/GN3S_v2/src/gn3s_main.adb
Normal file
@@ -0,0 +1 @@
|
||||
M:gn3s_main
|
||||
344
firmware/GN3S_v2/src/gn3s_main.c
Normal file
344
firmware/GN3S_v2/src/gn3s_main.c
Normal file
@@ -0,0 +1,344 @@
|
||||
/*
|
||||
* Code from: USRP - Universal Software Radio Peripheral (GNU Radio)
|
||||
*
|
||||
* Initial modifications by:
|
||||
*
|
||||
* Stephan Esterhuizen, Aerospace Engineering Sciences
|
||||
* University of Colorado at Boulder
|
||||
* Boulder CO, USA
|
||||
*
|
||||
* Further modifications for use with the SiGe USB module to accompany
|
||||
* the textbook: "A Software-Defined GPS and Galileo Receiver: A
|
||||
* Single-Frequency Approach" by Kai Borre, Dennis Akos, et.al. by:
|
||||
*
|
||||
* Marcus Junered, GNSS Research Group
|
||||
* Lulea University of Technology
|
||||
* Lulea, Sweden
|
||||
*
|
||||
* http://ccar.colorado.edu/gnss
|
||||
*
|
||||
* ---------------------------------------------------------------------
|
||||
*
|
||||
* GN3S - GNSS IF Streamer for Windows
|
||||
* Copyright (C) 2006 Marcus Junered
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#include "gn3s_main.h"
|
||||
|
||||
|
||||
BYTE DB_Addr; // Dual Byte Address stat
|
||||
BYTE I2C_Addr; // I2C address
|
||||
|
||||
volatile WORD guardTick = 0;
|
||||
volatile WORD guardCnt = 0;
|
||||
|
||||
// Set the page size to 0, so we know to calculate it on an EEPROM write
|
||||
BYTE EE_Page_Size = 0;
|
||||
|
||||
|
||||
void main(void) {
|
||||
init_usrp();
|
||||
init_gpif();
|
||||
init_se4110();
|
||||
|
||||
TD_Init(); // Init fucntion for A9 vendor commands
|
||||
|
||||
EA = 0; // disable all interrupts
|
||||
|
||||
setup_autovectors();
|
||||
usb_install_handlers();
|
||||
|
||||
EIEX4 = 1; // disable INT4 FIXME
|
||||
EA = 1; // global interrupt enable
|
||||
|
||||
fx2_renumerate(); // simulates disconnect / reconnect
|
||||
|
||||
// enable_se4110();
|
||||
program_3w();
|
||||
//Javi: disable capture filesize limitation
|
||||
//hook_timer_tick((unsigned int)guardC);
|
||||
|
||||
main_loop();
|
||||
}
|
||||
|
||||
|
||||
|
||||
static
|
||||
void get_ep0_data(void)
|
||||
{
|
||||
EP0BCL = 0; // arm EP0 for OUT xfer. This sets the
|
||||
// busy bit
|
||||
|
||||
// wait for busy to clear
|
||||
while (EP0CS & bmEPBUSY);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Handle our "Vendor Extension" commands on endpoint 0.
|
||||
* If we handle this one, return non-zero.
|
||||
*/
|
||||
unsigned char
|
||||
app_vendor_cmd(void)
|
||||
{
|
||||
WORD addr, len, bc;
|
||||
WORD i;
|
||||
|
||||
if (bRequestType == VRT_VENDOR_IN) {
|
||||
|
||||
// ///////////////////////////////
|
||||
// handle the IN requests
|
||||
// ///////////////////////////////
|
||||
|
||||
switch (bRequest) {
|
||||
|
||||
case VRQ_GET_STATUS:
|
||||
switch (wIndexL) {
|
||||
|
||||
case GS_RX_OVERRUN:
|
||||
EP0BUF[0] = GPIFIDLECS>>7;
|
||||
EP0BCH = 0;
|
||||
EP0BCL = 1;
|
||||
break;
|
||||
case GS_TX_UNDERRUN:
|
||||
EP0BUF[0] = GPIFIDLECS>>7;
|
||||
EP0BCH = 0;
|
||||
EP0BCL = 1;
|
||||
break;
|
||||
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
|
||||
case VRQ_DB_FX:
|
||||
DB_Addr = 0x01; //TPM: need to assert double byte
|
||||
I2C_Addr |= 0x01; //TPM: need to assert double byte
|
||||
// NOTE: This case falls through !
|
||||
case VRQ_RAM:
|
||||
case VRQ_EEPROM:
|
||||
addr = SETUPDAT[2]; // Get address and length
|
||||
addr |= SETUPDAT[3] << 8;
|
||||
len = SETUPDAT[6];
|
||||
len |= SETUPDAT[7] << 8;
|
||||
|
||||
while(len) // Move requested data through EP0IN
|
||||
{ // one packet at a time.
|
||||
|
||||
while(EP0CS & bmEPBUSY);
|
||||
|
||||
if(len < EP0BUFF_SIZE)
|
||||
bc = len;
|
||||
else
|
||||
bc = EP0BUFF_SIZE;
|
||||
|
||||
// Is this a RAM upload ?
|
||||
if(SETUPDAT[1] == VRQ_RAM)
|
||||
{
|
||||
for(i=0; i<bc; i++)
|
||||
*(EP0BUF+i) = *((BYTE xdata *)addr+i);
|
||||
}
|
||||
else
|
||||
{
|
||||
for(i=0; i<bc; i++)
|
||||
*(EP0BUF+i) = 0xcd;
|
||||
EEPROMRead(addr,(WORD)bc,(WORD)EP0BUF);
|
||||
}
|
||||
|
||||
EP0BCH = 0;
|
||||
EP0BCL = (BYTE)bc; // Arm endpoint with # bytes to transfer
|
||||
|
||||
addr += bc;
|
||||
len -= bc;
|
||||
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
else if (bRequestType == VRT_VENDOR_OUT) {
|
||||
|
||||
// ///////////////////////////////
|
||||
// handle the OUT requests
|
||||
// ///////////////////////////////
|
||||
|
||||
switch (bRequest) {
|
||||
|
||||
/* Start/Stop transfer */
|
||||
case VRQ_XFER:
|
||||
|
||||
/* start transfer */
|
||||
if (wValueL) {
|
||||
setup_flowstate_common();
|
||||
SYNCDELAY;
|
||||
GPIFABORT =0xff; SYNCDELAY;
|
||||
|
||||
GPIFTRIG = 0; SYNCDELAY;
|
||||
|
||||
setup_flowstate_read(); SYNCDELAY;
|
||||
/* Stop transfer */
|
||||
/* Zero out FIFO */
|
||||
FIFORESET = bmNAKALL;SYNCDELAY;
|
||||
FIFORESET = 2;SYNCDELAY;
|
||||
FIFORESET = 6;SYNCDELAY;
|
||||
FIFORESET = 0;SYNCDELAY;
|
||||
|
||||
/* Start transfer */
|
||||
GPIFTRIG = bmGPIF_EP6_START | bmGPIF_READ; SYNCDELAY;
|
||||
guardCnt = GUARD;
|
||||
}
|
||||
|
||||
/* stop transfer */
|
||||
else {
|
||||
GPIFTRIG = 0; SYNCDELAY;
|
||||
GPIFABORT =0xff; SYNCDELAY;
|
||||
|
||||
/* Clear fifo */
|
||||
FIFORESET = bmNAKALL;SYNCDELAY;
|
||||
FIFORESET = 2;SYNCDELAY;
|
||||
FIFORESET = 6;SYNCDELAY;
|
||||
FIFORESET = 0;SYNCDELAY;
|
||||
guardCnt = 0;
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case VRQ_DB_FX:
|
||||
DB_Addr = 0x01; //TPM: need to assert double byte
|
||||
I2C_Addr |= 0x01; //TPM: need to assert double byte
|
||||
// NOTE: This case falls through !
|
||||
case VRQ_RAM:
|
||||
case VRQ_EEPROM:
|
||||
addr = SETUPDAT[2]; // Get address and length
|
||||
addr |= SETUPDAT[3] << 8;
|
||||
len = SETUPDAT[6];
|
||||
len |= SETUPDAT[7] << 8;
|
||||
|
||||
// calculate the page size if we haven't already.
|
||||
// THIS IS A DESTRUCTIVE CALL - WILL ERASE THE EEPROM
|
||||
if (!EE_Page_Size)
|
||||
EE_Page_Size = EEPROMGetPageSize(); // Initialize EEPROM variables
|
||||
|
||||
while(len) // Move new data through EP0OUT
|
||||
{ // one packet at a time.
|
||||
// Arm endpoint - do it here to clear (after sud avail)
|
||||
EP0BCH = 0;
|
||||
EP0BCL = 0; // Clear bytecount to allow new data in; also stops NAKing
|
||||
|
||||
while(EP0CS & bmEPBUSY);
|
||||
|
||||
bc = EP0BCL; // Get the new bytecount
|
||||
|
||||
// Is this a RAM download ?
|
||||
if(SETUPDAT[1] == VRQ_RAM)
|
||||
{
|
||||
for(i=0; i<bc; i++)
|
||||
*((BYTE xdata *)addr+i) = *(EP0BUF+i);
|
||||
}
|
||||
else
|
||||
{
|
||||
for (i = 0; i < bc; )
|
||||
{
|
||||
// This write is normally one page long. Two special cases:
|
||||
// Starting from a non-page aligned address (addr & (EE_Page_Size - 1)) != 0
|
||||
// Less than a page left
|
||||
BYTE pageSize = EE_Page_Size;
|
||||
|
||||
if (EE_Page_Size != 1)
|
||||
{
|
||||
if (((addr+i) & (EE_Page_Size - 1)) != 0)
|
||||
pageSize = EE_Page_Size - ((addr+i) & (EE_Page_Size - 1));
|
||||
if (bc-i < pageSize)
|
||||
pageSize = bc-i;
|
||||
}
|
||||
|
||||
EEPROMWritePage(addr+i, EP0BUF+i, pageSize);
|
||||
i+= pageSize;
|
||||
}
|
||||
}
|
||||
|
||||
addr += bc;
|
||||
len -= bc;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
return 0; // invalid bRequestType
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
void guardC(void) interrupt {
|
||||
if(guardCnt)
|
||||
guardTick = 1;
|
||||
clear_timer_irq();
|
||||
}
|
||||
|
||||
static void main_loop(void)
|
||||
{
|
||||
setup_flowstate_common();
|
||||
SYNCDELAY;
|
||||
|
||||
|
||||
while (1) {
|
||||
// We don't do much, GPIF is running on autopilot
|
||||
|
||||
if (_usb_got_SUDAV) {
|
||||
usb_handle_setup_packet();
|
||||
_usb_got_SUDAV = 0;
|
||||
}
|
||||
|
||||
//Javi: Disable capture filesize limitation
|
||||
/*
|
||||
if (guardTick && guardCnt) {
|
||||
guardTick = 0;
|
||||
|
||||
if(!(--guardCnt)) {
|
||||
GPIFTRIG = 0; SYNCDELAY;
|
||||
GPIFABORT =0xff; SYNCDELAY;
|
||||
FIFORESET = bmNAKALL;SYNCDELAY;
|
||||
FIFORESET = 2;SYNCDELAY;
|
||||
FIFORESET = 6;SYNCDELAY;
|
||||
FIFORESET = 0;SYNCDELAY;
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
void TD_Init(void) // Called once at startup
|
||||
{
|
||||
//Rwuen = TRUE; // Enable remote-wakeup
|
||||
// Set the page size to 0, so we know to calculate it on an EEPROM write
|
||||
EE_Page_Size = 0;
|
||||
|
||||
// Determine I2C boot eeprom device address; addr = 0x0 for 8 bit addr eeproms (24LC00)
|
||||
I2C_Addr = SERIAL_ADDR | ((I2CS & 0x10) >> 4); // addr=0x01 for 16 bit addr eeprom (LC65)
|
||||
|
||||
// Indicate if it is a dual byte address part (BOOL)
|
||||
DB_Addr = (I2C_Addr & 0x01); // ID1 is 16 bit addr bit - set by rocker sw or jumper
|
||||
}
|
||||
114
firmware/GN3S_v2/src/gn3s_se4120.c
Normal file
114
firmware/GN3S_v2/src/gn3s_se4120.c
Normal file
@@ -0,0 +1,114 @@
|
||||
/*
|
||||
* Code from: USRP - Universal Software Radio Peripheral (GNU Radio)
|
||||
*
|
||||
* Initial modifications by:
|
||||
*
|
||||
* Stephan Esterhuizen, Aerospace Engineering Sciences
|
||||
* University of Colorado at Boulder
|
||||
* Boulder CO, USA
|
||||
*
|
||||
* Further modifications for use with the SiGe USB module to accompany
|
||||
* the textbook: "A Software-Defined GPS and Galileo Receiver: A
|
||||
* Single-Frequency Approach" by Kai Borre, Dennis Akos, et.al. by:
|
||||
*
|
||||
* Marcus Junered, GNSS Research Group
|
||||
* Lulea University of Technology
|
||||
* Lulea, Sweden
|
||||
* junered@ltu.se
|
||||
*
|
||||
*Futher modified for usage with a new frontend PCB
|
||||
* by Oscar Isoz GNSS Research Group
|
||||
* Lulea University of Technology
|
||||
* Lulea, Sweden
|
||||
* ---------------------------------------------------------------------
|
||||
*
|
||||
* GN3S - GNSS IF Streamer for Windows
|
||||
* Copyright (C) 2006 Marcus Junered
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#include "gn3s_se4110.h"
|
||||
|
||||
static unsigned short idx = 0;
|
||||
|
||||
|
||||
char init_se4110(void)
|
||||
{
|
||||
|
||||
/* D1,D5-D7 are inputs */
|
||||
IOD = 0xff;
|
||||
OED = 0xff;
|
||||
// OED = 0x1D; // Set Port D as outputs, except ADC_DOUT
|
||||
|
||||
/* Set all "config" ports */
|
||||
A0 = 1;
|
||||
A1 = 0;
|
||||
A2 = 0;
|
||||
A3 = 1;
|
||||
A4 = 0;
|
||||
A5 = 0;
|
||||
A7 = 1;
|
||||
|
||||
OEA = 0xBF; // Set Port A as output
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
short fifo_status() {
|
||||
return idx;
|
||||
}
|
||||
|
||||
|
||||
|
||||
char program_3w(void)
|
||||
{
|
||||
char i;
|
||||
char by0, by1;
|
||||
by0 =0x18;
|
||||
by1 =0xA4;
|
||||
|
||||
OEA = 0xFF;
|
||||
|
||||
A3 = 0;
|
||||
|
||||
A0 = 0;
|
||||
|
||||
for (i=7; i>=0; i--) {
|
||||
A1 = (by1 >> i) & 0x1;
|
||||
A2 = 1;
|
||||
A2 = 0;
|
||||
}
|
||||
|
||||
|
||||
/* Latch Enable */
|
||||
A0 = 1;
|
||||
A0 = 0;
|
||||
|
||||
for (i=7; i>=0; i--) {
|
||||
A1 = (by0 >> i) & 0x1;
|
||||
A2 = 1;
|
||||
A2 = 0;
|
||||
}
|
||||
|
||||
/* Latch Enable */
|
||||
A0 = 1;
|
||||
|
||||
OEA = 0xB9;
|
||||
|
||||
return 0;
|
||||
}
|
||||
292
firmware/GN3S_v2/src/gpif.c
Normal file
292
firmware/GN3S_v2/src/gpif.c
Normal file
@@ -0,0 +1,292 @@
|
||||
// This program configures the General Programmable Interface (GPIF) for FX2.
|
||||
// Please do not modify sections of text which are marked as "DO NOT EDIT ...".
|
||||
//
|
||||
// DO NOT EDIT ...
|
||||
// GPIF Initialization
|
||||
// Interface Timing Async
|
||||
// Internal Ready Init IntRdy=1
|
||||
// CTL Out Tristate-able Binary
|
||||
// SingleWrite WF Select 1
|
||||
// SingleRead WF Select 0
|
||||
// FifoWrite WF Select 3
|
||||
// FifoRead WF Select 2
|
||||
// Data Bus Idle Drive Tristate
|
||||
// END DO NOT EDIT
|
||||
|
||||
// DO NOT EDIT ...
|
||||
// GPIF Wave Names
|
||||
// Wave 0 = Single R
|
||||
// Wave 1 = Single W
|
||||
// Wave 2 = FIFO Rea
|
||||
// Wave 3 = FIFO Wri
|
||||
|
||||
// GPIF Ctrl Outputs Level
|
||||
// CTL 0 = BOGUS CMOS
|
||||
// CTL 1 = CTL1 CMOS
|
||||
// CTL 2 = CTL2 CMOS
|
||||
// CTL 3 = CTL3 CMOS
|
||||
// CTL 4 = CTL4 CMOS
|
||||
// CTL 5 = CTL5 CMOS
|
||||
|
||||
// GPIF Rdy Inputs
|
||||
// RDY0 = ADC_CLK
|
||||
// RDY1 = RDY1
|
||||
// RDY2 = RDY2
|
||||
// RDY3 = RDY3
|
||||
// RDY4 = RDY4
|
||||
// RDY5 = TCXpire
|
||||
// FIFOFlag = FIFOFlag
|
||||
// IntReady = IntReady
|
||||
// END DO NOT EDIT
|
||||
// DO NOT EDIT ...
|
||||
//
|
||||
// GPIF Waveform 0: Single R
|
||||
//
|
||||
// Interval 0 1 2 3 4 5 6 Idle (7)
|
||||
// _________ _________ _________ _________ _________ _________ _________ _________
|
||||
//
|
||||
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
|
||||
// DataMode NO Data NO Data NO Data NO Data NO Data NO Data NO Data
|
||||
// NextData SameData SameData SameData SameData SameData SameData SameData
|
||||
// Int Trig No Int No Int No Int No Int No Int No Int No Int
|
||||
// IF/Wait Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
|
||||
// Term A
|
||||
// LFunc
|
||||
// Term B
|
||||
// Branch1
|
||||
// Branch0
|
||||
// Re-Exec
|
||||
// Sngl/CRC Default Default Default Default Default Default Default
|
||||
// BOGUS 0 0 0 0 0 0 0 0
|
||||
// CTL1 0 0 0 0 0 0 0 0
|
||||
// CTL2 0 0 0 0 0 0 0 0
|
||||
// CTL3 0 0 0 0 0 0 0 0
|
||||
// CTL4 0 0 0 0 0 0 0 0
|
||||
// CTL5 0 0 0 0 0 0 0 0
|
||||
//
|
||||
// END DO NOT EDIT
|
||||
// DO NOT EDIT ...
|
||||
//
|
||||
// GPIF Waveform 1: Single W
|
||||
//
|
||||
// Interval 0 1 2 3 4 5 6 Idle (7)
|
||||
// _________ _________ _________ _________ _________ _________ _________ _________
|
||||
//
|
||||
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
|
||||
// DataMode NO Data NO Data NO Data NO Data NO Data NO Data NO Data
|
||||
// NextData SameData SameData SameData SameData SameData SameData SameData
|
||||
// Int Trig No Int No Int No Int No Int No Int No Int No Int
|
||||
// IF/Wait Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
|
||||
// Term A
|
||||
// LFunc
|
||||
// Term B
|
||||
// Branch1
|
||||
// Branch0
|
||||
// Re-Exec
|
||||
// Sngl/CRC Default Default Default Default Default Default Default
|
||||
// BOGUS 0 0 0 0 0 0 0 0
|
||||
// CTL1 0 0 0 0 0 0 0 0
|
||||
// CTL2 0 0 0 0 0 0 0 0
|
||||
// CTL3 0 0 0 0 0 0 0 0
|
||||
// CTL4 0 0 0 0 0 0 0 0
|
||||
// CTL5 0 0 0 0 0 0 0 0
|
||||
//
|
||||
// END DO NOT EDIT
|
||||
// DO NOT EDIT ...
|
||||
//
|
||||
// GPIF Waveform 2: FIFO Rea
|
||||
//
|
||||
// Interval 0 1 2 3 4 5 6 Idle (7)
|
||||
// _________ _________ _________ _________ _________ _________ _________ _________
|
||||
//
|
||||
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
|
||||
// DataMode Activate Activate Activate Activate Activate Activate Activate
|
||||
// NextData SameData SameData SameData SameData SameData SameData SameData
|
||||
// Int Trig No Int No Int No Int No Int No Int No Int No Int
|
||||
// IF/Wait IF Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
|
||||
// Term A FIFOFlag
|
||||
// LFunc AND
|
||||
// Term B FIFOFlag
|
||||
// Branch1 ThenIdle
|
||||
// Branch0 Else 0
|
||||
// Re-Exec No
|
||||
// Sngl/CRC Default Default Default Default Default Default Default
|
||||
// BOGUS 0 0 0 0 0 0 0 0
|
||||
// CTL1 0 0 0 0 0 0 0 0
|
||||
// CTL2 0 0 0 0 0 0 0 0
|
||||
// CTL3 0 0 0 0 0 0 0 0
|
||||
// CTL4 0 0 0 0 0 0 0 0
|
||||
// CTL5 0 0 0 0 0 0 0 0
|
||||
//
|
||||
// END DO NOT EDIT
|
||||
// DO NOT EDIT ...
|
||||
//
|
||||
// GPIF Waveform 3: FIFO Wri
|
||||
//
|
||||
// Interval 0 1 2 3 4 5 6 Idle (7)
|
||||
// _________ _________ _________ _________ _________ _________ _________ _________
|
||||
//
|
||||
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
|
||||
// DataMode Activate Activate Activate Activate Activate Activate Activate
|
||||
// NextData SameData SameData SameData SameData SameData SameData SameData
|
||||
// Int Trig No Int No Int No Int No Int No Int No Int No Int
|
||||
// IF/Wait IF Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
|
||||
// Term A FIFOFlag
|
||||
// LFunc AND
|
||||
// Term B FIFOFlag
|
||||
// Branch1 ThenIdle
|
||||
// Branch0 Else 0
|
||||
// Re-Exec No
|
||||
// Sngl/CRC Default Default Default Default Default Default Default
|
||||
// BOGUS 0 0 0 0 0 0 0 0
|
||||
// CTL1 0 0 0 0 0 0 0 0
|
||||
// CTL2 0 0 0 0 0 0 0 0
|
||||
// CTL3 0 0 0 0 0 0 0 0
|
||||
// CTL4 0 0 0 0 0 0 0 0
|
||||
// CTL5 0 0 0 0 0 0 0 0
|
||||
//
|
||||
// END DO NOT EDIT
|
||||
|
||||
// GPIF Program Code
|
||||
|
||||
// DO NOT EDIT ...
|
||||
#include "fx2.h"
|
||||
#include "fx2regs.h"
|
||||
#include "fx2sdly.h" // SYNCDELAY macro
|
||||
// END DO NOT EDIT
|
||||
|
||||
// DO NOT EDIT ...
|
||||
const char xdata WaveData[128] =
|
||||
{
|
||||
// Wave 0
|
||||
/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
|
||||
/* Opcode*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* Output*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
|
||||
// Wave 1
|
||||
/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
|
||||
/* Opcode*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* Output*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
|
||||
// Wave 2
|
||||
/* LenBr */ 0x38, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
|
||||
/* Opcode*/ 0x03, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00,
|
||||
/* Output*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* LFun */ 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
|
||||
// Wave 3
|
||||
/* LenBr */ 0x38, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
|
||||
/* Opcode*/ 0x03, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00,
|
||||
/* Output*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* LFun */ 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
|
||||
};
|
||||
// END DO NOT EDIT
|
||||
|
||||
// DO NOT EDIT ...
|
||||
const char xdata FlowStates[36] =
|
||||
{
|
||||
/* Wave 0 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
/* Wave 1 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
/* Wave 2 FlowStates */ 0x80,0xED,0x00,0x00,0x00,0x00,0x03,0x02,0x00,
|
||||
/* Wave 3 FlowStates */ 0x80,0xEE,0x00,0x00,0x00,0x00,0x03,0x02,0x00,
|
||||
};
|
||||
// END DO NOT EDIT
|
||||
|
||||
// DO NOT EDIT ...
|
||||
const char xdata InitData[7] =
|
||||
{
|
||||
/* Regs */ 0xA0,0x00,0x00,0x00,0xAE,0x4E,0x00
|
||||
};
|
||||
// END DO NOT EDIT
|
||||
|
||||
// TO DO: You may add additional code below.
|
||||
|
||||
void GpifInit( void )
|
||||
{
|
||||
BYTE i;
|
||||
|
||||
// Registers which require a synchronization delay, see section 15.14
|
||||
// FIFORESET FIFOPINPOLAR
|
||||
// INPKTEND OUTPKTEND
|
||||
// EPxBCH:L REVCTL
|
||||
// GPIFTCB3 GPIFTCB2
|
||||
// GPIFTCB1 GPIFTCB0
|
||||
// EPxFIFOPFH:L EPxAUTOINLENH:L
|
||||
// EPxFIFOCFG EPxGPIFFLGSEL
|
||||
// PINFLAGSxx EPxFIFOIRQ
|
||||
// EPxFIFOIE GPIFIRQ
|
||||
// GPIFIE GPIFADRH:L
|
||||
// UDMACRCH:L EPxGPIFTRIG
|
||||
// GPIFTRIG
|
||||
|
||||
// Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
|
||||
// ...these have been replaced by GPIFTC[B3:B0] registers
|
||||
|
||||
// 8051 doesn't have access to waveform memories 'til
|
||||
// the part is in GPIF mode.
|
||||
|
||||
IFCONFIG = 0xAE;
|
||||
// IFCLKSRC=1 , FIFOs executes on internal clk source
|
||||
// xMHz=1 , 48MHz internal clk rate
|
||||
// IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz
|
||||
// IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
|
||||
// ASYNC=1 , master samples asynchronous
|
||||
// GSTATE=1 , Drive GPIF states out on PORTE[2:0], debug WF
|
||||
// IFCFG[1:0]=10, FX2 in GPIF master mode
|
||||
|
||||
GPIFABORT = 0xFF; // abort any waveforms pending
|
||||
|
||||
GPIFREADYCFG = InitData[ 0 ];
|
||||
GPIFCTLCFG = InitData[ 1 ];
|
||||
GPIFIDLECS = InitData[ 2 ];
|
||||
GPIFIDLECTL = InitData[ 3 ];
|
||||
GPIFWFSELECT = InitData[ 5 ];
|
||||
GPIFREADYSTAT = InitData[ 6 ];
|
||||
|
||||
// use dual autopointer feature...
|
||||
AUTOPTRSETUP = 0x07; // inc both pointers,
|
||||
// ...warning: this introduces pdata hole(s)
|
||||
// ...at E67B (XAUTODAT1) and E67C (XAUTODAT2)
|
||||
|
||||
// source
|
||||
AUTOPTRH1 = MSB( &WaveData );
|
||||
AUTOPTRL1 = LSB( &WaveData );
|
||||
|
||||
// destination
|
||||
AUTOPTRH2 = 0xE4;
|
||||
AUTOPTRL2 = 0x00;
|
||||
|
||||
// transfer
|
||||
for ( i = 0x00; i < 128; i++ )
|
||||
{
|
||||
EXTAUTODAT2 = EXTAUTODAT1;
|
||||
}
|
||||
|
||||
// Configure GPIF Address pins, output initial value,
|
||||
PORTCCFG = 0xFF; // [7:0] as alt. func. GPIFADR[7:0]
|
||||
OEC = 0xFF; // and as outputs
|
||||
PORTECFG |= 0x80; // [8] as alt. func. GPIFADR[8]
|
||||
OEE |= 0x80; // and as output
|
||||
|
||||
// ...OR... tri-state GPIFADR[8:0] pins
|
||||
// PORTCCFG = 0x00; // [7:0] as port I/O
|
||||
// OEC = 0x00; // and as inputs
|
||||
// PORTECFG &= 0x7F; // [8] as port I/O
|
||||
// OEE &= 0x7F; // and as input
|
||||
|
||||
// GPIF address pins update when GPIFADRH/L written
|
||||
SYNCDELAY; //
|
||||
GPIFADRH = 0x00; // bits[7:1] always 0
|
||||
SYNCDELAY; //
|
||||
GPIFADRL = 0x00; // point to PERIPHERAL address 0x0000
|
||||
|
||||
// Configure GPIF FlowStates registers for Wave 0 of WaveData
|
||||
FLOWSTATE = FlowStates[ 0 ];
|
||||
FLOWLOGIC = FlowStates[ 1 ];
|
||||
FLOWEQ0CTL = FlowStates[ 2 ];
|
||||
FLOWEQ1CTL = FlowStates[ 3 ];
|
||||
FLOWHOLDOFF = FlowStates[ 4 ];
|
||||
FLOWSTB = FlowStates[ 5 ];
|
||||
FLOWSTBEDGE = FlowStates[ 6 ];
|
||||
FLOWSTBHPERIOD = FlowStates[ 7 ];
|
||||
}
|
||||
|
||||
BIN
firmware/GN3S_v2/src/gpif.gpf
Normal file
BIN
firmware/GN3S_v2/src/gpif.gpf
Normal file
Binary file not shown.
60
firmware/GN3S_v2/src/init_gpif.c
Normal file
60
firmware/GN3S_v2/src/init_gpif.c
Normal file
@@ -0,0 +1,60 @@
|
||||
/*
|
||||
* USRP - Universal Software Radio Peripheral
|
||||
*
|
||||
* Copyright (C) 2003 Free Software Foundation, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include "usrp_common.h"
|
||||
|
||||
// These are the tables generated by the Cypress GPIF Designer
|
||||
|
||||
extern const char WaveData[128];
|
||||
extern const char FlowStates[36];
|
||||
extern const char InitData[7];
|
||||
|
||||
// The tool is kind of screwed up, in that it doesn't configure some
|
||||
// of the ports correctly. We just use their tables and handle the
|
||||
// initialization ourselves. They also declare that their static
|
||||
// initialized data is in xdata, which screws us too.
|
||||
|
||||
void
|
||||
init_gpif(void)
|
||||
{
|
||||
// we've already setup IFCONFIG before calling this...
|
||||
|
||||
GPIFABORT = 0xFF; // abort any waveforms pending
|
||||
SYNCDELAY;
|
||||
|
||||
GPIFREADYCFG = InitData[0];
|
||||
GPIFCTLCFG = InitData[1];
|
||||
GPIFIDLECS = InitData[2];
|
||||
GPIFIDLECTL = InitData[3];
|
||||
// Hmmm, what's InitData[ 4 ] ...
|
||||
GPIFWFSELECT = InitData[5];
|
||||
// GPIFREADYSTAT = InitData[ 6 ]; // I think this register is read
|
||||
// only...
|
||||
|
||||
{
|
||||
BYTE i;
|
||||
|
||||
for (i = 0; i < 128; i++) {
|
||||
GPIF_WAVE_DATA[i] = WaveData[i];
|
||||
}
|
||||
}
|
||||
|
||||
FLOWSTATE = 0; /* ensure it's off */
|
||||
}
|
||||
2
firmware/GN3S_v2/src/readme.txt
Normal file
2
firmware/GN3S_v2/src/readme.txt
Normal file
@@ -0,0 +1,2 @@
|
||||
|
||||
- please note that modifying/enabling firmware can result in an inoperable board, proceed with caution
|
||||
3004
firmware/GN3S_v2/src/tags
Normal file
3004
firmware/GN3S_v2/src/tags
Normal file
File diff suppressed because it is too large
Load Diff
422
firmware/GN3S_v2/src/usb_descriptors.a51
Normal file
422
firmware/GN3S_v2/src/usb_descriptors.a51
Normal file
@@ -0,0 +1,422 @@
|
||||
;;;
|
||||
;;; Code from: USRP - Universal Software Radio Peripheral (GNU Radio)
|
||||
;;;
|
||||
;;; Initial modifications by:
|
||||
;;;
|
||||
;;; Stephan Esterhuizen, Aerospace Engineering Sciences
|
||||
;;; University of Colorado at Boulder
|
||||
;;; Boulder CO, USA
|
||||
;;;
|
||||
;;; Further modifications for use with the SiGe USB module to accompany
|
||||
;;; the textbook: "A Software-Defined GPS and Galileo Receiver: A
|
||||
;;; Single-Frequency Approach" by Kai Borre, Dennis Akos, et.al. by:
|
||||
;;;
|
||||
;;; Marcus Junered, GNSS Research Group
|
||||
;;; Lulea University of Technology
|
||||
;;; Lulea, Sweden
|
||||
;;; junered@ltu.se
|
||||
;;;
|
||||
;;; ---------------------------------------------------------------------
|
||||
;;;
|
||||
;;; GN3S - GNSS IF Streamer for Cypress FX2LP
|
||||
;;; Copyright (C) 2006 Marcus Junered
|
||||
;;;
|
||||
;;; This program is free software; you can redistribute it and/or modify
|
||||
;;; it under the terms of the GNU General Public License as published by
|
||||
;;; the Free Software Foundation; either version 2 of the License, or
|
||||
;;; (at your option) any later version.
|
||||
;;;
|
||||
;;; This program is distributed in the hope that it will be useful,
|
||||
;;; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
;;; GNU General Public License for more details.
|
||||
;;;
|
||||
;;; You should have received a copy of the GNU General Public License
|
||||
;;; along with this program; if not, write to the Free Software
|
||||
;;; Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
;;;
|
||||
|
||||
|
||||
;;; USB Descriptor table for the USRP
|
||||
;;;
|
||||
;;; We're a high-speed only device (480 Mb/sec) with 1 configuration
|
||||
;;; and 3 interfaces.
|
||||
;;;
|
||||
;;; interface 0: command and status (ep0 COMMAND)
|
||||
;;; interface 1: Transmit path (ep2 OUT BULK)
|
||||
;;; interface 2: Receive path (ep6 IN BULK)
|
||||
|
||||
.module usb_descriptors
|
||||
|
||||
;;VID_FREE = 0x1781 ; GN3S Project
|
||||
;;PID_USRP = 0x0B39 ; CU AAU SE4120L-EK3
|
||||
VID_FREE = 0x16C0 ; GN3S Modified driver Project
|
||||
PID_USRP = 0x072F ; CU AAU SE4120L-EK3
|
||||
;; We distinguish configured from unconfigured USRPs using the Device ID.
|
||||
;; If the MSB of the DID is 0, the device is unconfigured.
|
||||
;; The LSB of the DID is reserved for hardware revs.
|
||||
|
||||
DID_USRP1 = 0x0102 ; Device ID (bcd)
|
||||
|
||||
|
||||
DSCR_DEVICE = 1 ; Descriptor type: Device
|
||||
DSCR_CONFIG = 2 ; Descriptor type: Configuration
|
||||
DSCR_STRING = 3 ; Descriptor type: String
|
||||
DSCR_INTRFC = 4 ; Descriptor type: Interface
|
||||
DSCR_ENDPNT = 5 ; Descriptor type: Endpoint
|
||||
DSCR_DEVQUAL = 6 ; Descriptor type: Device Qualifier
|
||||
|
||||
DSCR_DEVICE_LEN = 18
|
||||
DSCR_CONFIG_LEN = 9
|
||||
DSCR_INTRFC_LEN = 9
|
||||
DSCR_ENDPNT_LEN = 7
|
||||
DSCR_DEVQUAL_LEN = 10
|
||||
|
||||
ET_CONTROL = 0 ; Endpoint type: Control
|
||||
ET_ISO = 1 ; Endpoint type: Isochronous
|
||||
ET_BULK = 2 ; Endpoint type: Bulk
|
||||
ET_INT = 3 ; Endpoint type: Interrupt
|
||||
|
||||
|
||||
;; configuration attributes
|
||||
bmSELF_POWERED = 1 << 6
|
||||
|
||||
;;; --------------------------------------------------------
|
||||
;;; external ram data
|
||||
;;;--------------------------------------------------------
|
||||
|
||||
.area USBDESCSEG (XDATA)
|
||||
|
||||
;;; ----------------------------------------------------------------
|
||||
;;; descriptors used when operating at high speed (480Mb/sec)
|
||||
;;; ----------------------------------------------------------------
|
||||
|
||||
.even ; descriptors must be 2-byte aligned for SUDPTR{H,L} to work
|
||||
|
||||
;; The .even directive isn't really honored by the linker. Bummer!
|
||||
;; (There's no way to specify an alignment requirement for a given area,
|
||||
;; hence when they're concatenated together, even doesn't work.)
|
||||
;;
|
||||
;; We work around this by telling the linker to put USBDESCSEG
|
||||
;; at 0xE000 absolute. This means that the maximimum length of this
|
||||
;; segment is 480 bytes, leaving room for the two hash slots
|
||||
;; at 0xE1EO to 0xE1FF.
|
||||
;;
|
||||
;; As of July 7, 2004, this segment is 326 bytes long
|
||||
|
||||
_high_speed_device_descr::
|
||||
.db DSCR_DEVICE_LEN
|
||||
.db DSCR_DEVICE
|
||||
.db <0x0200 ; Specification version (LSB)
|
||||
.db >0x0200 ; Specification version (MSB)
|
||||
.db 0xff ; device class (vendor specific)
|
||||
.db 0xff ; device subclass (vendor specific)
|
||||
.db 0xff ; device protocol (vendor specific)
|
||||
.db 64 ; bMaxPacketSize0 for endpoint 0
|
||||
.db <VID_FREE ; idVendor
|
||||
.db >VID_FREE ; idVendor
|
||||
.db <PID_USRP ; idProduct
|
||||
.db >PID_USRP ; idProduct
|
||||
.db <DID_USRP1 ; bcdDevice
|
||||
.db >DID_USRP1 ; bcdDevice
|
||||
.db SI_VENDOR ; iManufacturer (string index)
|
||||
.db SI_PRODUCT ; iProduct (string index)
|
||||
.db SI_SERIAL ; iSerial number (string index)
|
||||
.db 1 ; bNumConfigurations
|
||||
|
||||
;;; describes the other speed (12Mb/sec)
|
||||
.even
|
||||
_high_speed_devqual_descr::
|
||||
.db DSCR_DEVQUAL_LEN
|
||||
.db DSCR_DEVQUAL
|
||||
.db <0x0200 ; bcdUSB (LSB)
|
||||
.db >0x0200 ; bcdUSB (MSB)
|
||||
.db 0xff ; bDeviceClass
|
||||
.db 0xff ; bDeviceSubClass
|
||||
.db 0xff ; bDeviceProtocol
|
||||
.db 64 ; bMaxPacketSize0
|
||||
.db 1 ; bNumConfigurations (one config at 12Mb/sec)
|
||||
.db 0 ; bReserved
|
||||
|
||||
.even
|
||||
_high_speed_config_descr::
|
||||
.db DSCR_CONFIG_LEN
|
||||
.db DSCR_CONFIG
|
||||
.db <(_high_speed_config_descr_end - _high_speed_config_descr) ; LSB
|
||||
.db >(_high_speed_config_descr_end - _high_speed_config_descr) ; MSB
|
||||
.db 3 ; bNumInterfaces
|
||||
.db 1 ; bConfigurationValue
|
||||
.db 0 ; iConfiguration
|
||||
.db 0x80 | bmSELF_POWERED ; bmAttributes
|
||||
.db 0 ; bMaxPower
|
||||
|
||||
;; interface descriptor 0 (command & status, ep0 COMMAND)
|
||||
|
||||
.db DSCR_INTRFC_LEN
|
||||
.db DSCR_INTRFC
|
||||
.db 0 ; bInterfaceNumber (zero based)
|
||||
.db 0 ; bAlternateSetting
|
||||
.db 0 ; bNumEndpoints
|
||||
.db 0xff ; bInterfaceClass (vendor specific)
|
||||
.db 0xff ; bInterfaceSubClass (vendor specific)
|
||||
.db 0xff ; bInterfaceProtocol (vendor specific)
|
||||
.db SI_COMMAND_AND_STATUS ; iInterface (description)
|
||||
|
||||
;; interface descriptor 1 (transmit path, ep2 OUT BULK)
|
||||
|
||||
.db DSCR_INTRFC_LEN
|
||||
.db DSCR_INTRFC
|
||||
.db 1 ; bInterfaceNumber (zero based)
|
||||
.db 0 ; bAlternateSetting
|
||||
.db 1 ; bNumEndpoints
|
||||
.db 0xff ; bInterfaceClass (vendor specific)
|
||||
.db 0xff ; bInterfaceSubClass (vendor specific)
|
||||
.db 0xff ; bInterfaceProtocol (vendor specific)
|
||||
.db SI_TX_PATH ; iInterface (description)
|
||||
|
||||
;; interface 1's end point
|
||||
|
||||
.db DSCR_ENDPNT_LEN
|
||||
.db DSCR_ENDPNT
|
||||
.db 0x02 ; bEndpointAddress (ep 2 OUT)
|
||||
.db ET_BULK ; bmAttributes
|
||||
.db <512 ; wMaxPacketSize (LSB)
|
||||
.db >512 ; wMaxPacketSize (MSB)
|
||||
.db 0 ; bInterval (iso only)
|
||||
|
||||
;; interface descriptor 2 (receive path, ep6 IN BULK)
|
||||
|
||||
.db DSCR_INTRFC_LEN
|
||||
.db DSCR_INTRFC
|
||||
.db 2 ; bInterfaceNumber (zero based)
|
||||
.db 0 ; bAlternateSetting
|
||||
.db 1 ; bNumEndpoints
|
||||
.db 0xff ; bInterfaceClass (vendor specific)
|
||||
.db 0xff ; bInterfaceSubClass (vendor specific)
|
||||
.db 0xff ; bInterfaceProtocol (vendor specific)
|
||||
.db SI_RX_PATH ; iInterface (description)
|
||||
|
||||
;; interface 2's end point
|
||||
|
||||
.db DSCR_ENDPNT_LEN
|
||||
.db DSCR_ENDPNT
|
||||
.db 0x86 ; bEndpointAddress (ep 6 IN)
|
||||
.db ET_BULK ; bmAttributes
|
||||
.db <512 ; wMaxPacketSize (LSB)
|
||||
.db >512 ; wMaxPacketSize (MSB)
|
||||
.db 0 ; bInterval (iso only)
|
||||
|
||||
_high_speed_config_descr_end:
|
||||
|
||||
;;; ----------------------------------------------------------------
|
||||
;;; descriptors used when operating at full speed (12Mb/sec)
|
||||
;;; ----------------------------------------------------------------
|
||||
|
||||
.even
|
||||
_full_speed_device_descr::
|
||||
.db DSCR_DEVICE_LEN
|
||||
.db DSCR_DEVICE
|
||||
.db <0x0200 ; Specification version (LSB)
|
||||
.db >0x0200 ; Specification version (MSB)
|
||||
.db 0xff ; device class (vendor specific)
|
||||
.db 0xff ; device subclass (vendor specific)
|
||||
.db 0xff ; device protocol (vendor specific)
|
||||
.db 64 ; bMaxPacketSize0 for endpoint 0
|
||||
.db <VID_FREE ; idVendor
|
||||
.db >VID_FREE ; idVendor
|
||||
.db <PID_USRP ; idProduct
|
||||
.db >PID_USRP ; idProduct
|
||||
.db <DID_USRP1 ; bcdDevice
|
||||
.db >DID_USRP1 ; bcdDevice
|
||||
.db SI_VENDOR ; iManufacturer (string index)
|
||||
.db SI_PRODUCT ; iProduct (string index)
|
||||
.db SI_NONE ; iSerial number (None)
|
||||
.db 1 ; bNumConfigurations
|
||||
|
||||
|
||||
;;; describes the other speed (480Mb/sec)
|
||||
.even
|
||||
_full_speed_devqual_descr::
|
||||
.db DSCR_DEVQUAL_LEN
|
||||
.db DSCR_DEVQUAL
|
||||
.db <0x0200 ; bcdUSB
|
||||
.db >0x0200 ; bcdUSB
|
||||
.db 0xff ; bDeviceClass
|
||||
.db 0xff ; bDeviceSubClass
|
||||
.db 0xff ; bDeviceProtocol
|
||||
.db 64 ; bMaxPacketSize0
|
||||
.db 1 ; bNumConfigurations (one config at 480Mb/sec)
|
||||
.db 0 ; bReserved
|
||||
|
||||
.even
|
||||
_full_speed_config_descr::
|
||||
.db DSCR_CONFIG_LEN
|
||||
.db DSCR_CONFIG
|
||||
.db <(_full_speed_config_descr_end - _full_speed_config_descr) ; LSB
|
||||
.db >(_full_speed_config_descr_end - _full_speed_config_descr) ; MSB
|
||||
.db 1 ; bNumInterfaces
|
||||
.db 1 ; bConfigurationValue
|
||||
.db 0 ; iConfiguration
|
||||
.db 0x80 | bmSELF_POWERED ; bmAttributes
|
||||
.db 0 ; bMaxPower
|
||||
|
||||
;; interface descriptor 0 (command & status, ep0 COMMAND)
|
||||
|
||||
.db DSCR_INTRFC_LEN
|
||||
.db DSCR_INTRFC
|
||||
.db 0 ; bInterfaceNumber (zero based)
|
||||
.db 0 ; bAlternateSetting
|
||||
.db 0 ; bNumEndpoints
|
||||
.db 0xff ; bInterfaceClass (vendor specific)
|
||||
.db 0xff ; bInterfaceSubClass (vendor specific)
|
||||
.db 0xff ; bInterfaceProtocol (vendor specific)
|
||||
.db SI_COMMAND_AND_STATUS ; iInterface (description)
|
||||
|
||||
_full_speed_config_descr_end:
|
||||
|
||||
;;; ----------------------------------------------------------------
|
||||
;;; string descriptors
|
||||
;;; ----------------------------------------------------------------
|
||||
|
||||
_nstring_descriptors::
|
||||
.db (_string_descriptors_end - _string_descriptors) / 2
|
||||
|
||||
_string_descriptors::
|
||||
.db <str0, >str0
|
||||
.db <str1, >str1
|
||||
.db <str2, >str2
|
||||
.db <str3, >str3
|
||||
.db <str4, >str4
|
||||
.db <str5, >str5
|
||||
.db <str6, >str6
|
||||
_string_descriptors_end:
|
||||
|
||||
SI_NONE = 0
|
||||
;; str0 contains the language ID's.
|
||||
.even
|
||||
str0: .db str0_end - str0
|
||||
.db DSCR_STRING
|
||||
.db 0
|
||||
.db 0
|
||||
.db <0x0409 ; magic code for US English (LSB)
|
||||
.db >0x0409 ; magic code for US English (MSB)
|
||||
str0_end:
|
||||
|
||||
SI_VENDOR = 1
|
||||
.even
|
||||
str1: .db str1_end - str1
|
||||
.db DSCR_STRING
|
||||
.db 'G, 0 ; 16-bit unicode
|
||||
.db 'N, 0
|
||||
.db '3, 0
|
||||
.db 'S, 0
|
||||
.db ' , 0
|
||||
.db 'P, 0
|
||||
.db 'r, 0
|
||||
.db 'o, 0
|
||||
.db 'j, 0
|
||||
.db 'e, 0
|
||||
.db 'c, 0
|
||||
.db 't, 0
|
||||
str1_end:
|
||||
|
||||
SI_PRODUCT = 2
|
||||
.even
|
||||
str2: .db str2_end - str2
|
||||
.db DSCR_STRING
|
||||
.db 'C, 0
|
||||
.db 'U, 0
|
||||
.db ' , 0
|
||||
.db 'A, 0
|
||||
.db 'A, 0
|
||||
.db 'U, 0
|
||||
.db ' , 0
|
||||
.db 'S, 0
|
||||
.db 'i, 0
|
||||
.db 'G, 0
|
||||
.db 'e, 0
|
||||
.db ' , 0
|
||||
.db 'S, 0
|
||||
.db 'E, 0
|
||||
.db '4, 0
|
||||
.db '1, 0
|
||||
.db '1, 0
|
||||
.db '0, 0
|
||||
.db 'L, 0
|
||||
.db '-, 0
|
||||
.db 'E, 0
|
||||
.db 'K, 0
|
||||
.db '3, 0
|
||||
str2_end:
|
||||
|
||||
SI_COMMAND_AND_STATUS = 3
|
||||
.even
|
||||
str3: .db str3_end - str3
|
||||
.db DSCR_STRING
|
||||
.db 'C, 0
|
||||
.db 'o, 0
|
||||
.db 'm, 0
|
||||
.db 'm, 0
|
||||
.db 'a, 0
|
||||
.db 'n, 0
|
||||
.db 'd, 0
|
||||
.db ' , 0
|
||||
.db '&, 0
|
||||
.db ' , 0
|
||||
.db 'S, 0
|
||||
.db 't, 0
|
||||
.db 'a, 0
|
||||
.db 't, 0
|
||||
.db 'u, 0
|
||||
.db 's, 0
|
||||
str3_end:
|
||||
|
||||
SI_TX_PATH = 4
|
||||
.even
|
||||
str4: .db str4_end - str4
|
||||
.db DSCR_STRING
|
||||
.db 'T, 0
|
||||
.db 'r, 0
|
||||
.db 'a, 0
|
||||
.db 'n, 0
|
||||
.db 's, 0
|
||||
.db 'm, 0
|
||||
.db 'i, 0
|
||||
.db 't, 0
|
||||
.db ' , 0
|
||||
.db 'P, 0
|
||||
.db 'a, 0
|
||||
.db 't, 0
|
||||
.db 'h, 0
|
||||
str4_end:
|
||||
|
||||
SI_RX_PATH = 5
|
||||
.even
|
||||
str5: .db str5_end - str5
|
||||
.db DSCR_STRING
|
||||
.db 'R, 0
|
||||
.db 'e, 0
|
||||
.db 'c, 0
|
||||
.db 'e, 0
|
||||
.db 'i, 0
|
||||
.db 'v, 0
|
||||
.db 'e, 0
|
||||
.db ' , 0
|
||||
.db 'P, 0
|
||||
.db 'a, 0
|
||||
.db 't, 0
|
||||
.db 'h, 0
|
||||
str5_end:
|
||||
|
||||
SI_SERIAL = 6
|
||||
.even
|
||||
_serial_number_descriptor::
|
||||
str6: .db str6_end - str6
|
||||
.db DSCR_STRING
|
||||
.db '1, 0
|
||||
.db '0, 0
|
||||
.db '0, 0
|
||||
.db '0, 0
|
||||
.db '0, 0
|
||||
str6_end:
|
||||
|
||||
132
firmware/GN3S_v2/src/usrp_common.c
Normal file
132
firmware/GN3S_v2/src/usrp_common.c
Normal file
@@ -0,0 +1,132 @@
|
||||
/*
|
||||
* Code from: USRP - Universal Software Radio Peripheral (GNU Radio)
|
||||
*
|
||||
* Initial modifications by:
|
||||
*
|
||||
* Stephan Esterhuizen, Aerospace Engineering Sciences
|
||||
* University of Colorado at Boulder
|
||||
* Boulder CO, USA
|
||||
*
|
||||
* Further modifications for use with the SiGe USB module to accompany
|
||||
* the textbook: "A Software-Defined GPS and Galileo Receiver: A
|
||||
* Single-Frequency Approach" by Kai Borre, Dennis Akos, et.al. by:
|
||||
*
|
||||
* Marcus Junered, GNSS Research Group
|
||||
* Lulea University of Technology
|
||||
* Lulea, Sweden
|
||||
*
|
||||
* http://ccar.colorado.edu/gnss
|
||||
*
|
||||
* ---------------------------------------------------------------------
|
||||
*
|
||||
* GN3S - GNSS IF Streamer for Windows
|
||||
* Copyright (C) 2006 Marcus Junered
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#include "usrp_common.h"
|
||||
|
||||
|
||||
/* If wordwide is defined, will grab 16 bits, otherwise only
|
||||
* bits 7-0 is used */
|
||||
#undef wordwide
|
||||
|
||||
void init_usrp(void)
|
||||
{
|
||||
CPUCS = bmCLKSPD1; // CPU runs @ 48 MHz
|
||||
CKCON = 0; // MOVX takes 2 cycles
|
||||
|
||||
IFCONFIG = bmIFGPIF;
|
||||
//IFCONFIG = bmIFGPIF|bmIFCLKSRC|bmIFCLKOE;//|bm3048MHZ;
|
||||
//IFCONFIG = bmIFGPIF|bmIFCLKSRC;
|
||||
SYNCDELAY;
|
||||
|
||||
//REVCTL = bmDYN_OUT | bmENH_PKT; // highly recommended by docs
|
||||
//SYNCDELAY;
|
||||
|
||||
// configure end points
|
||||
|
||||
EP1OUTCFG = bmVALID | bmBULK;
|
||||
SYNCDELAY;
|
||||
EP1INCFG = bmVALID | bmBULK | bmIN;
|
||||
SYNCDELAY;
|
||||
|
||||
// 512 quad bulk OUT
|
||||
//EP2CFG = bmVALID | bmBULK ; //| bmQUADBUF;
|
||||
EP2CFG = 0;
|
||||
SYNCDELAY;
|
||||
// disabled
|
||||
EP4CFG = 0;
|
||||
SYNCDELAY;
|
||||
// 512 quad bulk IN
|
||||
EP6CFG = bmVALID | bmBULK | bmQUADBUF | bmIN;
|
||||
SYNCDELAY;
|
||||
// disabled
|
||||
EP8CFG = 0;
|
||||
SYNCDELAY;
|
||||
|
||||
// reset FIFOs
|
||||
FIFORESET = bmNAKALL;
|
||||
SYNCDELAY;
|
||||
//FIFORESET = 2;
|
||||
//SYNCDELAY;
|
||||
// FIFORESET = 4; SYNCDELAY;
|
||||
FIFORESET = 6;
|
||||
SYNCDELAY;
|
||||
// FIFORESET = 8; SYNCDELAY;
|
||||
FIFORESET = 0;
|
||||
SYNCDELAY;
|
||||
|
||||
// configure end point FIFOs
|
||||
|
||||
// let core see 0 to 1 transistion of autoout bit
|
||||
|
||||
|
||||
#ifdef wordwide
|
||||
EP2FIFOCFG = 0x00;
|
||||
EP6FIFOCFG = bmZEROLENIN | bmAUTOIN | bmWORDWIDE;
|
||||
#else
|
||||
EP2FIFOCFG = 0x00;
|
||||
EP4FIFOCFG = 0x00;
|
||||
EP6FIFOCFG = bmZEROLENIN | bmAUTOIN;
|
||||
EP8FIFOCFG = 0x00;
|
||||
#endif
|
||||
|
||||
SYNCDELAY;
|
||||
|
||||
EP0BCH = 0;
|
||||
SYNCDELAY;
|
||||
|
||||
// arm EP1OUT so we can receive "out" packets (TRM pg 8-8)
|
||||
|
||||
EP1OUTBC = 0;
|
||||
SYNCDELAY;
|
||||
|
||||
//EP2GPIFFLGSEL = 0x01;
|
||||
//SYNCDELAY; // For EP2OUT, GPIF uses EF flag
|
||||
EP6GPIFFLGSEL = 0x02;
|
||||
SYNCDELAY; // For EP6IN, GPIF uses FF flag
|
||||
|
||||
/* waveform DONE when FF/EF flags get set */
|
||||
EP6GPIFPFSTOP=0x01; SYNCDELAY;
|
||||
//EP2GPIFPFSTOP=0x01; SYNCDELAY;
|
||||
|
||||
EP6AUTOINLENH = (512) >> 8;
|
||||
SYNCDELAY; // this is the length for high speed
|
||||
EP6AUTOINLENL = (512) & 0xff;
|
||||
SYNCDELAY;
|
||||
}
|
||||
206
firmware/GN3S_v2/src/usrp_gpif.c
Normal file
206
firmware/GN3S_v2/src/usrp_gpif.c
Normal file
@@ -0,0 +1,206 @@
|
||||
/*
|
||||
* Machine generated by "edit-gpif". Do not edit by hand.
|
||||
*/
|
||||
|
||||
// This program configures the General Programmable Interface (GPIF) for FX2.
|
||||
// Please do not modify sections of text which are marked as "DO NOT EDIT ...".
|
||||
//
|
||||
// DO NOT EDIT ...
|
||||
// GPIF Initialization
|
||||
// Interface Timing Async
|
||||
// Internal Ready Init IntRdy=1
|
||||
// CTL Out Tristate-able Binary
|
||||
// SingleWrite WF Select 1
|
||||
// SingleRead WF Select 0
|
||||
// FifoWrite WF Select 3
|
||||
// FifoRead WF Select 2
|
||||
// Data Bus Idle Drive Tristate
|
||||
// END DO NOT EDIT
|
||||
|
||||
// DO NOT EDIT ...
|
||||
// GPIF Wave Names
|
||||
// Wave 0 = Single R
|
||||
// Wave 1 = Single W
|
||||
// Wave 2 = FIFO Rea
|
||||
// Wave 3 = FIFO Wri
|
||||
|
||||
// GPIF Ctrl Outputs Level
|
||||
// CTL 0 = BOGUS CMOS
|
||||
// CTL 1 = CTL1 CMOS
|
||||
// CTL 2 = CTL2 CMOS
|
||||
// CTL 3 = CTL3 CMOS
|
||||
// CTL 4 = CTL4 CMOS
|
||||
// CTL 5 = CTL5 CMOS
|
||||
|
||||
// GPIF Rdy Inputs
|
||||
// RDY0 = ADC_CLK
|
||||
// RDY1 = RDY1
|
||||
// RDY2 = RDY2
|
||||
// RDY3 = RDY3
|
||||
// RDY4 = RDY4
|
||||
// RDY5 = TCXpire
|
||||
// FIFOFlag = FIFOFlag
|
||||
// IntReady = IntReady
|
||||
// END DO NOT EDIT
|
||||
// DO NOT EDIT ...
|
||||
//
|
||||
// GPIF Waveform 0: Single R
|
||||
//
|
||||
// Interval 0 1 2 3 4 5 6 Idle (7)
|
||||
// _________ _________ _________ _________ _________ _________ _________ _________
|
||||
//
|
||||
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
|
||||
// DataMode NO Data NO Data NO Data NO Data NO Data NO Data NO Data
|
||||
// NextData SameData SameData SameData SameData SameData SameData SameData
|
||||
// Int Trig No Int No Int No Int No Int No Int No Int No Int
|
||||
// IF/Wait Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
|
||||
// Term A
|
||||
// LFunc
|
||||
// Term B
|
||||
// Branch1
|
||||
// Branch0
|
||||
// Re-Exec
|
||||
// Sngl/CRC Default Default Default Default Default Default Default
|
||||
// BOGUS 0 0 0 0 0 0 0 0
|
||||
// CTL1 0 0 0 0 0 0 0 0
|
||||
// CTL2 0 0 0 0 0 0 0 0
|
||||
// CTL3 0 0 0 0 0 0 0 0
|
||||
// CTL4 0 0 0 0 0 0 0 0
|
||||
// CTL5 0 0 0 0 0 0 0 0
|
||||
//
|
||||
// END DO NOT EDIT
|
||||
// DO NOT EDIT ...
|
||||
//
|
||||
// GPIF Waveform 1: Single W
|
||||
//
|
||||
// Interval 0 1 2 3 4 5 6 Idle (7)
|
||||
// _________ _________ _________ _________ _________ _________ _________ _________
|
||||
//
|
||||
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
|
||||
// DataMode NO Data NO Data NO Data NO Data NO Data NO Data NO Data
|
||||
// NextData SameData SameData SameData SameData SameData SameData SameData
|
||||
// Int Trig No Int No Int No Int No Int No Int No Int No Int
|
||||
// IF/Wait Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
|
||||
// Term A
|
||||
// LFunc
|
||||
// Term B
|
||||
// Branch1
|
||||
// Branch0
|
||||
// Re-Exec
|
||||
// Sngl/CRC Default Default Default Default Default Default Default
|
||||
// BOGUS 0 0 0 0 0 0 0 0
|
||||
// CTL1 0 0 0 0 0 0 0 0
|
||||
// CTL2 0 0 0 0 0 0 0 0
|
||||
// CTL3 0 0 0 0 0 0 0 0
|
||||
// CTL4 0 0 0 0 0 0 0 0
|
||||
// CTL5 0 0 0 0 0 0 0 0
|
||||
//
|
||||
// END DO NOT EDIT
|
||||
// DO NOT EDIT ...
|
||||
//
|
||||
// GPIF Waveform 2: FIFO Rea
|
||||
//
|
||||
// Interval 0 1 2 3 4 5 6 Idle (7)
|
||||
// _________ _________ _________ _________ _________ _________ _________ _________
|
||||
//
|
||||
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
|
||||
// DataMode Activate Activate Activate Activate Activate Activate Activate
|
||||
// NextData SameData SameData SameData SameData SameData SameData SameData
|
||||
// Int Trig No Int No Int No Int No Int No Int No Int No Int
|
||||
// IF/Wait IF Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
|
||||
// Term A TCXpire
|
||||
// LFunc AND
|
||||
// Term B TCXpire
|
||||
// Branch1 ThenIdle
|
||||
// Branch0 Else 0
|
||||
// Re-Exec No
|
||||
// Sngl/CRC Default Default Default Default Default Default Default
|
||||
// BOGUS 0 0 0 0 0 0 0 0
|
||||
// CTL1 0 0 0 0 0 0 0 0
|
||||
// CTL2 0 0 0 0 0 0 0 0
|
||||
// CTL3 0 0 0 0 0 0 0 0
|
||||
// CTL4 0 0 0 0 0 0 0 0
|
||||
// CTL5 0 0 0 0 0 0 0 0
|
||||
//
|
||||
// END DO NOT EDIT
|
||||
// DO NOT EDIT ...
|
||||
//
|
||||
// GPIF Waveform 3: FIFO Wri
|
||||
//
|
||||
// Interval 0 1 2 3 4 5 6 Idle (7)
|
||||
// _________ _________ _________ _________ _________ _________ _________ _________
|
||||
//
|
||||
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
|
||||
// DataMode NO Data NO Data NO Data NO Data NO Data NO Data NO Data
|
||||
// NextData SameData SameData SameData SameData SameData SameData SameData
|
||||
// Int Trig No Int No Int No Int No Int No Int No Int No Int
|
||||
// IF/Wait Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
|
||||
// Term A
|
||||
// LFunc
|
||||
// Term B
|
||||
// Branch1
|
||||
// Branch0
|
||||
// Re-Exec
|
||||
// Sngl/CRC Default Default Default Default Default Default Default
|
||||
// BOGUS 0 0 0 0 0 0 0 0
|
||||
// CTL1 0 0 0 0 0 0 0 0
|
||||
// CTL2 0 0 0 0 0 0 0 0
|
||||
// CTL3 0 0 0 0 0 0 0 0
|
||||
// CTL4 0 0 0 0 0 0 0 0
|
||||
// CTL5 0 0 0 0 0 0 0 0
|
||||
//
|
||||
// END DO NOT EDIT
|
||||
|
||||
// GPIF Program Code
|
||||
|
||||
// DO NOT EDIT ...
|
||||
// #include "fx2.h"
|
||||
// #include "fx2regs.h"
|
||||
// #include "fx2sdly.h" // SYNCDELAY macro
|
||||
// END DO NOT EDIT
|
||||
|
||||
// DO NOT EDIT ...
|
||||
const char WaveData[128] =
|
||||
{
|
||||
// Wave 0
|
||||
/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
|
||||
/* Opcode*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* Output*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
|
||||
// Wave 1
|
||||
/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
|
||||
/* Opcode*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* Output*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
|
||||
// Wave 2
|
||||
/* LenBr */ 0x38, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
|
||||
/* Opcode*/ 0x03, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00,
|
||||
/* Output*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* LFun */ 0x2D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
|
||||
// Wave 3
|
||||
/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
|
||||
/* Opcode*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* Output*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
|
||||
};
|
||||
// END DO NOT EDIT
|
||||
|
||||
// DO NOT EDIT ...
|
||||
const char FlowStates[36] =
|
||||
{
|
||||
/* Wave 0 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
/* Wave 1 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
/* Wave 2 FlowStates */ 0x80,0x2D,0x00,0x00,0x00,0x00,0x03,0x02,0x00,
|
||||
/* Wave 3 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
};
|
||||
// END DO NOT EDIT
|
||||
|
||||
// DO NOT EDIT ...
|
||||
const char InitData[7] =
|
||||
{
|
||||
/* Regs */ 0xA0,0x00,0x00,0x00,0x46,0x4E,0x00
|
||||
};
|
||||
// END DO NOT EDIT
|
||||
|
||||
// TO DO: You may add additional code below.
|
||||
|
||||
180
firmware/GN3S_v2/src/vectors.a51
Normal file
180
firmware/GN3S_v2/src/vectors.a51
Normal file
@@ -0,0 +1,180 @@
|
||||
;;; -*- asm -*-
|
||||
;;;
|
||||
;;; Copyright 2003 Free Software Foundation, Inc.
|
||||
;;;
|
||||
;;; This file is part of GNU Radio
|
||||
;;;
|
||||
;;; GNU Radio is free software; you can redistribute it and/or modify
|
||||
;;; it under the terms of the GNU General Public License as published by
|
||||
;;; the Free Software Foundation; either version 2, or (at your option)
|
||||
;;; any later version.
|
||||
;;;
|
||||
;;; GNU Radio is distributed in the hope that it will be useful,
|
||||
;;; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
;;; GNU General Public License for more details.
|
||||
;;;
|
||||
;;; You should have received a copy of the GNU General Public License
|
||||
;;; along with GNU Radio; see the file COPYING. If not, write to
|
||||
;;; the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
|
||||
;;; Boston, MA 02111-1307, USA.
|
||||
;;;
|
||||
|
||||
;;; Interrupt vectors.
|
||||
|
||||
;;; N.B. This object module must come first in the list of modules
|
||||
|
||||
.module vectors
|
||||
|
||||
;;; ----------------------------------------------------------------
|
||||
;;; standard FX2 interrupt vectors
|
||||
;;; ----------------------------------------------------------------
|
||||
|
||||
.area CSEG (CODE)
|
||||
.area GSINIT (CODE)
|
||||
.area CSEG (CODE)
|
||||
__standard_interrupt_vector::
|
||||
__reset_vector::
|
||||
ljmp s_GSINIT
|
||||
|
||||
;; 13 8-byte entries. We point them all at __isr_nop
|
||||
ljmp __isr_nop ; 3 bytes
|
||||
.ds 5 ; + 5 = 8 bytes for vector slot
|
||||
ljmp __isr_nop
|
||||
.ds 5
|
||||
ljmp __isr_nop
|
||||
.ds 5
|
||||
ljmp __isr_nop
|
||||
.ds 5
|
||||
ljmp __isr_nop
|
||||
.ds 5
|
||||
ljmp __isr_nop
|
||||
.ds 5
|
||||
ljmp __isr_nop
|
||||
.ds 5
|
||||
ljmp __isr_nop
|
||||
.ds 5
|
||||
ljmp __isr_nop
|
||||
.ds 5
|
||||
ljmp __isr_nop
|
||||
.ds 5
|
||||
ljmp __isr_nop
|
||||
.ds 5
|
||||
ljmp __isr_nop
|
||||
.ds 5
|
||||
ljmp __isr_nop
|
||||
.ds 5
|
||||
|
||||
__isr_nop::
|
||||
reti
|
||||
|
||||
;;; ----------------------------------------------------------------
|
||||
;;; the FIFO/GPIF autovector. 14 4-byte entries.
|
||||
;;; must start on a 128 byte boundary.
|
||||
;;; ----------------------------------------------------------------
|
||||
|
||||
. = __reset_vector + 0x0080
|
||||
|
||||
__fifo_gpif_autovector::
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
|
||||
|
||||
;;; ----------------------------------------------------------------
|
||||
;;; the USB autovector. 32 4-byte entries.
|
||||
;;; must start on a 256 byte boundary.
|
||||
;;; ----------------------------------------------------------------
|
||||
|
||||
. = __reset_vector + 0x0100
|
||||
|
||||
__usb_autovector::
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
ljmp __isr_nop
|
||||
nop
|
||||
Reference in New Issue
Block a user