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https://github.com/gnss-sdr/gnss-sdr
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Remove redundant parameter SignalSource.enable_FPGA
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c2223e3dad
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@ -519,19 +519,9 @@ int GNSSFlowgraph::connect_fpga_flowgraph()
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// Connect the counter
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// Connect the counter
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if (sig_source_.at(0) != nullptr)
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if (sig_source_.at(0) != nullptr)
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{
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{
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if (configuration_->property(sig_source_.at(0)->role() + ".enable_FPGA", false) == false)
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if (connect_fpga_sample_counter() != 0)
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{
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{
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if (connect_sample_counter() != 0)
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return 1;
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{
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return 1;
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}
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}
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else
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{
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if (connect_fpga_sample_counter() != 0)
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{
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return 1;
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}
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}
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}
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}
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}
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else
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else
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@ -546,11 +536,6 @@ int GNSSFlowgraph::connect_fpga_flowgraph()
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return 1;
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return 1;
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}
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}
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if (configuration_->property(sig_source_.at(0)->role() + ".enable_FPGA", false) == false)
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{
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check_signal_conditioners();
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}
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assign_channels();
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assign_channels();
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if (connect_observables_to_pvt() != 0)
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if (connect_observables_to_pvt() != 0)
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@ -572,27 +557,9 @@ int GNSSFlowgraph::connect_fpga_flowgraph()
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int GNSSFlowgraph::disconnect_fpga_flowgraph()
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int GNSSFlowgraph::disconnect_fpga_flowgraph()
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{
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{
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if (configuration_->property(sig_source_.at(0)->role() + ".enable_FPGA", false) == false)
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if (disconnect_fpga_sample_counter() != 0)
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{
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{
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if (disconnect_signal_sources_from_signal_conditioners() != 0)
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return 1;
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{
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return 1;
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}
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}
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if (configuration_->property(sig_source_.at(0)->role() + ".enable_FPGA", false) == false)
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{
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if (disconnect_sample_counter() != 0)
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{
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return 1;
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}
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}
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else
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{
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if (disconnect_fpga_sample_counter() != 0)
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{
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return 1;
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}
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}
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}
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if (disconnect_monitors() != 0)
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if (disconnect_monitors() != 0)
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