From b4d9a3a84b8d1eae7f6e564fefc5a37fe1634f8e Mon Sep 17 00:00:00 2001
From: Carles Fernandez <carles.fernandez@gmail.com>
Date: Tue, 23 Feb 2021 12:24:21 +0100
Subject: [PATCH] Remove redundant parameter SignalSource.enable_FPGA

---
 src/core/receiver/gnss_flowgraph.cc | 41 +++--------------------------
 1 file changed, 4 insertions(+), 37 deletions(-)

diff --git a/src/core/receiver/gnss_flowgraph.cc b/src/core/receiver/gnss_flowgraph.cc
index dbcf1fe5d..e8f5ac03f 100644
--- a/src/core/receiver/gnss_flowgraph.cc
+++ b/src/core/receiver/gnss_flowgraph.cc
@@ -519,19 +519,9 @@ int GNSSFlowgraph::connect_fpga_flowgraph()
     // Connect the counter
     if (sig_source_.at(0) != nullptr)
         {
-            if (configuration_->property(sig_source_.at(0)->role() + ".enable_FPGA", false) == false)
+            if (connect_fpga_sample_counter() != 0)
                 {
-                    if (connect_sample_counter() != 0)
-                        {
-                            return 1;
-                        }
-                }
-            else
-                {
-                    if (connect_fpga_sample_counter() != 0)
-                        {
-                            return 1;
-                        }
+                    return 1;
                 }
         }
     else
@@ -546,11 +536,6 @@ int GNSSFlowgraph::connect_fpga_flowgraph()
             return 1;
         }
 
-    if (configuration_->property(sig_source_.at(0)->role() + ".enable_FPGA", false) == false)
-        {
-            check_signal_conditioners();
-        }
-
     assign_channels();
 
     if (connect_observables_to_pvt() != 0)
@@ -572,27 +557,9 @@ int GNSSFlowgraph::connect_fpga_flowgraph()
 
 int GNSSFlowgraph::disconnect_fpga_flowgraph()
 {
-    if (configuration_->property(sig_source_.at(0)->role() + ".enable_FPGA", false) == false)
+    if (disconnect_fpga_sample_counter() != 0)
         {
-            if (disconnect_signal_sources_from_signal_conditioners() != 0)
-                {
-                    return 1;
-                }
-        }
-
-    if (configuration_->property(sig_source_.at(0)->role() + ".enable_FPGA", false) == false)
-        {
-            if (disconnect_sample_counter() != 0)
-                {
-                    return 1;
-                }
-        }
-    else
-        {
-            if (disconnect_fpga_sample_counter() != 0)
-                {
-                    return 1;
-                }
+            return 1;
         }
 
     if (disconnect_monitors() != 0)