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mirror of https://github.com/gnss-sdr/gnss-sdr synced 2025-06-10 18:44:10 +00:00

Use lock_guard instead of unique_lock

This commit is contained in:
Carles Fernandez 2024-08-18 10:57:40 +02:00
parent 9b393098a6
commit 7aa19d9642
No known key found for this signature in database
GPG Key ID: 4C583C52B0C3877D
6 changed files with 52 additions and 64 deletions

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@ -1,6 +1,6 @@
/*! /*!
* \file adrv9361_z7035_signal_source_fpga.cc * \file adrv9361_z7035_signal_source_fpga.cc
* \brief signal source for the Analog Devices ADRV9361-Z7035 evaluation board * \brief Signal source for the Analog Devices ADRV9361-Z7035 evaluation board
* directly connected to the FPGA accelerators. * directly connected to the FPGA accelerators.
* This source implements only the AD9361 control. It is NOT compatible with * This source implements only the AD9361 control. It is NOT compatible with
* conventional SDR acquisition and tracking blocks. * conventional SDR acquisition and tracking blocks.
@ -257,7 +257,6 @@ Adrv9361z7035SignalSourceFPGA::Adrv9361z7035SignalSourceFPGA(const Configuration
buffer_monitor_fpga = std::make_shared<Fpga_buffer_monitor>(num_freq_bands, dump_, dump_filename); buffer_monitor_fpga = std::make_shared<Fpga_buffer_monitor>(num_freq_bands, dump_, dump_filename);
thread_buffer_monitor = std::thread([&] { run_buffer_monitor_process(); }); thread_buffer_monitor = std::thread([&] { run_buffer_monitor_process(); });
// dynamic bits selection // dynamic bits selection
if (enable_dynamic_bit_selection_) if (enable_dynamic_bit_selection_)
{ {
@ -278,8 +277,7 @@ Adrv9361z7035SignalSourceFPGA::Adrv9361z7035SignalSourceFPGA(const Configuration
Adrv9361z7035SignalSourceFPGA::~Adrv9361z7035SignalSourceFPGA() Adrv9361z7035SignalSourceFPGA::~Adrv9361z7035SignalSourceFPGA()
{ {
/* cleanup and exit */ // cleanup and exit
if (rf_shutdown_) if (rf_shutdown_)
{ {
std::cout << "* AD9361 Disabling RX streaming channels\n"; std::cout << "* AD9361 Disabling RX streaming channels\n";
@ -301,24 +299,27 @@ Adrv9361z7035SignalSourceFPGA::~Adrv9361z7035SignalSourceFPGA()
} }
// disable buffer overflow checking and buffer monitoring // disable buffer overflow checking and buffer monitoring
std::unique_lock<std::mutex> lock_buffer_monitor(buffer_monitor_mutex); {
std::lock_guard<std::mutex> lock_buffer_monitor(buffer_monitor_mutex);
enable_ovf_check_buffer_monitor_active_ = false; enable_ovf_check_buffer_monitor_active_ = false;
lock_buffer_monitor.unlock(); }
if (thread_buffer_monitor.joinable()) if (thread_buffer_monitor.joinable())
{ {
thread_buffer_monitor.join(); thread_buffer_monitor.join();
} }
bool bit_selection_enabled = false;
std::unique_lock<std::mutex> lock_dyn_bit_sel(dynamic_bit_selection_mutex); {
bool bit_selection_enabled = enable_dynamic_bit_selection_; std::lock_guard<std::mutex> lock_dyn_bit_sel(dynamic_bit_selection_mutex);
lock_dyn_bit_sel.unlock(); bit_selection_enabled = enable_dynamic_bit_selection_;
}
if (bit_selection_enabled == true) if (bit_selection_enabled == true)
{ {
std::unique_lock<std::mutex> lock(dynamic_bit_selection_mutex); {
std::lock_guard<std::mutex> lock(dynamic_bit_selection_mutex);
enable_dynamic_bit_selection_ = false; enable_dynamic_bit_selection_ = false;
lock.unlock(); }
if (thread_dynamic_bit_selection.joinable()) if (thread_dynamic_bit_selection.joinable())
{ {
@ -337,12 +338,11 @@ void Adrv9361z7035SignalSourceFPGA::run_dynamic_bit_selection_process()
// setting the bit selection to the top bits // setting the bit selection to the top bits
dynamic_bit_selection_fpga->bit_selection(); dynamic_bit_selection_fpga->bit_selection();
std::this_thread::sleep_for(std::chrono::milliseconds(Gain_control_period_ms)); std::this_thread::sleep_for(std::chrono::milliseconds(Gain_control_period_ms));
std::unique_lock<std::mutex> lock(dynamic_bit_selection_mutex); std::lock_guard<std::mutex> lock(dynamic_bit_selection_mutex);
if (enable_dynamic_bit_selection_ == false) if (enable_dynamic_bit_selection_ == false)
{ {
dynamic_bit_selection_active = false; dynamic_bit_selection_active = false;
} }
lock.unlock();
} }
} }
@ -357,12 +357,11 @@ void Adrv9361z7035SignalSourceFPGA::run_buffer_monitor_process()
{ {
buffer_monitor_fpga->check_buffer_overflow_and_monitor_buffer_status(); buffer_monitor_fpga->check_buffer_overflow_and_monitor_buffer_status();
std::this_thread::sleep_for(std::chrono::milliseconds(buffer_monitor_period_ms)); std::this_thread::sleep_for(std::chrono::milliseconds(buffer_monitor_period_ms));
std::unique_lock<std::mutex> lock(buffer_monitor_mutex); std::lock_guard<std::mutex> lock(buffer_monitor_mutex);
if (enable_ovf_check_buffer_monitor_active_ == false) if (enable_ovf_check_buffer_monitor_active_ == false)
{ {
enable_ovf_check_buffer_monitor_active = false; enable_ovf_check_buffer_monitor_active = false;
} }
lock.unlock();
} }
} }

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@ -1,6 +1,6 @@
/*! /*!
* \file adrv9361_z7035_signal_source_fpga.h * \file adrv9361_z7035_signal_source_fpga.h
* \brief signal source for the Analog Devices ADRV9361-Z7035 evaluation board * \brief Signal source for the Analog Devices ADRV9361-Z7035 evaluation board
* directly connected to the FPGA accelerators. * directly connected to the FPGA accelerators.
* This source implements only the AD9361 control. It is NOT compatible with * This source implements only the AD9361 control. It is NOT compatible with
* conventional SDR acquisition and tracking blocks. * conventional SDR acquisition and tracking blocks.
@ -78,13 +78,14 @@ private:
const uint32_t buffer_monitor_period_ms = 1000; const uint32_t buffer_monitor_period_ms = 1000;
// buffer overflow and buffer monitoring initial delay // buffer overflow and buffer monitoring initial delay
const uint32_t buffer_monitoring_initial_delay_ms = 2000; const uint32_t buffer_monitoring_initial_delay_ms = 2000;
// sample block size when running in post-processing mode
const int sample_block_size = 16384;
const int32_t switch_to_real_time_mode = 2; const int32_t switch_to_real_time_mode = 2;
void run_dynamic_bit_selection_process(); void run_dynamic_bit_selection_process();
void run_buffer_monitor_process(); void run_buffer_monitor_process();
mutable std::mutex dynamic_bit_selection_mutex;
mutable std::mutex buffer_monitor_mutex;
std::thread thread_dynamic_bit_selection; std::thread thread_dynamic_bit_selection;
std::thread thread_buffer_monitor; std::thread thread_buffer_monitor;
@ -92,9 +93,6 @@ private:
std::shared_ptr<Fpga_dynamic_bit_selection> dynamic_bit_selection_fpga; std::shared_ptr<Fpga_dynamic_bit_selection> dynamic_bit_selection_fpga;
std::shared_ptr<Fpga_buffer_monitor> buffer_monitor_fpga; std::shared_ptr<Fpga_buffer_monitor> buffer_monitor_fpga;
std::mutex dynamic_bit_selection_mutex;
std::mutex buffer_monitor_mutex;
std::string gain_mode_rx1_; std::string gain_mode_rx1_;
std::string gain_mode_rx2_; std::string gain_mode_rx2_;
std::string rf_port_select_; std::string rf_port_select_;

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@ -1,6 +1,6 @@
/*! /*!
* \file fmcomms5_signal_source_fpga.cc * \file fmcomms5_signal_source_fpga.cc
* \brief signal source for the Analog Devices FMCOMMS5 directly connected * \brief Signal source for the Analog Devices FMCOMMS5 directly connected
* to the FPGA accelerators. * to the FPGA accelerators.
* This source implements only the AD9361 control. It is NOT compatible with * This source implements only the AD9361 control. It is NOT compatible with
* conventional SDR acquisition and tracking blocks. * conventional SDR acquisition and tracking blocks.
@ -217,7 +217,6 @@ Fmcomms5SignalSourceFPGA::Fmcomms5SignalSourceFPGA(const ConfigurationInterface
buffer_monitor_fpga = std::make_shared<Fpga_buffer_monitor>(num_freq_bands, dump_, dump_filename); buffer_monitor_fpga = std::make_shared<Fpga_buffer_monitor>(num_freq_bands, dump_, dump_filename);
thread_buffer_monitor = std::thread([&] { run_buffer_monitor_process(); }); thread_buffer_monitor = std::thread([&] { run_buffer_monitor_process(); });
// dynamic bits selection // dynamic bits selection
if (enable_dynamic_bit_selection_) if (enable_dynamic_bit_selection_)
{ {
@ -238,8 +237,7 @@ Fmcomms5SignalSourceFPGA::Fmcomms5SignalSourceFPGA(const ConfigurationInterface
Fmcomms5SignalSourceFPGA::~Fmcomms5SignalSourceFPGA() Fmcomms5SignalSourceFPGA::~Fmcomms5SignalSourceFPGA()
{ {
/* cleanup and exit */ // cleanup and exit
if (rf_shutdown_) if (rf_shutdown_)
{ {
std::cout << "* Disabling RX streaming channels\n"; std::cout << "* Disabling RX streaming channels\n";
@ -250,24 +248,27 @@ Fmcomms5SignalSourceFPGA::~Fmcomms5SignalSourceFPGA()
} }
// disable buffer overflow checking and buffer monitoring // disable buffer overflow checking and buffer monitoring
std::unique_lock<std::mutex> lock_buffer_monitor(buffer_monitor_mutex); {
std::lock_guard<std::mutex> lock_buffer_monitor(buffer_monitor_mutex);
enable_ovf_check_buffer_monitor_active_ = false; enable_ovf_check_buffer_monitor_active_ = false;
lock_buffer_monitor.unlock(); }
if (thread_buffer_monitor.joinable()) if (thread_buffer_monitor.joinable())
{ {
thread_buffer_monitor.join(); thread_buffer_monitor.join();
} }
bool bit_selection_enabled = false;
std::unique_lock<std::mutex> lock_dyn_bit_sel(dynamic_bit_selection_mutex); {
bool bit_selection_enabled = enable_dynamic_bit_selection_; std::lock_guard<std::mutex> lock_dyn_bit_sel(dynamic_bit_selection_mutex);
lock_dyn_bit_sel.unlock(); bit_selection_enabled = enable_dynamic_bit_selection_;
}
if (bit_selection_enabled == true) if (bit_selection_enabled == true)
{ {
std::unique_lock<std::mutex> lock(dynamic_bit_selection_mutex); {
std::lock_guard<std::mutex> lock(dynamic_bit_selection_mutex);
enable_dynamic_bit_selection_ = false; enable_dynamic_bit_selection_ = false;
lock.unlock(); }
if (thread_dynamic_bit_selection.joinable()) if (thread_dynamic_bit_selection.joinable())
{ {
@ -286,12 +287,11 @@ void Fmcomms5SignalSourceFPGA::run_dynamic_bit_selection_process()
// setting the bit selection to the top bits // setting the bit selection to the top bits
dynamic_bit_selection_fpga->bit_selection(); dynamic_bit_selection_fpga->bit_selection();
std::this_thread::sleep_for(std::chrono::milliseconds(Gain_control_period_ms)); std::this_thread::sleep_for(std::chrono::milliseconds(Gain_control_period_ms));
std::unique_lock<std::mutex> lock(dynamic_bit_selection_mutex); std::lock_guard<std::mutex> lock(dynamic_bit_selection_mutex);
if (enable_dynamic_bit_selection_ == false) if (enable_dynamic_bit_selection_ == false)
{ {
dynamic_bit_selection_active = false; dynamic_bit_selection_active = false;
} }
lock.unlock();
} }
} }
@ -306,12 +306,11 @@ void Fmcomms5SignalSourceFPGA::run_buffer_monitor_process()
{ {
buffer_monitor_fpga->check_buffer_overflow_and_monitor_buffer_status(); buffer_monitor_fpga->check_buffer_overflow_and_monitor_buffer_status();
std::this_thread::sleep_for(std::chrono::milliseconds(buffer_monitor_period_ms)); std::this_thread::sleep_for(std::chrono::milliseconds(buffer_monitor_period_ms));
std::unique_lock<std::mutex> lock(buffer_monitor_mutex); std::lock_guard<std::mutex> lock(buffer_monitor_mutex);
if (enable_ovf_check_buffer_monitor_active_ == false) if (enable_ovf_check_buffer_monitor_active_ == false)
{ {
enable_ovf_check_buffer_monitor_active = false; enable_ovf_check_buffer_monitor_active = false;
} }
lock.unlock();
} }
} }

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@ -1,6 +1,6 @@
/*! /*!
* \file fmcomms5_signal_source_fpga.h * \file fmcomms5_signal_source_fpga.h
* \brief signal source for the Analog Devices FMCOMMS5 directly connected * \brief Signal source for the Analog Devices FMCOMMS5 directly connected
* to the FPGA accelerators. * to the FPGA accelerators.
* This source implements only the AD9361 control. It is NOT compatible with * This source implements only the AD9361 control. It is NOT compatible with
* conventional SDR acquisition and tracking blocks. * conventional SDR acquisition and tracking blocks.
@ -67,7 +67,6 @@ private:
const std::string default_dump_filename = std::string("FPGA_buffer_monitor_dump.dat"); const std::string default_dump_filename = std::string("FPGA_buffer_monitor_dump.dat");
const std::string default_rf_port_select = std::string("A_BALANCED"); const std::string default_rf_port_select = std::string("A_BALANCED");
const std::string default_gain_mode = std::string("slow_attack"); const std::string default_gain_mode = std::string("slow_attack");
const double default_tx_attenuation_db = -10.0;
const double default_manual_gain_rx1 = 64.0; const double default_manual_gain_rx1 = 64.0;
const double default_manual_gain_rx2 = 64.0; const double default_manual_gain_rx2 = 64.0;
const uint64_t default_bandwidth = 12500000; const uint64_t default_bandwidth = 12500000;
@ -78,13 +77,14 @@ private:
const uint32_t buffer_monitor_period_ms = 1000; const uint32_t buffer_monitor_period_ms = 1000;
// buffer overflow and buffer monitoring initial delay // buffer overflow and buffer monitoring initial delay
const uint32_t buffer_monitoring_initial_delay_ms = 2000; const uint32_t buffer_monitoring_initial_delay_ms = 2000;
// sample block size when running in post-processing mode
const int sample_block_size = 16384;
const int32_t switch_to_real_time_mode = 2; const int32_t switch_to_real_time_mode = 2;
void run_dynamic_bit_selection_process(); void run_dynamic_bit_selection_process();
void run_buffer_monitor_process(); void run_buffer_monitor_process();
mutable std::mutex dynamic_bit_selection_mutex;
mutable std::mutex buffer_monitor_mutex;
std::thread thread_dynamic_bit_selection; std::thread thread_dynamic_bit_selection;
std::thread thread_buffer_monitor; std::thread thread_buffer_monitor;
@ -92,9 +92,6 @@ private:
std::shared_ptr<Fpga_dynamic_bit_selection> dynamic_bit_selection_fpga; std::shared_ptr<Fpga_dynamic_bit_selection> dynamic_bit_selection_fpga;
std::shared_ptr<Fpga_buffer_monitor> buffer_monitor_fpga; std::shared_ptr<Fpga_buffer_monitor> buffer_monitor_fpga;
std::mutex dynamic_bit_selection_mutex;
std::mutex buffer_monitor_mutex;
std::string gain_mode_rx1_; std::string gain_mode_rx1_;
std::string gain_mode_rx2_; std::string gain_mode_rx2_;
std::string rf_port_select_; std::string rf_port_select_;

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@ -140,13 +140,11 @@ MAX2771EVKITSignalSourceFPGA::MAX2771EVKITSignalSourceFPGA(const ConfigurationIn
} }
} }
std::vector<uint32_t> MAX2771EVKITSignalSourceFPGA::setup_regs(void) std::vector<uint32_t> MAX2771EVKITSignalSourceFPGA::setup_regs(void)
{ {
std::vector<uint32_t> register_values = std::vector<uint32_t>(MAX2771_NUM_REGS); auto register_values = std::vector<uint32_t>(MAX2771_NUM_REGS);
uint32_t LNA_mode = (LNA_active_) ? 0x0 : 0x2; uint32_t LNA_mode = (LNA_active_) ? 0x0 : 0x2;
uint32_t Filter_Bandwidth; uint32_t Filter_Bandwidth;
switch (bandwidth_) switch (bandwidth_)
@ -376,10 +374,10 @@ bool MAX2771EVKITSignalSourceFPGA::configure(std::vector<uint32_t> register_valu
return 0; return 0;
} }
MAX2771EVKITSignalSourceFPGA::~MAX2771EVKITSignalSourceFPGA() MAX2771EVKITSignalSourceFPGA::~MAX2771EVKITSignalSourceFPGA()
{ {
/* cleanup and exit */ // cleanup and exit
if (rf_shutdown_) if (rf_shutdown_)
{ {
chipen_ = false; chipen_ = false;
@ -392,7 +390,6 @@ MAX2771EVKITSignalSourceFPGA::~MAX2771EVKITSignalSourceFPGA()
return; return;
} }
if (configure(register_values)) if (configure(register_values))
{ {
std::cerr << "Error disabling the MAX2771 device " << '\n'; std::cerr << "Error disabling the MAX2771 device " << '\n';
@ -405,9 +402,10 @@ MAX2771EVKITSignalSourceFPGA::~MAX2771EVKITSignalSourceFPGA()
} }
// disable buffer overflow checking and buffer monitoring // disable buffer overflow checking and buffer monitoring
std::unique_lock<std::mutex> lock_buffer_monitor(buffer_monitor_mutex); {
std::lock_guard<std::mutex> lock_buffer_monitor(buffer_monitor_mutex);
enable_ovf_check_buffer_monitor_active_ = false; enable_ovf_check_buffer_monitor_active_ = false;
lock_buffer_monitor.unlock(); }
if (thread_buffer_monitor.joinable()) if (thread_buffer_monitor.joinable())
{ {
@ -426,12 +424,11 @@ void MAX2771EVKITSignalSourceFPGA::run_buffer_monitor_process()
{ {
buffer_monitor_fpga->check_buffer_overflow_and_monitor_buffer_status(); buffer_monitor_fpga->check_buffer_overflow_and_monitor_buffer_status();
std::this_thread::sleep_for(std::chrono::milliseconds(buffer_monitor_period_ms)); std::this_thread::sleep_for(std::chrono::milliseconds(buffer_monitor_period_ms));
std::unique_lock<std::mutex> lock(buffer_monitor_mutex); std::lock_guard<std::mutex> lock(buffer_monitor_mutex);
if (enable_ovf_check_buffer_monitor_active_ == false) if (enable_ovf_check_buffer_monitor_active_ == false)
{ {
enable_ovf_check_buffer_monitor_active = false; enable_ovf_check_buffer_monitor_active = false;
} }
lock.unlock();
} }
} }

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@ -53,7 +53,6 @@ public:
std::vector<uint32_t> setup_regs(void); std::vector<uint32_t> setup_regs(void);
inline size_t item_size() override inline size_t item_size() override
{ {
return item_size_; return item_size_;
@ -130,14 +129,13 @@ private:
bool configure(std::vector<uint32_t> register_values); bool configure(std::vector<uint32_t> register_values);
void run_buffer_monitor_process(); void run_buffer_monitor_process();
mutable std::mutex buffer_monitor_mutex;
std::thread thread_buffer_monitor; std::thread thread_buffer_monitor;
std::shared_ptr<Fpga_buffer_monitor> buffer_monitor_fpga; std::shared_ptr<Fpga_buffer_monitor> buffer_monitor_fpga;
std::shared_ptr<Fpga_spidev> spidev_fpga; std::shared_ptr<Fpga_spidev> spidev_fpga;
std::mutex buffer_monitor_mutex;
uint64_t freq_; // frequency of local oscillator uint64_t freq_; // frequency of local oscillator
uint64_t sample_rate_; uint64_t sample_rate_;