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mirror of https://github.com/gnss-sdr/gnss-sdr synced 2025-09-12 15:56:02 +00:00

VEML now working with optimizations

This commit is contained in:
Cillian O'Driscoll
2015-10-14 15:44:10 +01:00
parent a3ad3e7f20
commit 625e86c1bc

View File

@@ -260,26 +260,21 @@ void galileo_e1_dll_pll_veml_tracking_cc::update_local_code()
// NOTE: TODO: // NOTE: TODO:
// This is WRONG!!!!! The early should be + and the late should be - // This is WRONG!!!!! The early should be + and the late should be -
// FIXME // FIXME
int64_t very_early_code_phase_fxp = double_to_fxpt64( tcode_half_chips + 2*d_very_early_late_spc_chips ); int64_t very_early_code_phase_fxp = double_to_fxpt64( tcode_half_chips - 2*d_very_early_late_spc_chips );
int64_t early_code_phase_fxp = double_to_fxpt64( tcode_half_chips + 2*d_early_late_spc_chips ); int64_t early_code_phase_fxp = double_to_fxpt64( tcode_half_chips - 2*d_early_late_spc_chips );
int64_t late_code_phase_fxp = double_to_fxpt64( tcode_half_chips - 2*d_early_late_spc_chips ); int64_t late_code_phase_fxp = double_to_fxpt64( tcode_half_chips + 2*d_early_late_spc_chips );
int64_t very_late_code_phase_fxp = double_to_fxpt64( tcode_half_chips - 2*d_very_early_late_spc_chips ); int64_t very_late_code_phase_fxp = double_to_fxpt64( tcode_half_chips + 2*d_very_early_late_spc_chips );
int64_t code_phase_step_fxp = double_to_fxpt64( code_phase_step_half_chips ); int64_t code_phase_step_fxp = double_to_fxpt64( code_phase_step_half_chips );
LOG(INFO) << "Initial code phase: " << very_late_code_phase_fxp << ". "
<< "Integer part: " << (very_late_code_phase_fxp >> 32 ) << ". "
<< "Increment: " << code_phase_step_fxp << ". "
<< "As double: " << static_cast< double >( code_phase_step_fxp ) * std::pow( 2, -32 );
//EPL code generation //EPL code generation
for (int i = 0; i < d_current_prn_length_samples; i++) for (int i = 0; i < d_current_prn_length_samples; i++)
{ {
d_very_early_code[i] = d_ca_code[ 1 + ( very_early_code_phase_fxp >> 32 ) ]; d_very_early_code[i] = d_ca_code[ 2 + ( very_early_code_phase_fxp >> 32 ) ];
d_early_code[i] = d_ca_code[ 1 + ( early_code_phase_fxp >> 32 ) ]; d_early_code[i] = d_ca_code[ 2 + ( early_code_phase_fxp >> 32 ) ];
d_prompt_code[i] = d_ca_code[ 1 + ( prompt_code_phase_fxp >> 32 ) ]; d_prompt_code[i] = d_ca_code[ 2 + ( prompt_code_phase_fxp >> 32 ) ];
d_late_code[i] = d_ca_code[ 1 + ( late_code_phase_fxp >> 32 ) ]; d_late_code[i] = d_ca_code[ 2 + ( late_code_phase_fxp >> 32 ) ];
d_very_late_code[i] = d_ca_code[ 1 + ( very_late_code_phase_fxp >> 32 ) ]; d_very_late_code[i] = d_ca_code[ 2 + ( very_late_code_phase_fxp >> 32 ) ];
very_early_code_phase_fxp += code_phase_step_fxp; very_early_code_phase_fxp += code_phase_step_fxp;
early_code_phase_fxp += code_phase_step_fxp; early_code_phase_fxp += code_phase_step_fxp;
@@ -287,11 +282,6 @@ void galileo_e1_dll_pll_veml_tracking_cc::update_local_code()
late_code_phase_fxp += code_phase_step_fxp; late_code_phase_fxp += code_phase_step_fxp;
very_late_code_phase_fxp += code_phase_step_fxp; very_late_code_phase_fxp += code_phase_step_fxp;
} }
LOG(INFO) << "Final code phase: " << very_early_code_phase_fxp << ". "
<< "Integer part: " << (very_early_code_phase_fxp >> 32 ) << ". "
<< "Increment: " << code_phase_step_fxp << ". "
<< "As double: " << static_cast< double >( code_phase_step_fxp ) * std::pow( 2, -32 );
} }
@@ -370,6 +360,8 @@ int galileo_e1_dll_pll_veml_tracking_cc::general_work (int noutput_items, gr_vec
// Generate local code and carrier replicas (using \hat{f}_d(k-1)) // Generate local code and carrier replicas (using \hat{f}_d(k-1))
update_local_code(); update_local_code();
/*
update_local_carrier(); update_local_carrier();
@@ -387,28 +379,28 @@ int galileo_e1_dll_pll_veml_tracking_cc::general_work (int noutput_items, gr_vec
d_Prompt, d_Prompt,
d_Late, d_Late,
d_Very_Late); d_Very_Late);
*/
gr_complex phase_as_complex( std::cos( d_rem_carr_phase_rad ),
-std::sin( d_rem_carr_phase_rad ) );
//gr_complex phase_as_complex( std::cos( d_rem_carr_phase_rad ), double carrier_doppler_inc_rad = 2.0*M_PI*d_carrier_doppler_hz/d_fs_in;
//-std::sin( d_rem_carr_phase_rad ) );
//double carrier_doppler_inc_rad = 2.0*M_PI*d_carrier_doppler_hz/d_fs_in; gr_complex phase_inc_as_complex( std::cos( carrier_doppler_inc_rad ),
-std::sin( carrier_doppler_inc_rad ) );
//gr_complex phase_inc_as_complex( std::cos( carrier_doppler_inc_rad ), d_correlator.Carrier_rotate_and_VEPL_volk(d_current_prn_length_samples,
//-std::sin( carrier_doppler_inc_rad ) ); in,
//d_correlator.Carrier_rotate_and_VEPL_volk(d_current_prn_length_samples, &phase_as_complex,
//in, phase_inc_as_complex,
//&phase_as_complex, d_very_early_code,
//phase_inc_as_complex, d_early_code,
//d_very_early_code, d_prompt_code,
//d_early_code, d_late_code,
//d_prompt_code, d_very_late_code,
//d_late_code, d_Very_Early,
//d_very_late_code, d_Early,
//d_Very_Early, d_Prompt,
//d_Early, d_Late,
//d_Prompt, d_Very_Late );
//d_Late,
//d_Very_Late );
// ################## PLL ########################################################## // ################## PLL ##########################################################
// PLL discriminator // PLL discriminator