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https://github.com/gnss-sdr/gnss-sdr
synced 2025-09-11 15:26:02 +00:00
VEML now working with optimizations
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@@ -260,26 +260,21 @@ void galileo_e1_dll_pll_veml_tracking_cc::update_local_code()
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// NOTE: TODO:
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// This is WRONG!!!!! The early should be + and the late should be -
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// FIXME
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int64_t very_early_code_phase_fxp = double_to_fxpt64( tcode_half_chips + 2*d_very_early_late_spc_chips );
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int64_t early_code_phase_fxp = double_to_fxpt64( tcode_half_chips + 2*d_early_late_spc_chips );
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int64_t late_code_phase_fxp = double_to_fxpt64( tcode_half_chips - 2*d_early_late_spc_chips );
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int64_t very_late_code_phase_fxp = double_to_fxpt64( tcode_half_chips - 2*d_very_early_late_spc_chips );
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int64_t very_early_code_phase_fxp = double_to_fxpt64( tcode_half_chips - 2*d_very_early_late_spc_chips );
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int64_t early_code_phase_fxp = double_to_fxpt64( tcode_half_chips - 2*d_early_late_spc_chips );
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int64_t late_code_phase_fxp = double_to_fxpt64( tcode_half_chips + 2*d_early_late_spc_chips );
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int64_t very_late_code_phase_fxp = double_to_fxpt64( tcode_half_chips + 2*d_very_early_late_spc_chips );
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int64_t code_phase_step_fxp = double_to_fxpt64( code_phase_step_half_chips );
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LOG(INFO) << "Initial code phase: " << very_late_code_phase_fxp << ". "
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<< "Integer part: " << (very_late_code_phase_fxp >> 32 ) << ". "
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<< "Increment: " << code_phase_step_fxp << ". "
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<< "As double: " << static_cast< double >( code_phase_step_fxp ) * std::pow( 2, -32 );
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//EPL code generation
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for (int i = 0; i < d_current_prn_length_samples; i++)
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{
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d_very_early_code[i] = d_ca_code[ 1 + ( very_early_code_phase_fxp >> 32 ) ];
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d_early_code[i] = d_ca_code[ 1 + ( early_code_phase_fxp >> 32 ) ];
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d_prompt_code[i] = d_ca_code[ 1 + ( prompt_code_phase_fxp >> 32 ) ];
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d_late_code[i] = d_ca_code[ 1 + ( late_code_phase_fxp >> 32 ) ];
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d_very_late_code[i] = d_ca_code[ 1 + ( very_late_code_phase_fxp >> 32 ) ];
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d_very_early_code[i] = d_ca_code[ 2 + ( very_early_code_phase_fxp >> 32 ) ];
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d_early_code[i] = d_ca_code[ 2 + ( early_code_phase_fxp >> 32 ) ];
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d_prompt_code[i] = d_ca_code[ 2 + ( prompt_code_phase_fxp >> 32 ) ];
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d_late_code[i] = d_ca_code[ 2 + ( late_code_phase_fxp >> 32 ) ];
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d_very_late_code[i] = d_ca_code[ 2 + ( very_late_code_phase_fxp >> 32 ) ];
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very_early_code_phase_fxp += code_phase_step_fxp;
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early_code_phase_fxp += code_phase_step_fxp;
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@@ -287,11 +282,6 @@ void galileo_e1_dll_pll_veml_tracking_cc::update_local_code()
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late_code_phase_fxp += code_phase_step_fxp;
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very_late_code_phase_fxp += code_phase_step_fxp;
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}
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LOG(INFO) << "Final code phase: " << very_early_code_phase_fxp << ". "
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<< "Integer part: " << (very_early_code_phase_fxp >> 32 ) << ". "
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<< "Increment: " << code_phase_step_fxp << ". "
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<< "As double: " << static_cast< double >( code_phase_step_fxp ) * std::pow( 2, -32 );
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}
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@@ -370,6 +360,8 @@ int galileo_e1_dll_pll_veml_tracking_cc::general_work (int noutput_items, gr_vec
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// Generate local code and carrier replicas (using \hat{f}_d(k-1))
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update_local_code();
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/*
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update_local_carrier();
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@@ -387,28 +379,28 @@ int galileo_e1_dll_pll_veml_tracking_cc::general_work (int noutput_items, gr_vec
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d_Prompt,
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d_Late,
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d_Very_Late);
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*/
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gr_complex phase_as_complex( std::cos( d_rem_carr_phase_rad ),
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-std::sin( d_rem_carr_phase_rad ) );
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//gr_complex phase_as_complex( std::cos( d_rem_carr_phase_rad ),
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//-std::sin( d_rem_carr_phase_rad ) );
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double carrier_doppler_inc_rad = 2.0*M_PI*d_carrier_doppler_hz/d_fs_in;
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//double carrier_doppler_inc_rad = 2.0*M_PI*d_carrier_doppler_hz/d_fs_in;
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//gr_complex phase_inc_as_complex( std::cos( carrier_doppler_inc_rad ),
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//-std::sin( carrier_doppler_inc_rad ) );
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//d_correlator.Carrier_rotate_and_VEPL_volk(d_current_prn_length_samples,
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//in,
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//&phase_as_complex,
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//phase_inc_as_complex,
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//d_very_early_code,
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//d_early_code,
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//d_prompt_code,
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//d_late_code,
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//d_very_late_code,
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//d_Very_Early,
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//d_Early,
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//d_Prompt,
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//d_Late,
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//d_Very_Late );
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gr_complex phase_inc_as_complex( std::cos( carrier_doppler_inc_rad ),
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-std::sin( carrier_doppler_inc_rad ) );
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d_correlator.Carrier_rotate_and_VEPL_volk(d_current_prn_length_samples,
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in,
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&phase_as_complex,
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phase_inc_as_complex,
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d_very_early_code,
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d_early_code,
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d_prompt_code,
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d_late_code,
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d_very_late_code,
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d_Very_Early,
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d_Early,
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d_Prompt,
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d_Late,
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d_Very_Late );
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// ################## PLL ##########################################################
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// PLL discriminator
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