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Optimizing GPS L1 CA bit transitiion detection by using a bit transition slope pattern in the FPGA

This commit is contained in:
Marc Majoral 2021-09-27 17:44:44 +02:00
parent e185eae133
commit 43c8d6bd43
1 changed files with 3 additions and 3 deletions
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6
src/algorithms/tracking/gnuradio_blocks/dll_pll_veml_tracking_fpga.cc
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@ -131,9 +131,9 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
d_trk_parameters.spc = d_trk_parameters.early_late_space_chips;
d_trk_parameters.y_intercept = 1.0;
// symbol integration: 20 trk symbols (20 ms) = 1 tlm bit
// set the preamble in the secondary code acquisition to obtain tlm symbol synchronization
d_secondary_code_length = static_cast<uint32_t>(GPS_CA_PREAMBLE_LENGTH_SYMBOLS);
d_secondary_code_string = GPS_CA_PREAMBLE_SYMBOLS_STR;
// set the bit transition pattern in secondary code to obtain bit synchronization
d_secondary_code_length = static_cast<uint32_t>(GPS_CA_BIT_TRANSITION_SYMBOLS_LENGTH_SYMBOLS);
d_secondary_code_string = GPS_CA_BIT_TRANSITION_SYMBOLS_STR;
d_symbols_per_bit = GPS_CA_TELEMETRY_SYMBOLS_PER_BIT;
}
else if (d_signal_type == "2S")