1
0
mirror of https://github.com/gnss-sdr/gnss-sdr synced 2024-12-15 12:40:35 +00:00

added support for extended coherent integration in the FPGA. The code still needs to be optimized and cleaned.

This commit is contained in:
Marc Majoral 2019-06-18 18:22:01 +02:00
parent 46979c2197
commit 33d1115246
12 changed files with 1562 additions and 33 deletions

View File

@ -134,6 +134,58 @@ void pcps_acquisition_fpga::set_state(int32_t state)
void pcps_acquisition_fpga::send_positive_acquisition() void pcps_acquisition_fpga::send_positive_acquisition()
{ {
// debug L5
// d_gnss_synchro->Acq_delay_samples = 2694;
// d_gnss_synchro->Acq_doppler_hz = 2650;
// d_gnss_synchro->Acq_samplestamp_samples = 56500224;
// d_gnss_synchro->Flag_valid_word = 0;
// d_gnss_synchro->Flag_valid_pseudorange = 0;
// d_gnss_synchro->Flag_valid_symbol_output = 0;
// d_gnss_synchro->Flag_valid_acquisition = 0;
// d_gnss_synchro->Acq_delay_samples = 10846;
// d_gnss_synchro->Acq_doppler_hz = 2575;
// d_gnss_synchro->Acq_samplestamp_samples = 399605760;
// d_gnss_synchro->Flag_valid_word = 0;
// d_gnss_synchro->Flag_valid_pseudorange = 0;
// d_gnss_synchro->Flag_valid_symbol_output = 0;
// d_gnss_synchro->Flag_valid_acquisition = 0;
// if (d_channel == 0)
// {
// d_gnss_synchro->Acq_delay_samples = 401;
// d_gnss_synchro->Acq_doppler_hz = 2650;
// d_gnss_synchro->Acq_samplestamp_samples = 96591872;
// d_gnss_synchro->Flag_valid_word = 0;
// d_gnss_synchro->Flag_valid_pseudorange = 0;
// d_gnss_synchro->Flag_valid_symbol_output = 0;
// d_gnss_synchro->Flag_valid_acquisition = 0;
// d_gnss_synchro->Acq_delay_samples = 1505;
// d_gnss_synchro->Acq_doppler_hz = 2575;
// d_gnss_synchro->Acq_samplestamp_samples = 194265553;
// d_gnss_synchro->Flag_valid_word = 0;
// d_gnss_synchro->Flag_valid_pseudorange = 0;
// d_gnss_synchro->Flag_valid_symbol_output = 0;
// d_gnss_synchro->Flag_valid_acquisition = 0;
// }
// debug E5a
// d_gnss_synchro->Acq_delay_samples = 2012;
// d_gnss_synchro->Acq_doppler_hz = -1125;
// d_gnss_synchro->Acq_samplestamp_samples = 363462656;
// d_gnss_synchro->Flag_valid_word = 0;
// d_gnss_synchro->Flag_valid_pseudorange = 0;
// d_gnss_synchro->Flag_valid_symbol_output = 0;
// d_gnss_synchro->Flag_valid_acquisition = 0;
// Declare positive acquisition using a message port // Declare positive acquisition using a message port
// 0=STOP_CHANNEL 1=ACQ_SUCCEES 2=ACQ_FAIL // 0=STOP_CHANNEL 1=ACQ_SUCCEES 2=ACQ_FAIL
DLOG(INFO) << "positive acquisition" DLOG(INFO) << "positive acquisition"
@ -146,6 +198,23 @@ void pcps_acquisition_fpga::send_positive_acquisition()
<< ", magnitude " << d_mag << ", magnitude " << d_mag
<< ", input signal power " << d_input_power; << ", input signal power " << d_input_power;
std::cout << "positive acquisition"
<< ", satellite " << d_gnss_synchro->System << " " << d_gnss_synchro->PRN
<< ", sample_stamp " << d_sample_counter
<< ", test statistics value " << d_test_statistics
<< ", test statistics threshold " << d_threshold
<< ", code phase " << d_gnss_synchro->Acq_delay_samples
<< ", doppler " << d_gnss_synchro->Acq_doppler_hz
<< ", magnitude " << d_mag
<< ", input signal power " << d_input_power
<< ", d_gnss_synchro->Acq_samplestamp_samples " << d_gnss_synchro->Acq_samplestamp_samples
<< ", d_gnss_synchro->Flag_valid_word " << d_gnss_synchro->Flag_valid_word
<< ", Flag_valid_pseudorange " << d_gnss_synchro->Flag_valid_pseudorange
<< ", d_gnss_synchro->Flag_valid_symbol_output " << d_gnss_synchro->Flag_valid_symbol_output
<< ", d_gnss_synchro->Flag_valid_acquisition " << d_gnss_synchro->Flag_valid_acquisition
<< std::endl;
//the channel FSM is set, so, notify it directly the positive acquisition to minimize delays //the channel FSM is set, so, notify it directly the positive acquisition to minimize delays
d_channel_fsm.lock()->Event_valid_acquisition(); d_channel_fsm.lock()->Event_valid_acquisition();
} }

View File

@ -303,6 +303,7 @@ void Fpga_Acquisition::close_device()
void Fpga_Acquisition::reset_acquisition(void) void Fpga_Acquisition::reset_acquisition(void)
{ {
//printf("============ resetting the hw now from the acquisition ===============");
d_map_base[8] = RESET_ACQUISITION; // writing a 2 to d_map_base[8] resets the acquisition. This causes a reset of all d_map_base[8] = RESET_ACQUISITION; // writing a 2 to d_map_base[8] resets the acquisition. This causes a reset of all
// the FPGA HW modules including the multicorrelators // the FPGA HW modules including the multicorrelators
} }

View File

@ -280,6 +280,7 @@ GalileoE1DllPllVemlTrackingFpga::GalileoE1DllPllVemlTrackingFpga(
trk_param_fpga.data_codes = d_data_codes; trk_param_fpga.data_codes = d_data_codes;
trk_param_fpga.code_length_chips = GALILEO_E1_B_CODE_LENGTH_CHIPS; trk_param_fpga.code_length_chips = GALILEO_E1_B_CODE_LENGTH_CHIPS;
trk_param_fpga.code_samples_per_chip = code_samples_per_chip; // 2 sample per chip trk_param_fpga.code_samples_per_chip = code_samples_per_chip; // 2 sample per chip
trk_param_fpga.extended_correlation_in_fpga = false;
//################# MAKE TRACKING GNURadio object ################### //################# MAKE TRACKING GNURadio object ###################
tracking_fpga_sc = dll_pll_veml_make_tracking_fpga(trk_param_fpga); tracking_fpga_sc = dll_pll_veml_make_tracking_fpga(trk_param_fpga);
channel_ = 0; channel_ = 0;

View File

@ -262,6 +262,14 @@ GalileoE5aDllPllTrackingFpga::GalileoE5aDllPllTrackingFpga(
trk_param_fpga.data_codes = d_data_codes; trk_param_fpga.data_codes = d_data_codes;
trk_param_fpga.code_length_chips = code_length_chips; trk_param_fpga.code_length_chips = code_length_chips;
trk_param_fpga.code_samples_per_chip = code_samples_per_chip; // 2 sample per chip trk_param_fpga.code_samples_per_chip = code_samples_per_chip; // 2 sample per chip
if (d_track_pilot)
{
trk_param_fpga.extended_correlation_in_fpga = true;
}
else
{
trk_param_fpga.extended_correlation_in_fpga = false;
}
//################# MAKE TRACKING GNURadio object ################### //################# MAKE TRACKING GNURadio object ###################
tracking_fpga_sc = dll_pll_veml_make_tracking_fpga(trk_param_fpga); tracking_fpga_sc = dll_pll_veml_make_tracking_fpga(trk_param_fpga);
channel_ = 0; channel_ = 0;

View File

@ -229,7 +229,7 @@ GpsL1CaDllPllTrackingFpga::GpsL1CaDllPllTrackingFpga(
trk_param_fpga.ca_codes = d_ca_codes; trk_param_fpga.ca_codes = d_ca_codes;
trk_param_fpga.code_length_chips = GPS_L1_CA_CODE_LENGTH_CHIPS; trk_param_fpga.code_length_chips = GPS_L1_CA_CODE_LENGTH_CHIPS;
trk_param_fpga.code_samples_per_chip = 1; // 1 sample per chip trk_param_fpga.code_samples_per_chip = 1; // 1 sample per chip
trk_param_fpga.extended_correlation_in_fpga = false;
//################# MAKE TRACKING GNURadio object ################### //################# MAKE TRACKING GNURadio object ###################
tracking_fpga_sc = dll_pll_veml_make_tracking_fpga(trk_param_fpga); tracking_fpga_sc = dll_pll_veml_make_tracking_fpga(trk_param_fpga);
channel_ = 0; channel_ = 0;

View File

@ -286,6 +286,7 @@ GpsL5DllPllTrackingFpga::GpsL5DllPllTrackingFpga(
trk_param_fpga.data_codes = d_data_codes; trk_param_fpga.data_codes = d_data_codes;
trk_param_fpga.code_length_chips = code_length_chips; trk_param_fpga.code_length_chips = code_length_chips;
trk_param_fpga.code_samples_per_chip = code_samples_per_chip; // 2 sample per chip trk_param_fpga.code_samples_per_chip = code_samples_per_chip; // 2 sample per chip
trk_param_fpga.extended_correlation_in_fpga = true;
tracking_fpga_sc = dll_pll_veml_make_tracking_fpga(trk_param_fpga); tracking_fpga_sc = dll_pll_veml_make_tracking_fpga(trk_param_fpga);
channel_ = 0; channel_ = 0;
DLOG(INFO) << "tracking(" << tracking_fpga_sc->unique_id() << ")"; DLOG(INFO) << "tracking(" << tracking_fpga_sc->unique_id() << ")";

View File

@ -87,9 +87,12 @@ private:
void do_correlation_step(void); void do_correlation_step(void);
void run_dll_pll(); void run_dll_pll();
void update_tracking_vars(); void update_tracking_vars();
void update_tracking_vars_extend_integration_in_FPGA();
void clear_tracking_vars(); void clear_tracking_vars();
void save_correlation_results(); void save_correlation_results();
void save_correlation_results_extended_integration_in_FPGA();
void log_data(bool integrating); void log_data(bool integrating);
void log_data_extended_integration_in_FPGA(bool integrating, bool extended_correlation_in_fpga_enabled);
int32_t save_matfile(); int32_t save_matfile();
//void run_state_2(Gnss_Synchro &current_synchro_data); //void run_state_2(Gnss_Synchro &current_synchro_data);
@ -148,6 +151,9 @@ private:
gr_complex d_L_accu; gr_complex d_L_accu;
gr_complex d_VL_accu; gr_complex d_VL_accu;
// gr_complex d_P_data_accu; // when the extended integration is done in the FPGA we need to accumulate the pilot correlator results too
uint32_t d_num_current_syncrho_repetitions;
gr_complex *d_Prompt_Data; gr_complex *d_Prompt_Data;
double d_code_phase_step_chips; double d_code_phase_step_chips;
@ -158,6 +164,9 @@ private:
boost::circular_buffer<std::pair<double, double>> d_carr_ph_history; boost::circular_buffer<std::pair<double, double>> d_carr_ph_history;
// remaining code phase and carrier phase between tracking loops // remaining code phase and carrier phase between tracking loops
double d_rem_code_phase_samples; double d_rem_code_phase_samples;
double d_rem_code_phase_samples_first;
double d_rem_code_phase_samples_next;
double d_rem_code_phase_samples_prev;
float d_rem_carr_phase_rad; float d_rem_carr_phase_rad;
// PLL and DLL filter library // PLL and DLL filter library
@ -184,8 +193,13 @@ private:
double T_prn_seconds; double T_prn_seconds;
double T_prn_samples; double T_prn_samples;
double K_blk_samples; double K_blk_samples;
double K_blk_samples_prev;
// PRN period in samples // PRN period in samples
int32_t d_current_prn_length_samples; // REPLACED BY d_correlation_length_samples, d_next_integration_length_samples
//int32_t d_current_prn_length_samples;
int32_t d_current_integration_length_samples;
int32_t d_past_integration_length_samples;
// processing samples counters // processing samples counters
uint64_t d_sample_counter; uint64_t d_sample_counter;
uint64_t d_acq_sample_stamp; uint64_t d_acq_sample_stamp;
@ -204,6 +218,9 @@ private:
gr_complex *d_Prompt_buffer; gr_complex *d_Prompt_buffer;
Exponential_Smoother d_cn0_smoother; Exponential_Smoother d_cn0_smoother;
bool d_extended_correlation_in_fpga;
// file dump // file dump
std::ofstream d_dump_file; std::ofstream d_dump_file;
std::string d_dump_filename; std::string d_dump_filename;
@ -212,8 +229,60 @@ private:
// extra // extra
int32_t d_correlation_length_samples; int32_t d_correlation_length_samples;
int32_t d_next_prn_length_samples; //int32_t d_next_prn_length_samples;
int32_t d_next_integration_length_samples;
int32_t d_extended_integration_first_prn_length_samples;
int32_t d_extended_integration_next_prn_length_samples;
double d_extended_integration_first_acc_carrier_phase_rad;
double d_extended_integration_next_acc_carrier_phase_rad_step;
//float d_extended_integration_first_rem_carr_phase_rad;
//float d_extended_integration_next_rem_carr_phase_rad_step;
uint64_t d_sample_counter_next; uint64_t d_sample_counter_next;
// DEBUG STUFF
uint64_t d_current_synchro_data_Tracking_sample_counter[20];
double d_current_synchro_data_Code_phase_samples[20];
double d_current_synchro_data_Carrier_phase_rads[20];
double d_current_synchro_data_Carrier_Doppler_hz[20];
double d_current_synchro_data_CN0_dB_hz[20];
bool d_current_synchro_data_Flag_valid_symbol_output[20];
int32_t d_current_synchro_data_correlation_length_ms[20];
double d_current_synchro_data_Prompt_I[20];
double d_current_synchro_data_Prompt_Q[20];
double T_prn_samples_prev;
int32_t d_actual_blk_length;
bool d_flag_printout;
std::string *d_secondary_code_string_data;
std::string *d_secondary_code_string_pilot;
uint32_t d_secondary_code_length_data;
uint32_t d_secondary_code_length_pilot;
uint32_t d_first_length_secondary_code;
uint32_t d_next_length_secondary_code;
uint32_t d_debug_counter;
uint32_t d_secondary_code_post_apply_counter; // init in set_gnss_synchro
std::string *d_secondary_code_string_post_apply; // init in constructor
uint32_t d_secondary_code_post_apply_length; // init in constructor
bool enable_post_apply_secondary_code;
uint32_t d_secondary_code_debug_counter_whole_bits;
bool d_sc_remodulate_enabled;
bool d_sc_demodulate_enabled;
bool d_sc_prompt_changed;
float debug_d_rem_carr_phase_rad;
uint32_t debug_first_time;
}; };
#endif //GNSS_SDR_DLL_PLL_VEML_TRACKING_FPGA_H #endif //GNSS_SDR_DLL_PLL_VEML_TRACKING_FPGA_H

View File

@ -77,4 +77,5 @@ Dll_Pll_Conf_Fpga::Dll_Pll_Conf_Fpga()
code_samples_per_chip = 0U; code_samples_per_chip = 0U;
ca_codes = nullptr; ca_codes = nullptr;
data_codes = nullptr; data_codes = nullptr;
extended_correlation_in_fpga = false;
} }

View File

@ -83,6 +83,7 @@ public:
uint32_t code_samples_per_chip; uint32_t code_samples_per_chip;
int32_t* ca_codes; int32_t* ca_codes;
int32_t* data_codes; int32_t* data_codes;
bool extended_correlation_in_fpga;
Dll_Pll_Conf_Fpga(); Dll_Pll_Conf_Fpga();
}; };

View File

@ -119,6 +119,9 @@ Fpga_Multicorrelator_8sc::Fpga_Multicorrelator_8sc(int32_t n_correlators,
d_code_samples_per_chip = code_samples_per_chip; d_code_samples_per_chip = code_samples_per_chip;
d_code_length_samples = d_code_length_chips * d_code_samples_per_chip; d_code_length_samples = d_code_length_chips * d_code_samples_per_chip;
d_secondary_code_enabled = false;
DLOG(INFO) << "TRACKING FPGA CLASS CREATED"; DLOG(INFO) << "TRACKING FPGA CLASS CREATED";
} }
@ -206,6 +209,23 @@ void Fpga_Multicorrelator_8sc::Carrier_wipeoff_multicorrelator_resampler(
std::cout << "Tracking_module Read failed to retrieve 4 bytes!" << std::endl; std::cout << "Tracking_module Read failed to retrieve 4 bytes!" << std::endl;
std::cout << "Tracking_module Interrupt number " << irq_count << std::endl; std::cout << "Tracking_module Interrupt number " << irq_count << std::endl;
} }
// release secondary code indices, keep channel locked
if (d_secondary_code_enabled == true)
{
//printf("in the right place\n");
// debug - force reset counter every time
//d_map_base[DROP_SAMPLES_REG_ADDR] = ENABLE_SECONDARY_CODE | INIT_SECONDARY_CODE_ADDRESSES;
d_map_base[DROP_SAMPLES_REG_ADDR] = ENABLE_SECONDARY_CODE; // keep secondary code enabled
// //printf("do not enable secondary code on purpose\n");
// d_map_base[DROP_SAMPLES_REG_ADDR] = 0; // block samples
}
else
{
//printf("in the wrong place\n");
d_map_base[DROP_SAMPLES_REG_ADDR] = 0; // block samples
}
Fpga_Multicorrelator_8sc::read_tracking_gps_results(); Fpga_Multicorrelator_8sc::read_tracking_gps_results();
} }
@ -457,8 +477,10 @@ void Fpga_Multicorrelator_8sc::read_tracking_gps_results(void)
void Fpga_Multicorrelator_8sc::unlock_channel(void) void Fpga_Multicorrelator_8sc::unlock_channel(void)
{ {
// unlock the channel to let the next samples go through // unlock the channel to let the next samples go through
d_map_base[DROP_SAMPLES_REG_ADDR] = 1; // unlock the channel d_map_base[DROP_SAMPLES_REG_ADDR] = DROP_SAMPLES; // unlock the channel and disable secondary codes
d_map_base[STOP_TRACKING_REG_ADDR] = 1; // set the tracking module back to idle d_map_base[STOP_TRACKING_REG_ADDR] = 1; // set the tracking module back to idle
d_secondary_code_enabled = false;
} }
@ -478,3 +500,250 @@ void Fpga_Multicorrelator_8sc::lock_channel(void)
// lock the channel for processing // lock the channel for processing
d_map_base[DROP_SAMPLES_REG_ADDR] = 0; // lock the channel d_map_base[DROP_SAMPLES_REG_ADDR] = 0; // lock the channel
} }
void Fpga_Multicorrelator_8sc::set_secondary_code_lengths(uint32_t secondary_code_0_length, uint32_t secondary_code_1_length)
{
d_secondary_code_0_length = secondary_code_0_length;
d_secondary_code_1_length = secondary_code_1_length;
// debug
//printf("warning extending the code length 0 to 20\n");
//d_secondary_code_0_length = 20;
uint32_t secondary_code_length_0_minus_1 = d_secondary_code_0_length - 1;
uint32_t secondary_code_length_1_minus_1 = d_secondary_code_1_length - 1;
d_map_base[SECONDARY_CODE_LENGTHS_REG_ADDR] = secondary_code_length_1_minus_1*256 + secondary_code_length_0_minus_1;
//std::cout << "setting secondary code lengths : \n";
//std::cout << "initialized correlator 1 sec code length = " << d_secondary_code_1_length << " correlator 0 sec code length = " << d_secondary_code_0_length << std::endl;
}
void Fpga_Multicorrelator_8sc::update_secondary_code_length(uint32_t first_length_secondary_code, uint32_t next_length_secondary_code)
{
d_map_base[FIRST_PRN_LENGTH_MINUS_1_REG_ADDR] = first_length_secondary_code - 1;
d_map_base[NEXT_PRN_LENGTH_MINUS_1_REG_ADDR] = next_length_secondary_code - 1;
//std::cout << " first_length_secondary_code = " << first_length_secondary_code << " next_length_secondary_code = " << next_length_secondary_code << " sum = " << first_length_secondary_code + next_length_secondary_code << std::endl;
}
void Fpga_Multicorrelator_8sc::initialize_secondary_code(uint32_t secondary_code, std::string *secondary_code_string)
{
uint32_t secondary_code_length;
uint32_t reg_addr;
if (secondary_code == 0)
{
secondary_code_length = d_secondary_code_0_length;
reg_addr = PROG_SECONDARY_CODE_0_DATA_REG_ADDR;
}
else
{
secondary_code_length = d_secondary_code_1_length;
reg_addr = PROG_SECONDARY_CODE_1_DATA_REG_ADDR;
}
Fpga_Multicorrelator_8sc::write_secondary_code(secondary_code_length, secondary_code_string, reg_addr);
}
//void Fpga_Multicorrelator_8sc::initialize_secondary_codes(bool track_pilot,
// uint32_t secondary_code_length_data, std::string *secondary_code_string_data,
// uint32_t secondary_code_length_pilot, std::string *secondary_code_string_pilot)
//{
// if (track_pilot)
// {
// // write secondary_code_length_pilot | secondary_code_length_data << 8
// d_map_base[SECONDARY_CODE_LENGTHS_REG_ADDR] = secondary_code_length_pilot + secondary_code_length_data*256;
//
// // write pilot secondary code
// Fpga_Multicorrelator_8sc::write_secondary_code(secondary_code_length_pilot, secondary_code_string_pilot, PROG_SECONDARY_CODE_0_DATA_REG_ADDR);
//
// // write data secondary code
// Fpga_Multicorrelator_8sc::write_secondary_code(secondary_code_length_data, secondary_code_string_pilot, PROG_SECONDARY_CODE_1_DATA_REG_ADDR);
//
// }
// else
// {
// d_map_base[SECONDARY_CODE_LENGTHS_REG_ADDR] = secondary_code_length_data;
//
// // write data secondary code
// Fpga_Multicorrelator_8sc::write_secondary_code(secondary_code_length_data, secondary_code_string_pilot, PROG_SECONDARY_CODE_0_DATA_REG_ADDR);
// }
//
// std::cout << "going to print string " << std::endl;
// std::cout << secondary_code_string_data << std::endl;
//
//
//}
void Fpga_Multicorrelator_8sc::write_secondary_code(uint32_t secondary_code_length, std::string *secondary_code_string, uint32_t reg_addr)
{
uint32_t num_words = ceil(((float) secondary_code_length)/SECONDARY_CODE_WORD_SIZE);
uint32_t last_word_size = secondary_code_length % SECONDARY_CODE_WORD_SIZE;
//uint32_t initial_pointer;
if (last_word_size == 0)
{
last_word_size = SECONDARY_CODE_WORD_SIZE;
}
// debug
//std::cout << "secondary_code_length = " << secondary_code_length << std::endl;
//std::cout << "secondary code string = " << *secondary_code_string << std::endl;
//std::cout << "reg_addr = " << reg_addr << std::endl;
// debug
//std::cout << "num_words = " << num_words << std::endl;
//std::cout << "last_word_size = " << last_word_size << std::endl;
uint32_t write_val = 0U;
uint32_t pow_k;
uint32_t mem_addr;
if (num_words > 1)
{
for (mem_addr = 0; mem_addr < num_words - 1 ;mem_addr++)
{
//std::cout << "------------------------------------------------------ going to write word " << mem_addr << std::endl;
write_val = 0U;
pow_k = 1;
for (unsigned int k=0;k<SECONDARY_CODE_WORD_SIZE;k++)
{
// debug
//std::cout << "reading bit position = " << mem_addr*SECONDARY_CODE_WORD_SIZE + k << std::endl;
//std::cout << "bit shift = " << pow_k << std::endl;
std::string string_tmp(1, secondary_code_string->at(mem_addr*SECONDARY_CODE_WORD_SIZE + k));
write_val = write_val | std::stoi(string_tmp)*pow_k;
// debug
//std::cout << "computing bit k = " << k << " bit k value = "<< std::stoi(string_tmp) << std::endl;
//std::cout << "computing bit k displaced = " << std::stoi(string_tmp)*pow_k << std::endl;
//std::cout << "write val = " << write_val << std::endl;
pow_k = pow_k*2;
}
//std::cout << "writing secondary code reg addr " << reg_addr << "secondary code value " << write_val << std::endl;
// debug
//write_val = 0;
write_val = write_val | mem_addr*SECONDARY_CODE_ADDR_BITS | SECONDARY_CODE_WR_STROBE;
d_map_base[reg_addr] = write_val;
//std::cout << "writing fpga register value " << write_val << std::endl;
// debug
// std::cout << "wrote word " << mem_addr << "value is ";
// while (write_val) {
// if (write_val & 1)
// printf("1");
// else
// printf("0");
//
// write_val >>= 1;
// }
// printf("\n");
}
}
write_val = 0U;
pow_k = 1;
mem_addr = num_words - 1;
//std::cout << "------------------------------------------------------ going to write word " << mem_addr << std::endl;
for (unsigned int k=0;k<last_word_size;k++)
{
// debug
//std::cout << "reading bit position = " << mem_addr*SECONDARY_CODE_WORD_SIZE + k << std::endl;
//std::cout << "bit shift = " << pow_k << std::endl;
std::string string_tmp(1, secondary_code_string->at(mem_addr*SECONDARY_CODE_WORD_SIZE + k));
write_val = write_val | std::stoi(string_tmp)*pow_k;
// debug
//std::cout << "computing bit k = " << k << " bit k value = "<< std::stoi(string_tmp) << std::endl;
//std::cout << "computing bit k displaced = " << std::stoi(string_tmp)*pow_k << std::endl;
//std::cout << "write val = " << write_val << std::endl;
pow_k = pow_k*2;
}
// debug
//write_val = 0;
//std::cout << "writing secondary code reg addr " << reg_addr << "secondary code value " << write_val << std::endl;
write_val = write_val | (mem_addr*SECONDARY_CODE_ADDR_BITS) | (SECONDARY_CODE_WR_STROBE);
d_map_base[reg_addr] = write_val;
//std::cout << "writing fpga register value " << write_val << std::endl;
// // debug
// write_val = write_val | 705200;
// d_map_base[reg_addr] = write_val;
// printf("warning : extending the code length to 20\n");
// std::cout << "writing fpga register value " << write_val << std::endl;
// // debug
// //write_val = (SECONDARY_CODE_WR_STROBE) | 0x00055400;
// write_val = (SECONDARY_CODE_WR_STROBE) | 0x00000155;
// d_map_base[reg_addr] = write_val;
// for (unsigned int k=1;k<5;k++)
// {
// write_val = (k*SECONDARY_CODE_ADDR_BITS) | (SECONDARY_CODE_WR_STROBE) | 0x00055555;
// d_map_base[reg_addr] = write_val;
// }
// // debug
// std::cout << "wrote word " << mem_addr << " value is " << write_val << " = ";
// while (write_val) {
// if (write_val & 1)
// printf("1");
// else
// printf("0");
//
// write_val >>= 1;
// }
// printf("\n");
//printf("\n=============================================================================* END OF THIS\n");
}
//void Fpga_Multicorrelator_8sc::init_secondary_code_indices(void)
//{
// d_map_base[DROP_SAMPLES_REG_ADDR] = 5; // leave channel unlocked, and init
//}
void Fpga_Multicorrelator_8sc::enable_secondary_codes()
{
d_map_base[DROP_SAMPLES_REG_ADDR] = INIT_SECONDARY_CODE_ADDRESSES | ENABLE_SECONDARY_CODE; // enable secondary codes and clear secondary code indices
d_secondary_code_enabled = true;
//std::cout << "enabling secondary codes d_map_base[DROP_SAMPLES_REG_ADDR] = " << (INIT_SECONDARY_CODE_ADDRESSES | ENABLE_SECONDARY_CODE) << std::endl;
// // debug
// printf("do not enable secondary code on purpose\n");
// d_map_base[DROP_SAMPLES_REG_ADDR] = 0;
}
void Fpga_Multicorrelator_8sc::disable_secondary_codes()
{
// this function is to be called before starting the tracking process in order to disable the secondary codes by default
//printf("xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx disabling secondary codes in fpga\n");
d_map_base[DROP_SAMPLES_REG_ADDR] = DROP_SAMPLES;
}

View File

@ -58,6 +58,11 @@
#define PHASE_STEP_RATE_REG_ADDR 22 #define PHASE_STEP_RATE_REG_ADDR 22
#define STOP_TRACKING_REG_ADDR 23 #define STOP_TRACKING_REG_ADDR 23
#define INT_ON_RST_REG_ADDR 24 // cause interrupt on reset to prevent deadlock #define INT_ON_RST_REG_ADDR 24 // cause interrupt on reset to prevent deadlock
#define SECONDARY_CODE_LENGTHS_REG_ADDR 25
#define PROG_SECONDARY_CODE_0_DATA_REG_ADDR 26
#define PROG_SECONDARY_CODE_1_DATA_REG_ADDR 27
#define FIRST_PRN_LENGTH_MINUS_1_REG_ADDR 28
#define NEXT_PRN_LENGTH_MINUS_1_REG_ADDR 29
#define START_FLAG_ADDR 30 #define START_FLAG_ADDR 30
// read-write addresses // read-write addresses
#define TEST_REG_ADDR 31 #define TEST_REG_ADDR 31
@ -67,6 +72,13 @@
#define SAMPLE_COUNTER_REG_ADDR_LSW 13 #define SAMPLE_COUNTER_REG_ADDR_LSW 13
#define SAMPLE_COUNTER_REG_ADDR_MSW 14 #define SAMPLE_COUNTER_REG_ADDR_MSW 14
// FPGA-related constants
#define SECONDARY_CODE_WORD_SIZE 20 // the secondary codes are written in to the FPGA in words of SECONDARY_CODE_WORD_SIZE bits
#define SECONDARY_CODE_WR_STROBE 0x800000 // write strobe position in the secondary code write register
#define SECONDARY_CODE_ADDR_BITS 0x100000 // memory address position in the secondary code write register
#define DROP_SAMPLES 1 // bit 0 of DROP_SAMPLES_REG_ADDR
#define ENABLE_SECONDARY_CODE 2 // bit 1 of DROP_SAMPLES_REG_ADDR
#define INIT_SECONDARY_CODE_ADDRESSES 4 // bit 2 of DROP_SAMPLES_REG_ADDR
/*! /*!
* \brief Class that implements carrier wipe-off and correlators. * \brief Class that implements carrier wipe-off and correlators.
@ -93,6 +105,16 @@ public:
uint64_t read_sample_counter(); uint64_t read_sample_counter();
void lock_channel(void); void lock_channel(void);
void unlock_channel(void); void unlock_channel(void);
// void initialize_secondary_codes(bool track_pilot,
// uint32_t secondary_code_length_data, std::string *secondary_code_string_data,
// uint32_t secondary_code_length_pilot, std::string *secondary_code_string_pilot);
void set_secondary_code_lengths(uint32_t secondary_code_0_length, uint32_t secondary_code_1_length);
void initialize_secondary_code(uint32_t secondary_code, std::string *secondary_code_string);
void update_secondary_code_length(uint32_t first_length_secondary_code, uint32_t next_length_secondary_code);
void enable_secondary_codes();
void disable_secondary_codes();
// void init_secondary_code_indices();
private: private:
gr_complex *d_corr_out; gr_complex *d_corr_out;
@ -139,6 +161,10 @@ private:
uint32_t d_multicorr_type; uint32_t d_multicorr_type;
uint32_t d_secondary_code_0_length;
uint32_t d_secondary_code_1_length;
bool d_secondary_code_enabled;
// private functions // private functions
uint32_t fpga_acquisition_test_register(uint32_t writeval); uint32_t fpga_acquisition_test_register(uint32_t writeval);
void fpga_configure_tracking_gps_local_code(int32_t PRN); void fpga_configure_tracking_gps_local_code(int32_t PRN);
@ -149,6 +175,7 @@ private:
void fpga_launch_multicorrelator_fpga(void); void fpga_launch_multicorrelator_fpga(void);
void read_tracking_gps_results(void); void read_tracking_gps_results(void);
void close_device(void); void close_device(void);
void write_secondary_code(uint32_t secondary_code_length, std::string *secondary_code_string, uint32_t reg_addr);
}; };
#endif /* GNSS_SDR_FPGA_MULTICORRELATOR_H_ */ #endif /* GNSS_SDR_FPGA_MULTICORRELATOR_H_ */