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added support for extended coherent integration in the FPGA. The code still needs to be optimized and cleaned.

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This commit is contained in:
Marc Majoral
2019-06-18 18:22:01 +02:00
parent 46979c2197
commit 33d1115246
12 changed files with 1562 additions and 33 deletions
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69
src/algorithms/acquisition/gnuradio_blocks/pcps_acquisition_fpga.cc
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@@ -134,6 +134,58 @@ void pcps_acquisition_fpga::set_state(int32_t state)
void pcps_acquisition_fpga::send_positive_acquisition()
{
// debug L5
// d_gnss_synchro->Acq_delay_samples = 2694;
// d_gnss_synchro->Acq_doppler_hz = 2650;
// d_gnss_synchro->Acq_samplestamp_samples = 56500224;
// d_gnss_synchro->Flag_valid_word = 0;
// d_gnss_synchro->Flag_valid_pseudorange = 0;
// d_gnss_synchro->Flag_valid_symbol_output = 0;
// d_gnss_synchro->Flag_valid_acquisition = 0;
// d_gnss_synchro->Acq_delay_samples = 10846;
// d_gnss_synchro->Acq_doppler_hz = 2575;
// d_gnss_synchro->Acq_samplestamp_samples = 399605760;
// d_gnss_synchro->Flag_valid_word = 0;
// d_gnss_synchro->Flag_valid_pseudorange = 0;
// d_gnss_synchro->Flag_valid_symbol_output = 0;
// d_gnss_synchro->Flag_valid_acquisition = 0;
// if (d_channel == 0)
// {
// d_gnss_synchro->Acq_delay_samples = 401;
// d_gnss_synchro->Acq_doppler_hz = 2650;
// d_gnss_synchro->Acq_samplestamp_samples = 96591872;
// d_gnss_synchro->Flag_valid_word = 0;
// d_gnss_synchro->Flag_valid_pseudorange = 0;
// d_gnss_synchro->Flag_valid_symbol_output = 0;
// d_gnss_synchro->Flag_valid_acquisition = 0;
// d_gnss_synchro->Acq_delay_samples = 1505;
// d_gnss_synchro->Acq_doppler_hz = 2575;
// d_gnss_synchro->Acq_samplestamp_samples = 194265553;
// d_gnss_synchro->Flag_valid_word = 0;
// d_gnss_synchro->Flag_valid_pseudorange = 0;
// d_gnss_synchro->Flag_valid_symbol_output = 0;
// d_gnss_synchro->Flag_valid_acquisition = 0;
// }
// debug E5a
// d_gnss_synchro->Acq_delay_samples = 2012;
// d_gnss_synchro->Acq_doppler_hz = -1125;
// d_gnss_synchro->Acq_samplestamp_samples = 363462656;
// d_gnss_synchro->Flag_valid_word = 0;
// d_gnss_synchro->Flag_valid_pseudorange = 0;
// d_gnss_synchro->Flag_valid_symbol_output = 0;
// d_gnss_synchro->Flag_valid_acquisition = 0;
// Declare positive acquisition using a message port
// 0=STOP_CHANNEL 1=ACQ_SUCCEES 2=ACQ_FAIL
DLOG(INFO) << "positive acquisition"
@@ -146,6 +198,23 @@ void pcps_acquisition_fpga::send_positive_acquisition()
<< ", magnitude " << d_mag
<< ", input signal power " << d_input_power;
std::cout << "positive acquisition"
<< ", satellite " << d_gnss_synchro->System << " " << d_gnss_synchro->PRN
<< ", sample_stamp " << d_sample_counter
<< ", test statistics value " << d_test_statistics
<< ", test statistics threshold " << d_threshold
<< ", code phase " << d_gnss_synchro->Acq_delay_samples
<< ", doppler " << d_gnss_synchro->Acq_doppler_hz
<< ", magnitude " << d_mag
<< ", input signal power " << d_input_power
<< ", d_gnss_synchro->Acq_samplestamp_samples " << d_gnss_synchro->Acq_samplestamp_samples
<< ", d_gnss_synchro->Flag_valid_word " << d_gnss_synchro->Flag_valid_word
<< ", Flag_valid_pseudorange " << d_gnss_synchro->Flag_valid_pseudorange
<< ", d_gnss_synchro->Flag_valid_symbol_output " << d_gnss_synchro->Flag_valid_symbol_output
<< ", d_gnss_synchro->Flag_valid_acquisition " << d_gnss_synchro->Flag_valid_acquisition
<< std::endl;
//the channel FSM is set, so, notify it directly the positive acquisition to minimize delays
d_channel_fsm.lock()->Event_valid_acquisition();
}

1
src/algorithms/acquisition/libs/fpga_acquisition.cc
View File

@@ -303,6 +303,7 @@ void Fpga_Acquisition::close_device()
void Fpga_Acquisition::reset_acquisition(void)
{
//printf("============ resetting the hw now from the acquisition ===============");
d_map_base[8] = RESET_ACQUISITION; // writing a 2 to d_map_base[8] resets the acquisition. This causes a reset of all
// the FPGA HW modules including the multicorrelators
}