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Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into DMA

This commit is contained in:
Marc Majoral 2022-12-05 19:21:30 +01:00
parent 4ce4682ea8 44aa398ea1
commit 31124ae72b
7 changed files with 51 additions and 75 deletions
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7
src/algorithms/input_filter/gnuradio_blocks/CMakeLists.txt
View File

@ -53,13 +53,6 @@ target_include_directories(input_filter_gr_blocks
${GNSSSDR_SOURCE_DIR}/src/core/interfaces
)
if(LOG4CPP_WITH_OLD_CMAKE)
target_link_libraries(input_filter_gr_blocks
PRIVATE
Log4cpp::log4cpp
)
endif()
if(GNURADIO_USES_STD_POINTERS)
target_compile_definitions(input_filter_gr_blocks
PUBLIC -DGNURADIO_USES_STD_POINTERS=1

14
src/algorithms/libs/glonass_l1_signal_replica.cc
View File

@ -27,18 +27,17 @@ void glonass_l1_ca_code_gen_complex(own::span<std::complex<float>> dest, uint32_
const uint32_t code_length = 511;
std::bitset<code_length> G1{};
auto G1_register = std::bitset<9>{}.set(); // All true
bool feedback1;
bool aux;
uint32_t delay;
uint32_t lcv;
uint32_t lcv2;
bool feedback1;
bool aux;
/* Generate G1 Register */
for (lcv = 0; lcv < code_length; lcv++)
{
G1[lcv] = G1_register[2];
feedback1 = G1_register[4] xor G1_register[0];
feedback1 = G1_register[4] ^ G1_register[0];
for (lcv2 = 0; lcv2 < 8; lcv2++)
{
@ -62,11 +61,6 @@ void glonass_l1_ca_code_gen_complex(own::span<std::complex<float>> dest, uint32_
}
}
/* Set the delay */
delay = code_length;
delay += chip_shift;
delay %= code_length;
/* Generate PRN from G1 and G2 Registers */
for (lcv = 0; lcv < code_length; lcv++)
{
@ -79,8 +73,6 @@ void glonass_l1_ca_code_gen_complex(own::span<std::complex<float>> dest, uint32_
{
dest[lcv] = std::complex<float>(-1, 0);
}
delay++;
delay %= code_length;
}
}

14
src/algorithms/libs/glonass_l2_signal_replica.cc
View File

@ -27,18 +27,17 @@ void glonass_l2_ca_code_gen_complex(own::span<std::complex<float>> dest, uint32_
const uint32_t code_length = 511;
std::bitset<code_length> G1{};
auto G1_register = std::bitset<9>{}.set(); // All true
bool feedback1;
bool aux;
uint32_t delay;
uint32_t lcv;
uint32_t lcv2;
bool feedback1;
bool aux;
/* Generate G1 Register */
for (lcv = 0; lcv < code_length; lcv++)
{
G1[lcv] = G1_register[2];
feedback1 = G1_register[4] xor G1_register[0];
feedback1 = G1_register[4] ^ G1_register[0];
for (lcv2 = 0; lcv2 < 8; lcv2++)
{
@ -62,11 +61,6 @@ void glonass_l2_ca_code_gen_complex(own::span<std::complex<float>> dest, uint32_
}
}
/* Set the delay */
delay = code_length;
delay += chip_shift;
delay %= code_length;
/* Generate PRN from G1 and G2 Registers */
for (lcv = 0; lcv < code_length; lcv++)
{
@ -79,8 +73,6 @@ void glonass_l2_ca_code_gen_complex(own::span<std::complex<float>> dest, uint32_
{
dest[lcv] = std::complex<float>(-1, 0);
}
delay++;
delay %= code_length;
}
}

49
src/algorithms/signal_source/adapters/CMakeLists.txt
View File

@ -6,48 +6,41 @@
# Optional drivers
set(OPT_DRIVER_SOURCES "")
set(OPT_DRIVER_HEADERS "")
if(ENABLE_RAW_UDP AND PCAP_FOUND)
set(OPT_DRIVER_SOURCES ${OPT_DRIVER_SOURCES} custom_udp_signal_source.cc)
set(OPT_DRIVER_HEADERS ${OPT_DRIVER_HEADERS} custom_udp_signal_source.h)
list(APPEND OPT_DRIVER_SOURCES custom_udp_signal_source.cc)
list(APPEND OPT_DRIVER_HEADERS custom_udp_signal_source.h)
endif()
if(ENABLE_PLUTOSDR)
##############################################
# ADALM-PLUTO (Analog Devices Inc.)
##############################################
set(OPT_DRIVER_SOURCES ${OPT_DRIVER_SOURCES} plutosdr_signal_source.cc)
set(OPT_DRIVER_HEADERS ${OPT_DRIVER_HEADERS} plutosdr_signal_source.h)
list(APPEND OPT_DRIVER_SOURCES plutosdr_signal_source.cc)
list(APPEND OPT_DRIVER_HEADERS plutosdr_signal_source.h)
endif()
if(ENABLE_FMCOMMS2)
###############################################
# FMCOMMS2 based SDR Hardware
###############################################
set(OPT_DRIVER_SOURCES ${OPT_DRIVER_SOURCES} fmcomms2_signal_source.cc)
set(OPT_DRIVER_HEADERS ${OPT_DRIVER_HEADERS} fmcomms2_signal_source.h)
list(APPEND OPT_DRIVER_SOURCES fmcomms2_signal_source.cc)
list(APPEND OPT_DRIVER_HEADERS fmcomms2_signal_source.h)
endif()
if(ENABLE_AD9361)
###############################################
# AD9361 DIRECT TO FPGA Hardware
###############################################
set(OPT_DRIVER_SOURCES ${OPT_DRIVER_SOURCES} ad9361_fpga_signal_source.cc)
set(OPT_DRIVER_HEADERS ${OPT_DRIVER_HEADERS} ad9361_fpga_signal_source.h)
list(APPEND OPT_DRIVER_SOURCES ad9361_fpga_signal_source.cc)
list(APPEND OPT_DRIVER_HEADERS ad9361_fpga_signal_source.h)
endif()
if(ENABLE_FLEXIBAND AND TELEORBIT_FOUND)
set(OPT_DRIVER_SOURCES ${OPT_DRIVER_SOURCES} flexiband_signal_source.cc)
set(OPT_DRIVER_HEADERS ${OPT_DRIVER_HEADERS} flexiband_signal_source.h)
list(APPEND OPT_DRIVER_SOURCES flexiband_signal_source.cc)
list(APPEND OPT_DRIVER_HEADERS flexiband_signal_source.h)
endif()
if(ENABLE_ARRAY)
##############################################
# DBFCTTC GNSS EXPERIMENTAL ARRAY PROTOTYPE
@ -56,32 +49,30 @@ if(ENABLE_ARRAY)
message(" gr-dbfcttc not found, install it from https://github.com/gnss-sdr/gr-dbfcttc")
message(FATAL_ERROR "gr-dbfcttc required for building gnss-sdr with this option enabled")
endif()
set(OPT_DRIVER_SOURCES ${OPT_DRIVER_SOURCES} raw_array_signal_source.cc)
set(OPT_DRIVER_HEADERS ${OPT_DRIVER_HEADERS} raw_array_signal_source.h)
list(APPEND OPT_DRIVER_SOURCES raw_array_signal_source.cc)
list(APPEND OPT_DRIVER_HEADERS raw_array_signal_source.h)
endif()
if(ENABLE_OSMOSDR)
################################################################################
# OsmoSDR - https://osmocom.org/projects/gr-osmosdr/
################################################################################
if(GROSMOSDR_FOUND)
set(OPT_DRIVER_SOURCES ${OPT_DRIVER_SOURCES} osmosdr_signal_source.cc)
set(OPT_DRIVER_HEADERS ${OPT_DRIVER_HEADERS} osmosdr_signal_source.h)
list(APPEND OPT_DRIVER_SOURCES osmosdr_signal_source.cc)
list(APPEND OPT_DRIVER_HEADERS osmosdr_signal_source.h)
endif()
endif()
if(ENABLE_LIMESDR)
if(GRLIMESDR_FOUND)
set(OPT_DRIVER_SOURCES ${OPT_DRIVER_SOURCES} limesdr_signal_source.cc)
set(OPT_DRIVER_HEADERS ${OPT_DRIVER_HEADERS} limesdr_signal_source.h)
list(APPEND OPT_DRIVER_SOURCES limesdr_signal_source.cc)
list(APPEND OPT_DRIVER_HEADERS limesdr_signal_source.h)
endif()
endif()
if(ENABLE_UHD)
set(OPT_DRIVER_SOURCES ${OPT_DRIVER_SOURCES} uhd_signal_source.cc)
set(OPT_DRIVER_HEADERS ${OPT_DRIVER_HEADERS} uhd_signal_source.h)
list(APPEND OPT_DRIVER_SOURCES uhd_signal_source.cc)
list(APPEND OPT_DRIVER_HEADERS uhd_signal_source.h)
endif()
if(ENABLE_ZMQ)
@ -89,7 +80,6 @@ if(ENABLE_ZMQ)
list(APPEND OPT_DRIVER_HEADERS zmq_signal_source.h)
endif()
set(SIGNAL_SOURCE_ADAPTER_SOURCES
signal_source_base.cc
file_source_base.cc
@ -218,7 +208,6 @@ if(ENABLE_LIMESDR AND GRLIMESDR_FOUND)
)
endif()
if(ENABLE_AD9361 AND LIBIIO_FOUND)
target_link_libraries(signal_source_adapters
PRIVATE
@ -302,8 +291,6 @@ target_compile_definitions(signal_source_adapters
PRIVATE -DGNSSSDR_INSTALL_DIR="${CMAKE_INSTALL_PREFIX}"
)
set_property(TARGET signal_source_adapters
APPEND PROPERTY INTERFACE_INCLUDE_DIRECTORIES
$<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}>

6
src/algorithms/signal_source/adapters/spir_gss6450_file_signal_source.cc
View File

@ -190,7 +190,6 @@ void SpirGSS6450FileSignalSource::connect(gr::top_block_sptr top_block)
if (n_channels_ > 1)
{
uint32_t aux = 0;
for (int32_t i = 0; i < n_channels_; i++)
{
if (i != (sel_ch_ - 1))
@ -204,8 +203,6 @@ void SpirGSS6450FileSignalSource::connect(gr::top_block_sptr top_block)
{
top_block->connect(deint_, i, unpack_spir_vec_.at(i), 0);
}
aux++;
}
}
}
@ -251,7 +248,6 @@ void SpirGSS6450FileSignalSource::disconnect(gr::top_block_sptr top_block)
}
if (n_channels_ > 1)
{
uint32_t aux = 0;
for (int32_t i = 0; i < n_channels_; i++)
{
if (i != (sel_ch_ - 1))
@ -265,8 +261,6 @@ void SpirGSS6450FileSignalSource::disconnect(gr::top_block_sptr top_block)
{
top_block->disconnect(deint_, i, unpack_spir_vec_.at(i), 0);
}
aux++;
}
}
}

19
src/algorithms/signal_source/gnuradio_blocks/CMakeLists.txt
View File

@ -5,14 +5,11 @@
# SPDX-License-Identifier: BSD-3-Clause
set(OPT_DRIVER_SOURCES "")
set(OPT_DRIVER_HEADERS "")
if(ENABLE_RAW_UDP AND PCAP_FOUND)
set(OPT_DRIVER_SOURCES gr_complex_ip_packet_source.cc)
set(OPT_DRIVER_HEADERS gr_complex_ip_packet_source.h)
list(APPEND OPT_DRIVER_SOURCES gr_complex_ip_packet_source.cc)
list(APPEND OPT_DRIVER_HEADERS gr_complex_ip_packet_source.h)
endif()
set(SIGNAL_SOURCE_GR_BLOCKS_SOURCES
fifo_reader.cc
unpack_byte_2bit_samples.cc
@ -26,7 +23,6 @@ set(SIGNAL_SOURCE_GR_BLOCKS_SOURCES
${OPT_DRIVER_SOURCES}
)
set(SIGNAL_SOURCE_GR_BLOCKS_HEADERS
fifo_reader.h
unpack_byte_2bit_samples.h
@ -134,6 +130,17 @@ else()
)
endif()
if(Boost_VERSION_STRING VERSION_GREATER "1.57.99")
target_compile_definitions(signal_source_gr_blocks
PRIVATE
-DHAS_BOOST_ENDIAN=1
)
target_link_libraries(signal_source_gr_blocks
PRIVATE
Boost::headers
)
endif()
if(ENABLE_CLANG_TIDY)
if(CLANG_TIDY_EXE)
set_target_properties(signal_source_gr_blocks

17
src/algorithms/signal_source/gnuradio_blocks/labsat23_source.cc
View File

@ -32,6 +32,10 @@
#include <sstream>
#include <utility>
#if HAS_BOOST_ENDIAN
#include <boost/endian/conversion.hpp>
#endif
labsat23_source_sptr labsat23_make_source_sptr(const char *signal_file_basename, const std::vector<int> &channel_selector, Concurrent_Queue<pmt::pmt_t> *queue, bool digital_io_enabled)
{
@ -737,7 +741,8 @@ void labsat23_source::decode_ls3w_register(uint64_t input, std::vector<gr_comple
{
std::bitset<64> bs(input);
// Reverse, since register are written to file as 64-bit little endian words
// Earlier samples are written in the MSBs of the register. Bit-reverse the register
// for easier indexing. Note this bit-reverses individual samples as well for quant > 1 bit
for (std::size_t i = 0; i < 32; ++i)
{
bool t = bs[i];
@ -1074,14 +1079,20 @@ int labsat23_source::general_work(int noutput_items,
std::size_t output_pointer = 0;
for (int i = 0; i < registers_to_read; i++)
{
uint64_t read_register = 0ULL;
// Labsat3W writes its 64-bit shift register to files in little endian. Read and convert to host endianness.
#if HAS_BOOST_ENDIAN
binary_input_file.read(reinterpret_cast<char *>(&read_register), sizeof(read_register));
boost::endian::little_to_native_inplace(read_register);
#else
std::array<char, 8> memory_block{};
binary_input_file.read(memory_block.data(), 8);
uint64_t read_register = 0ULL;
for (int k = 7; k >= 0; --k)
{
read_register <<= 8;
read_register |= uint64_t(memory_block[k]);
read_register |= uint64_t(memory_block[k]); // This is buggy if the MSB of the char is set.
}
#endif
if (binary_input_file.gcount() == 8)
{