mirror of
https://github.com/gnss-sdr/gnss-sdr
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98 lines
3.2 KiB
C
98 lines
3.2 KiB
C
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/*
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* USRP - Universal Software Radio Peripheral
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*
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* Copyright (C) 2003,2004 Free Software Foundation, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _USRP_COMMANDS_H_
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#define _USRP_COMMANDS_H_
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#define MAX_EP0_PKTSIZE 64 // max size of EP0 packet on FX2
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// ----------------------------------------------------------------
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// Vendor bmRequestType's
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// ----------------------------------------------------------------
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#define VRT_VENDOR_IN 0xC0
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#define VRT_VENDOR_OUT 0x40
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// ----------------------------------------------------------------
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// USRP Vendor Requests
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//
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// Note that Cypress reserves [0xA0,0xAF].
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// 0xA0 is the firmware load function.
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// ----------------------------------------------------------------
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// IN commands
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#define VRQ_GET_STATUS 0x80
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#define GS_TX_UNDERRUN 0 // wIndexL // returns 1 byte
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#define GS_RX_OVERRUN 1 // wIndexL // returns 1 byte
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#define VRQ_I2C_READ 0x81 // wValueL: i2c address; length: how much to read
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#define VRQ_SPI_READ 0x82 // wValue: optional header bytes
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// wIndexH: enables
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// wIndexL: format
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// len: how much to read
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// OUT commands
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#define VRQ_SET_LED 0x01 // wValueL off/on {0,1}; wIndexL: which {0,1}
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#define VRQ_FPGA_LOAD 0x02
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# define FL_BEGIN 0 // wIndexL: begin fpga programming cycle. stalls if trouble.
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# define FL_XFER 1 // wIndexL: xfer up to 64 bytes of data
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# define FL_END 2 // wIndexL: end programming cycle, check for success.
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// stalls endpoint if trouble.
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#define VRQ_FPGA_WRITE_REG 0x03 // wIndexL: regno; data: 32-bit regval MSB first
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#define VRQ_FPGA_SET_RESET 0x04 // wValueL: {0,1}
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#define VRQ_FPGA_SET_TX_ENABLE 0x05 // wValueL: {0,1}
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#define VRQ_FPGA_SET_RX_ENABLE 0x06 // wValueL: {0,1}
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// see below VRQ_FPGA_SET_{TX,RX}_RESET
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#define VRQ_SET_SLEEP_BITS 0x07 // wValueH: mask; wValueL: bits. set bits given by mask to bits
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# define SLEEP_ADC0 0x01
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# define SLEEP_ADC1 0x02
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# define SLEEP_DAC0 0x04
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# define SLEEP_DAC1 0x08
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#define VRQ_I2C_WRITE 0x08 // wValueL: i2c address; data: data
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#define VRQ_SPI_WRITE 0x09 // wValue: optional header bytes
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// wIndexH: enables
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// wIndexL: format
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// len: how much to write
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#define VRQ_FPGA_SET_TX_RESET 0x0a // wValueL: {0, 1}
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#define VRQ_FPGA_SET_RX_RESET 0x0b // wValueL: {0, 1}
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// -------------------------------------------------------------------
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// we store the hashes at fixed addresses in the FX2 internal memory
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#define USRP_HASH_SLOT_0_ADDR 0xe1e0
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#define USRP_HASH_SLOT_1_ADDR 0xe1f0
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#endif /* _USRP_COMMANDS_H_ */
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