From d9ed9cc3027a693fb4e8f684e01cf3ff7024d12c Mon Sep 17 00:00:00 2001 From: osmarks Date: Thu, 25 Dec 2025 11:40:35 +0000 Subject: [PATCH] =?UTF-8?q?Edit=20=E2=80=98emerald=5Frapids=E2=80=99?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- emerald_rapids.myco | 2 ++ 1 file changed, 2 insertions(+) diff --git a/emerald_rapids.myco b/emerald_rapids.myco index b8650d2..7d64344 100644 --- a/emerald_rapids.myco +++ b/emerald_rapids.myco @@ -1,5 +1,7 @@ Emerald Rapids is [[Intel]]'s fifth generation of "Xeon Scalable" server [[central processing unit|CPU]]s, succeeding [[Sapphire Rapids]]. Emerald Rapids uses the same core design as Sapphire Rapids, but a redesigned chiplet layout (two die instead of four) and much more [[L3 cache]]. +Only the XCC products are materially changed; lower-core-count single-chiplet products are mostly the same across generations. + Emerald Rapids uses the [[Eagle Stream]] platform, with 8-channel [[DDR5]] up to 5600MT/s (varies by SKU) and 80 PCIe 5.0 lanes. => https://newsletter.semianalysis.com/p/intel-emerald-rapids-backtracks-on \ No newline at end of file