mirror of https://github.com/gnss-sdr/gnss-sdr
578 lines
21 KiB
C++
578 lines
21 KiB
C++
/*!
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* \file fpga_multicorrelator.cc
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* \brief FPGA vector correlator class
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* \authors <ul>
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* <li> Marc Majoral, 2019. mmajoral(at)cttc.cat
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* <li> Javier Arribas, 2019. jarribas(at)cttc.es
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* </ul>
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*
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* Class that controls and executes a highly optimized vector correlator
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* class in the FPGA
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*
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* -------------------------------------------------------------------------
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*
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* Copyright (C) 2010-2019 (see AUTHORS file for a list of contributors)
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*
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* GNSS-SDR is a software defined Global Navigation
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* Satellite Systems receiver
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*
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* This file is part of GNSS-SDR.
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*
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* GNSS-SDR is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* GNSS-SDR is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GNSS-SDR. If not, see <https://www.gnu.org/licenses/>.
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*
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* -------------------------------------------------------------------------
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*/
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#include "fpga_multicorrelator.h"
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#include <glog/logging.h>
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#include <volk_gnsssdr/volk_gnsssdr.h>
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#include <cmath>
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#include <fcntl.h> // for O_RDWR, O_RSYNC
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#include <string>
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#include <sys/mman.h> // for PROT_READ, PROT_WRITE, MAP_SHARED
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#include <utility>
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#ifndef TEMP_FAILURE_RETRY
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#define TEMP_FAILURE_RETRY(exp) \
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({ \
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decltype(exp) _rc; \
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do \
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{ \
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_rc = (exp); \
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} \
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while (_rc == -1 && errno == EINTR); \
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_rc; \
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})
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#endif
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// floating point math constants related to the parameters that are written in the FPGA
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const float PHASE_CARR_MAX_DIV_PI = 683565275.5764316; // 2^(31)/pi
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const float TWO_PI = 6.283185307179586;
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Fpga_Multicorrelator_8sc::Fpga_Multicorrelator_8sc(int32_t n_correlators,
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const std::string &device_name, int32_t device_base, int32_t *ca_codes, int32_t *data_codes, uint32_t code_length_chips, bool track_pilot,
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uint32_t code_samples_per_chip)
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{
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d_n_correlators = n_correlators;
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d_device_name = device_name;
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d_device_base = device_base;
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d_track_pilot = track_pilot;
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d_device_descriptor = 0;
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d_map_base = nullptr;
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// instantiate variable length vectors
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if (d_track_pilot)
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{
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d_initial_index = static_cast<uint32_t *>(volk_gnsssdr_malloc(
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(n_correlators + 1) * sizeof(uint32_t), volk_gnsssdr_get_alignment()));
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d_initial_interp_counter = static_cast<uint32_t *>(volk_gnsssdr_malloc(
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(n_correlators + 1) * sizeof(uint32_t), volk_gnsssdr_get_alignment()));
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}
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else
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{
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d_initial_index = static_cast<uint32_t *>(volk_gnsssdr_malloc(
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n_correlators * sizeof(uint32_t), volk_gnsssdr_get_alignment()));
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d_initial_interp_counter = static_cast<uint32_t *>(volk_gnsssdr_malloc(
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n_correlators * sizeof(uint32_t), volk_gnsssdr_get_alignment()));
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}
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d_shifts_chips = nullptr;
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d_prompt_data_shift = nullptr;
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d_Prompt_Data = nullptr;
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d_corr_out = nullptr;
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d_code_length_chips = 0;
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d_rem_code_phase_chips = 0;
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d_code_phase_step_chips = 0;
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d_rem_carrier_phase_in_rad = 0;
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d_phase_step_rad = 0;
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d_rem_carr_phase_rad_int = 0;
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d_phase_step_rad_int = 0;
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d_initial_sample_counter = 0;
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d_channel = 0;
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d_correlator_length_samples = 0;
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d_code_phase_step_chips_num = 0;
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d_code_length_chips = code_length_chips;
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d_ca_codes = ca_codes;
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d_data_codes = data_codes;
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d_code_samples_per_chip = code_samples_per_chip;
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d_code_length_samples = d_code_length_chips * d_code_samples_per_chip;
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d_secondary_code_enabled = false;
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DLOG(INFO) << "TRACKING FPGA CLASS CREATED";
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}
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Fpga_Multicorrelator_8sc::~Fpga_Multicorrelator_8sc()
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{
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close_device();
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if (d_initial_index != nullptr)
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{
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volk_gnsssdr_free(d_initial_index);
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}
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if (d_initial_interp_counter != nullptr)
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{
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volk_gnsssdr_free(d_initial_interp_counter);
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}
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}
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uint64_t Fpga_Multicorrelator_8sc::read_sample_counter()
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{
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uint64_t sample_counter_tmp;
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uint64_t sample_counter_msw_tmp;
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sample_counter_tmp = d_map_base[sample_counter_reg_addr_lsw];
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sample_counter_msw_tmp = d_map_base[sample_counter_reg_addr_msw];
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sample_counter_msw_tmp = sample_counter_msw_tmp << 32;
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sample_counter_tmp = sample_counter_tmp + sample_counter_msw_tmp; // 2^32
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return sample_counter_tmp;
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}
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void Fpga_Multicorrelator_8sc::set_initial_sample(uint64_t samples_offset)
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{
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d_initial_sample_counter = samples_offset;
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d_map_base[initial_counter_value_reg_addr_lsw] = (d_initial_sample_counter & 0xFFFFFFFF);
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d_map_base[initial_counter_value_reg_addr_msw] = (d_initial_sample_counter >> 32) & 0xFFFFFFFF;
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}
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void Fpga_Multicorrelator_8sc::set_local_code_and_taps(float *shifts_chips, float *prompt_data_shift, int32_t PRN)
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{
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d_shifts_chips = shifts_chips;
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d_prompt_data_shift = prompt_data_shift;
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Fpga_Multicorrelator_8sc::fpga_configure_tracking_gps_local_code(PRN);
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}
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void Fpga_Multicorrelator_8sc::set_output_vectors(gr_complex *corr_out, gr_complex *Prompt_Data)
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{
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d_corr_out = corr_out;
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d_Prompt_Data = Prompt_Data;
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}
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void Fpga_Multicorrelator_8sc::update_local_code()
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{
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Fpga_Multicorrelator_8sc::fpga_compute_code_shift_parameters();
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Fpga_Multicorrelator_8sc::fpga_configure_code_parameters_in_fpga();
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}
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void Fpga_Multicorrelator_8sc::Carrier_wipeoff_multicorrelator_resampler(
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float rem_carrier_phase_in_rad, // nco phase initial position
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float phase_step_rad, // nco phase step
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float carrier_phase_rate_step_rad __attribute__((unused)), // nco phase step rate change
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float rem_code_phase_chips, // code resampler initial position
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float code_phase_step_chips __attribute__((unused)), // code resampler step
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float code_phase_rate_step_chips __attribute__((unused)), // code resampler step rate
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int32_t signal_length_samples) // number of samples
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{
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d_rem_carrier_phase_in_rad = rem_carrier_phase_in_rad; // nco phase initial position
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d_phase_step_rad = phase_step_rad; // nco phase step
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d_carrier_phase_rate_step_rad = carrier_phase_rate_step_rad; // nco phase step rate
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d_rem_code_phase_chips = rem_code_phase_chips; // code resampler initial position
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d_code_phase_step_chips = code_phase_step_chips; // code resampler step
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d_code_phase_rate_step_chips = code_phase_rate_step_chips; // code resampler step rate
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d_correlator_length_samples = signal_length_samples; // number of samples
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Fpga_Multicorrelator_8sc::update_local_code();
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Fpga_Multicorrelator_8sc::fpga_compute_signal_parameters_in_fpga();
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Fpga_Multicorrelator_8sc::fpga_configure_signal_parameters_in_fpga();
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Fpga_Multicorrelator_8sc::fpga_launch_multicorrelator_fpga();
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int32_t irq_count;
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ssize_t nb;
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nb = read(d_device_descriptor, &irq_count, sizeof(irq_count));
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if (nb != sizeof(irq_count))
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{
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std::cout << "Tracking_module Read failed to retrieve 4 bytes!" << std::endl;
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std::cout << "Tracking_module Interrupt number " << irq_count << std::endl;
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}
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// release secondary code indices, keep channel locked
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if (d_secondary_code_enabled == true)
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{
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d_map_base[drop_samples_reg_addr] = enable_secondary_code; // keep secondary code enabled
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}
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else
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{
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d_map_base[drop_samples_reg_addr] = 0; // block samples
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}
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Fpga_Multicorrelator_8sc::read_tracking_gps_results();
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}
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bool Fpga_Multicorrelator_8sc::free()
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{
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// unlock the channel
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Fpga_Multicorrelator_8sc::unlock_channel();
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// free the FPGA dynamically created variables
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if (d_initial_index != nullptr)
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{
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volk_gnsssdr_free(d_initial_index);
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d_initial_index = nullptr;
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}
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if (d_initial_interp_counter != nullptr)
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{
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volk_gnsssdr_free(d_initial_interp_counter);
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d_initial_interp_counter = nullptr;
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}
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return true;
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}
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void Fpga_Multicorrelator_8sc::set_channel(uint32_t channel)
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{
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char device_io_name[max_length_deviceio_name]; // driver io name
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d_channel = channel;
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// open the device corresponding to the assigned channel
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std::string mergedname;
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std::stringstream devicebasetemp;
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int32_t numdevice = d_device_base + d_channel;
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devicebasetemp << numdevice;
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mergedname = d_device_name + devicebasetemp.str();
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if (mergedname.size() > max_length_deviceio_name)
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{
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mergedname = mergedname.substr(0, max_length_deviceio_name);
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}
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mergedname.copy(device_io_name, mergedname.size() + 1);
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device_io_name[mergedname.size()] = '\0';
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std::cout << "trk device_io_name = " << device_io_name << std::endl;
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if ((d_device_descriptor = open(device_io_name, O_RDWR | O_SYNC)) == -1)
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{
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LOG(WARNING) << "Cannot open deviceio" << device_io_name;
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std::cout << "Cannot open deviceio" << device_io_name << std::endl;
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}
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d_map_base = reinterpret_cast<volatile uint32_t *>(mmap(nullptr, page_size,
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PROT_READ | PROT_WRITE, MAP_SHARED, d_device_descriptor, 0));
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if (d_map_base == reinterpret_cast<void *>(-1))
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{
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LOG(WARNING) << "Cannot map the FPGA tracking module "
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<< d_channel << "into user memory";
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std::cout << "Cannot map deviceio" << device_io_name << std::endl;
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}
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// sanity check: check test register
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uint32_t writeval = test_register_track_writeval;
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uint32_t readval;
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readval = Fpga_Multicorrelator_8sc::fpga_acquisition_test_register(writeval);
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if (writeval != readval)
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{
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LOG(WARNING) << "Test register sanity check failed";
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std::cout << "Tracking test register sanity check failed" << std::endl;
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}
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else
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{
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LOG(INFO) << "Test register sanity check success !";
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}
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}
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uint32_t Fpga_Multicorrelator_8sc::fpga_acquisition_test_register(
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uint32_t writeval)
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{
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uint32_t readval = 0;
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// write value to test register
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d_map_base[test_reg_addr] = writeval;
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// read value from test register
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readval = d_map_base[test_reg_addr];
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// return read value
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return readval;
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}
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void Fpga_Multicorrelator_8sc::fpga_configure_tracking_gps_local_code(int32_t PRN)
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{
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uint32_t k;
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d_map_base[prog_mems_addr] = local_code_fpga_clear_address_counter;
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for (k = 0; k < d_code_length_samples; k++)
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{
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d_map_base[prog_mems_addr] = d_ca_codes[(d_code_length_samples * (PRN - 1)) + k];
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}
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if (d_track_pilot)
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{
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d_map_base[prog_mems_addr] = local_code_fpga_clear_address_counter;
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for (k = 0; k < d_code_length_samples; k++)
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{
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d_map_base[prog_mems_addr] = d_data_codes[(d_code_length_samples * (PRN - 1)) + k];
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}
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}
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d_map_base[code_length_minus_1_reg_addr] = (d_code_length_samples)-1; // number of samples - 1
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}
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void Fpga_Multicorrelator_8sc::fpga_compute_code_shift_parameters()
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{
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float frac_part; // decimal part
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int32_t dec_part; // fractional part
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for (uint32_t i = 0; i < d_n_correlators; i++)
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{
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dec_part = std::floor(d_shifts_chips[i] - d_rem_code_phase_chips);
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if (dec_part < 0)
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{
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dec_part = dec_part + d_code_length_samples; // % operator does not work as in Matlab with negative numbers
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}
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d_initial_index[i] = dec_part;
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frac_part = fmod(d_shifts_chips[i] - d_rem_code_phase_chips, 1.0);
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if (frac_part < 0)
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{
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frac_part = frac_part + 1.0; // fmod operator does not work as in Matlab with negative numbers
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}
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d_initial_interp_counter[i] = static_cast<uint32_t>(std::floor(max_code_resampler_counter * frac_part));
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}
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if (d_track_pilot)
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{
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dec_part = std::floor(d_prompt_data_shift[0] - d_rem_code_phase_chips);
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if (dec_part < 0)
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{
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dec_part = dec_part + d_code_length_samples; // % operator does not work as in Matlab with negative numbers
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}
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d_initial_index[d_n_correlators] = dec_part;
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frac_part = fmod(d_prompt_data_shift[0] - d_rem_code_phase_chips, 1.0);
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if (frac_part < 0)
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{
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frac_part = frac_part + 1.0; // fmod operator does not work as in Matlab with negative numbers
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}
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d_initial_interp_counter[d_n_correlators] = static_cast<uint32_t>(std::floor(max_code_resampler_counter * frac_part));
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}
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}
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void Fpga_Multicorrelator_8sc::fpga_configure_code_parameters_in_fpga()
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{
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for (uint32_t i = 0; i < d_n_correlators; i++)
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{
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d_map_base[initial_index_reg_base_addr + i] = d_initial_index[i];
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d_map_base[initial_interp_counter_reg_base_addr + i] = d_initial_interp_counter[i];
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}
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if (d_track_pilot)
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{
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d_map_base[initial_index_reg_base_addr + d_n_correlators] = d_initial_index[d_n_correlators];
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d_map_base[initial_interp_counter_reg_base_addr + d_n_correlators] = d_initial_interp_counter[d_n_correlators];
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}
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}
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void Fpga_Multicorrelator_8sc::fpga_compute_signal_parameters_in_fpga()
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{
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float d_rem_carrier_phase_in_rad_temp;
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d_code_phase_step_chips_num = static_cast<uint32_t>(roundf(max_code_resampler_counter * d_code_phase_step_chips));
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d_code_phase_rate_step_chips_num = static_cast<uint32_t>(roundf(max_code_resampler_counter * d_code_phase_rate_step_chips));
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if (d_rem_carrier_phase_in_rad > M_PI)
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{
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d_rem_carrier_phase_in_rad_temp = -TWO_PI + d_rem_carrier_phase_in_rad;
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}
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else if (d_rem_carrier_phase_in_rad < -M_PI)
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{
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d_rem_carrier_phase_in_rad_temp = TWO_PI + d_rem_carrier_phase_in_rad;
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}
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else
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{
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d_rem_carrier_phase_in_rad_temp = d_rem_carrier_phase_in_rad;
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}
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d_rem_carr_phase_rad_int = static_cast<int32_t>(roundf((d_rem_carrier_phase_in_rad_temp)*PHASE_CARR_MAX_DIV_PI));
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d_phase_step_rad_int = static_cast<int32_t>(roundf((d_phase_step_rad)*PHASE_CARR_MAX_DIV_PI)); // the FPGA accepts a range for the phase step between -pi and +pi
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d_carrier_phase_rate_step_rad_int = static_cast<int32_t>(roundf((d_carrier_phase_rate_step_rad)*PHASE_CARR_MAX_DIV_PI));
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}
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void Fpga_Multicorrelator_8sc::fpga_configure_signal_parameters_in_fpga()
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{
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d_map_base[code_phase_step_chips_num_reg_addr] = d_code_phase_step_chips_num; // code phase step
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d_map_base[code_phase_step_chips_rate_reg_addr] = d_code_phase_rate_step_chips_num; // code phase step rate
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d_map_base[nsamples_minus_1_reg_addr] = d_correlator_length_samples - 1; // number of samples
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d_map_base[rem_carr_phase_rad_reg_addr] = d_rem_carr_phase_rad_int; // initial nco phase
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d_map_base[phase_step_rad_reg_addr] = d_phase_step_rad_int; // nco phase step
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d_map_base[phase_step_rate_reg_addr] = d_carrier_phase_rate_step_rad_int; // nco phase step rate
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}
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void Fpga_Multicorrelator_8sc::fpga_launch_multicorrelator_fpga()
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{
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// enable interrupts
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int32_t reenable = 1;
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ssize_t nbytes = TEMP_FAILURE_RETRY(write(d_device_descriptor, reinterpret_cast<void *>(&reenable), sizeof(int32_t)));
|
|
if (nbytes != sizeof(int32_t))
|
|
{
|
|
std::cerr << "Error launching the FPGA multicorrelator" << std::endl;
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|
}
|
|
// writing 1 to reg 14 launches the tracking
|
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d_map_base[start_flag_addr] = 1;
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}
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|
|
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void Fpga_Multicorrelator_8sc::read_tracking_gps_results()
|
|
{
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int32_t readval_real;
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int32_t readval_imag;
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|
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for (uint32_t k = 0; k < d_n_correlators; k++)
|
|
{
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|
readval_real = d_map_base[result_reg_real_base_addr + k];
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readval_imag = d_map_base[result_reg_imag_base_addr + k];
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d_corr_out[k] = gr_complex(readval_real, readval_imag);
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|
}
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|
if (d_track_pilot)
|
|
{
|
|
readval_real = d_map_base[result_reg_real_base_addr + d_n_correlators];
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readval_imag = d_map_base[result_reg_imag_base_addr + d_n_correlators];
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d_Prompt_Data[0] = gr_complex(readval_real, readval_imag);
|
|
}
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|
}
|
|
|
|
|
|
void Fpga_Multicorrelator_8sc::unlock_channel()
|
|
{
|
|
// unlock the channel to let the next samples go through
|
|
d_map_base[drop_samples_reg_addr] = drop_samples; // unlock the channel and disable secondary codes
|
|
d_map_base[stop_tracking_reg_addr] = 1; // set the tracking module back to idle
|
|
|
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d_secondary_code_enabled = false;
|
|
}
|
|
|
|
|
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void Fpga_Multicorrelator_8sc::close_device()
|
|
{
|
|
auto *aux = const_cast<uint32_t *>(d_map_base);
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|
if (munmap(static_cast<void *>(aux), page_size) == -1)
|
|
{
|
|
std::cout << "Failed to unmap memory uio" << std::endl;
|
|
}
|
|
close(d_device_descriptor);
|
|
}
|
|
|
|
|
|
void Fpga_Multicorrelator_8sc::lock_channel()
|
|
{
|
|
// lock the channel for processing
|
|
d_map_base[drop_samples_reg_addr] = 0; // lock the channel
|
|
}
|
|
|
|
|
|
void Fpga_Multicorrelator_8sc::set_secondary_code_lengths(uint32_t secondary_code_0_length, uint32_t secondary_code_1_length)
|
|
{
|
|
d_secondary_code_0_length = secondary_code_0_length;
|
|
d_secondary_code_1_length = secondary_code_1_length;
|
|
|
|
uint32_t secondary_code_length_0_minus_1 = d_secondary_code_0_length - 1;
|
|
uint32_t secondary_code_length_1_minus_1 = d_secondary_code_1_length - 1;
|
|
|
|
d_map_base[secondary_code_lengths_reg_addr] = secondary_code_length_1_minus_1 * 256 + secondary_code_length_0_minus_1;
|
|
}
|
|
|
|
void Fpga_Multicorrelator_8sc::update_prn_code_length(uint32_t first_prn_length, uint32_t next_prn_length)
|
|
{
|
|
d_map_base[first_prn_length_minus_1_reg_addr] = first_prn_length - 1;
|
|
d_map_base[next_prn_length_minus_1_reg_addr] = next_prn_length - 1;
|
|
}
|
|
|
|
void Fpga_Multicorrelator_8sc::initialize_secondary_code(uint32_t secondary_code, std::string *secondary_code_string)
|
|
{
|
|
uint32_t secondary_code_length;
|
|
uint32_t reg_addr;
|
|
if (secondary_code == 0)
|
|
{
|
|
secondary_code_length = d_secondary_code_0_length;
|
|
reg_addr = prog_secondary_code_0_data_reg_addr;
|
|
}
|
|
else
|
|
{
|
|
secondary_code_length = d_secondary_code_1_length;
|
|
reg_addr = prog_secondary_code_1_data_reg_addr;
|
|
}
|
|
Fpga_Multicorrelator_8sc::write_secondary_code(secondary_code_length, secondary_code_string, reg_addr);
|
|
}
|
|
|
|
|
|
void Fpga_Multicorrelator_8sc::write_secondary_code(uint32_t secondary_code_length, std::string *secondary_code_string, uint32_t reg_addr)
|
|
{
|
|
uint32_t num_words = std::ceil(static_cast<float>(secondary_code_length) / secondary_code_word_size);
|
|
uint32_t last_word_size = secondary_code_length % secondary_code_word_size;
|
|
|
|
if (last_word_size == 0)
|
|
{
|
|
last_word_size = secondary_code_word_size;
|
|
}
|
|
|
|
uint32_t write_val = 0U;
|
|
uint32_t pow_k;
|
|
uint32_t mem_addr;
|
|
if (num_words > 1)
|
|
{
|
|
for (mem_addr = 0; mem_addr < num_words - 1; mem_addr++)
|
|
{
|
|
write_val = 0U;
|
|
pow_k = 1;
|
|
for (unsigned int k = 0; k < secondary_code_word_size; k++)
|
|
{
|
|
std::string string_tmp(1, secondary_code_string->at(mem_addr * secondary_code_word_size + k));
|
|
write_val = write_val | std::stoi(string_tmp) * pow_k;
|
|
pow_k = pow_k * 2;
|
|
}
|
|
write_val = write_val | mem_addr * secondary_code_addr_bits | secondary_code_wr_strobe;
|
|
d_map_base[reg_addr] = write_val;
|
|
}
|
|
}
|
|
write_val = 0U;
|
|
pow_k = 1;
|
|
mem_addr = num_words - 1;
|
|
|
|
for (unsigned int k = 0; k < last_word_size; k++)
|
|
{
|
|
std::string string_tmp(1, secondary_code_string->at(mem_addr * secondary_code_word_size + k));
|
|
write_val = write_val | std::stoi(string_tmp) * pow_k;
|
|
pow_k = pow_k * 2;
|
|
}
|
|
|
|
write_val = write_val | (mem_addr * secondary_code_addr_bits) | (secondary_code_wr_strobe);
|
|
d_map_base[reg_addr] = write_val;
|
|
}
|
|
|
|
void Fpga_Multicorrelator_8sc::enable_secondary_codes()
|
|
{
|
|
d_map_base[drop_samples_reg_addr] = init_secondary_code_addresses | enable_secondary_code; // enable secondary codes and clear secondary code indices
|
|
d_secondary_code_enabled = true;
|
|
}
|
|
|
|
void Fpga_Multicorrelator_8sc::disable_secondary_codes()
|
|
{
|
|
// this function is to be called before starting the tracking process in order to disable the secondary codes by default
|
|
d_map_base[drop_samples_reg_addr] = drop_samples;
|
|
}
|